perf/x86/amd: Add support for AMD NB and L2I "uncore" counters
Add support for AMD Family 15h [and above] northbridge performance counters. MSRs 0xc0010240 ~ 0xc0010247 are shared across all cores that share a common northbridge. Add support for AMD Family 16h L2 performance counters. MSRs 0xc0010230 ~ 0xc0010237 are shared across all cores that share a common L2 cache. We do not enable counter overflow interrupts. Sampling mode and per-thread events are not supported. Signed-off-by: Jacob Shin <jacob.shin@amd.com> Cc: Arnaldo Carvalho de Melo <acme@ghostprotocols.net> Cc: Stephane Eranian <eranian@google.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Link: http://lkml.kernel.org/r/20130419213428.GA8229@jshin-Toonie Signed-off-by: Ingo Molnar <mingo@kernel.org>
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@@ -168,6 +168,7 @@
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#define X86_FEATURE_TOPOEXT (6*32+22) /* topology extensions CPUID leafs */
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#define X86_FEATURE_PERFCTR_CORE (6*32+23) /* core performance counter extensions */
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#define X86_FEATURE_PERFCTR_NB (6*32+24) /* NB performance counter extensions */
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#define X86_FEATURE_PERFCTR_L2 (6*32+28) /* L2 performance counter extensions */
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/*
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* Auxiliary flags: Linux defined - For features scattered in various
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@@ -311,6 +312,7 @@ extern const char * const x86_power_flags[32];
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#define cpu_has_pclmulqdq boot_cpu_has(X86_FEATURE_PCLMULQDQ)
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#define cpu_has_perfctr_core boot_cpu_has(X86_FEATURE_PERFCTR_CORE)
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#define cpu_has_perfctr_nb boot_cpu_has(X86_FEATURE_PERFCTR_NB)
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#define cpu_has_perfctr_l2 boot_cpu_has(X86_FEATURE_PERFCTR_L2)
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#define cpu_has_cx8 boot_cpu_has(X86_FEATURE_CX8)
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#define cpu_has_cx16 boot_cpu_has(X86_FEATURE_CX16)
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#define cpu_has_eager_fpu boot_cpu_has(X86_FEATURE_EAGER_FPU)
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