xiaomi-sm8450/android_kernel_xiaomi_sm8450
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

drm/i915: Optimize pipe irq handling on bdw

Browse Source 
We have a per-pipe bit in the master irq control register, so use it.
This allows us to drop the masks for aggregate interrupt bits and be a
bit more explicit in the code. It also removes one indentation level.

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Daniel Vetter
2013-11-07 11:05:40 +01:00
parent 40c499f93f
commit c42664cceb
2 changed files with 20 additions and 25 deletions
Download Patch File Download Diff File Expand all files Collapse all files

40
drivers/gpu/drm/i915/i915_irq.c
View File

@@ -1749,6 +1749,7 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
u32 master_ctl;
irqreturn_t ret = IRQ_NONE;
uint32_t tmp = 0;
enum pipe pipe;
atomic_inc(&dev_priv->irq_received);
@@ -1777,31 +1778,28 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
}
}
if (master_ctl & GEN8_DE_IRQS) {
int de_ret = 0;
int pipe;
for_each_pipe(pipe) {
uint32_t pipe_iir;
for_each_pipe(pipe) {
uint32_t pipe_iir;
pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
if (pipe_iir & GEN8_PIPE_VBLANK)
drm_handle_vblank(dev, pipe);
if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
continue;
if (pipe_iir & GEN8_PIPE_FLIP_DONE) {
intel_prepare_page_flip(dev, pipe);
intel_finish_page_flip_plane(dev, pipe);
}
pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
if (pipe_iir & GEN8_PIPE_VBLANK)
drm_handle_vblank(dev, pipe);
if (pipe_iir & GEN8_DE_PIPE_IRQ_ERRORS)
DRM_ERROR("Errors on pipe %c\n", 'A' + pipe);
if (pipe_iir) {
de_ret++;
ret = IRQ_HANDLED;
I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
}
if (pipe_iir & GEN8_PIPE_FLIP_DONE) {
intel_prepare_page_flip(dev, pipe);
intel_finish_page_flip_plane(dev, pipe);
}
if (!de_ret)
if (pipe_iir & GEN8_DE_PIPE_IRQ_ERRORS)
DRM_ERROR("Errors on pipe %c\n", 'A' + pipe);
if (pipe_iir) {
ret = IRQ_HANDLED;
I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
} else
DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
}