xiaomi-sm8450/android_kernel_xiaomi_sm8450
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless

Browse Source 
John says:

--------------------
I apologize for not having sent this sooner.  FWIW, I was in a car
somewhere between Illinois and North Carolina for most of the day
Sunday and Monday... :-)

This is (obviously) the last non-fix pull request for wireless bits
intended for 3.5.  It includes AP support for mwifiex, a variety of HCI
and other updates for NFC, some brcmfmac and brcmsmac refactoring,
a large batch of ssb and bcma updates, a batch of ath6kl updates,
some cfg80211 and mac80211 updates/refactoring from Johannes Berg,
a rather large collection of Bluetooth updates by way of Gustavo,
and a variety of other bits here and there.
--------------------

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
2012-05-22 16:07:23 -04:00
parent 35c579070a a0d0d1685f
commit c3719a1ef5
173 changed files with 6623 additions and 5504 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
include/linux/Kbuild
View File

@@ -269,6 +269,7 @@ header-y += netfilter_ipv4.h
header-y += netfilter_ipv6.h
header-y += netlink.h
header-y += netrom.h
header-y += nfc.h
header-y += nfs.h
header-y += nfs2.h
header-y += nfs3.h

7
include/linux/bcma/bcma.h
View File

@@ -26,6 +26,11 @@ struct bcma_chipinfo {
u8 pkg;
};
struct bcma_boardinfo {
u16 vendor;
u16 type;
};
enum bcma_clkmode {
BCMA_CLKMODE_FAST,
BCMA_CLKMODE_DYNAMIC,
@@ -198,6 +203,8 @@ struct bcma_bus {
struct bcma_chipinfo chipinfo;
struct bcma_boardinfo boardinfo;
struct bcma_device *mapped_core;
struct list_head cores;
u8 nr_cores;

11
include/linux/bcma/bcma_driver_pci.h
View File

@@ -87,6 +87,13 @@ struct pci_dev;
#define BCMA_CORE_PCI_PCICFG2 0x0600 /* PCI config space 2 (rev >= 8) */
#define BCMA_CORE_PCI_PCICFG3 0x0700 /* PCI config space 3 (rev >= 8) */
#define BCMA_CORE_PCI_SPROM(wordoffset) (0x0800 + ((wordoffset) * 2)) /* SPROM shadow area (72 bytes) */
#define BCMA_CORE_PCI_SPROM_PI_OFFSET 0 /* first word */
#define BCMA_CORE_PCI_SPROM_PI_MASK 0xf000 /* bit 15:12 */
#define BCMA_CORE_PCI_SPROM_PI_SHIFT 12 /* bit 15:12 */
#define BCMA_CORE_PCI_SPROM_MISC_CONFIG 5 /* word 5 */
#define BCMA_CORE_PCI_SPROM_L23READY_EXIT_NOPERST 0x8000 /* bit 15 */
#define BCMA_CORE_PCI_SPROM_CLKREQ_OFFSET_REV5 20 /* word 20 for srom rev <= 5 */
#define BCMA_CORE_PCI_SPROM_CLKREQ_ENB 0x0800 /* bit 11 */
/* SBtoPCIx */
#define BCMA_CORE_PCI_SBTOPCI_MEM 0x00000000
@@ -133,6 +140,7 @@ struct pci_dev;
#define BCMA_CORE_PCI_DLLP_LRREG 0x120 /* Link Replay */
#define BCMA_CORE_PCI_DLLP_LACKTOREG 0x124 /* Link Ack Timeout */
#define BCMA_CORE_PCI_DLLP_PMTHRESHREG 0x128 /* Power Management Threshold */
#define BCMA_CORE_PCI_ASPMTIMER_EXTEND 0x01000000 /* > rev7: enable extend ASPM timer */
#define BCMA_CORE_PCI_DLLP_RTRYWPREG 0x12C /* Retry buffer write ptr */
#define BCMA_CORE_PCI_DLLP_RTRYRPREG 0x130 /* Retry buffer Read ptr */
#define BCMA_CORE_PCI_DLLP_RTRYPPREG 0x134 /* Retry buffer Purged ptr */
@@ -201,12 +209,15 @@ struct bcma_drv_pci {
};
/* Register access */
#define pcicore_read16(pc, offset) bcma_read16((pc)->core, offset)
#define pcicore_read32(pc, offset) bcma_read32((pc)->core, offset)
#define pcicore_write16(pc, offset, val) bcma_write16((pc)->core, offset, val)
#define pcicore_write32(pc, offset, val) bcma_write32((pc)->core, offset, val)
extern void __devinit bcma_core_pci_init(struct bcma_drv_pci *pc);
extern int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc,
struct bcma_device *core, bool enable);
extern void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend);
extern int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev);
extern int bcma_core_pci_plat_dev_init(struct pci_dev *dev);

7
include/linux/nfc/pn544.h
View File

@@ -84,6 +84,12 @@ struct pn544_fw_packet {
};
#ifdef __KERNEL__
enum {
NFC_GPIO_ENABLE,
NFC_GPIO_FW_RESET,
NFC_GPIO_IRQ
};
/* board config */
struct pn544_nfc_platform_data {
int (*request_resources) (struct i2c_client *client);
@@ -91,6 +97,7 @@ struct pn544_nfc_platform_data {
void (*enable) (int fw);
int (*test) (void);
void (*disable) (void);
int (*get_gpio)(int type);
};
#endif /* __KERNEL__ */

8
include/linux/nl80211.h
View File

@@ -1594,6 +1594,8 @@ enum nl80211_sta_flags {
NL80211_STA_FLAG_MAX = __NL80211_STA_FLAG_AFTER_LAST - 1
};
#define NL80211_STA_FLAG_MAX_OLD_API NL80211_STA_FLAG_TDLS_PEER
/**
* struct nl80211_sta_flag_update - station flags mask/set
* @mask: mask of station flags to set
@@ -1994,9 +1996,9 @@ enum nl80211_reg_rule_flags {
* enum nl80211_dfs_regions - regulatory DFS regions
*
* @NL80211_DFS_UNSET: Country has no DFS master region specified
* @NL80211_DFS_FCC_: Country follows DFS master rules from FCC
* @NL80211_DFS_FCC_: Country follows DFS master rules from ETSI
* @NL80211_DFS_JP_: Country follows DFS master rules from JP/MKK/Telec
* @NL80211_DFS_FCC: Country follows DFS master rules from FCC
* @NL80211_DFS_ETSI: Country follows DFS master rules from ETSI
* @NL80211_DFS_JP: Country follows DFS master rules from JP/MKK/Telec
*/
enum nl80211_dfs_regions {
NL80211_DFS_UNSET = 0,

1
include/linux/ssb/ssb.h
View File

@@ -188,7 +188,6 @@ struct ssb_sprom {
struct ssb_boardinfo {
u16 vendor;
u16 type;
u8 rev;
};

61
include/linux/ssb/ssb_regs.h
View File

@@ -228,6 +228,7 @@
#define SSB_SPROM1_AGAIN_BG_SHIFT 0
#define SSB_SPROM1_AGAIN_A 0xFF00 /* A-PHY */
#define SSB_SPROM1_AGAIN_A_SHIFT 8
#define SSB_SPROM1_CCODE 0x0076
/* SPROM Revision 2 (inherits from rev 1) */
#define SSB_SPROM2_BFLHI 0x0038 /* Boardflags (high 16 bits) */
@@ -267,6 +268,7 @@
#define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
/* SPROM Revision 4 */
#define SSB_SPROM4_BOARDREV 0x0042 /* Board revision */
#define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */
#define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */
#define SSB_SPROM4_BFL2LO 0x0048 /* Board flags 2 (low 16 bits) */
@@ -389,6 +391,11 @@
#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
#define SSB_SPROM8_GPIOB_P3_SHIFT 8
#define SSB_SPROM8_LEDDC 0x009A
#define SSB_SPROM8_LEDDC_ON 0xFF00 /* oncount */
#define SSB_SPROM8_LEDDC_ON_SHIFT 8
#define SSB_SPROM8_LEDDC_OFF 0x00FF /* offcount */
#define SSB_SPROM8_LEDDC_OFF_SHIFT 0
#define SSB_SPROM8_ANTAVAIL 0x009C /* Antenna available bitfields*/
#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
@@ -404,6 +411,13 @@
#define SSB_SPROM8_AGAIN2_SHIFT 0
#define SSB_SPROM8_AGAIN3 0xFF00 /* Antenna 3 */
#define SSB_SPROM8_AGAIN3_SHIFT 8
#define SSB_SPROM8_TXRXC 0x00A2
#define SSB_SPROM8_TXRXC_TXCHAIN 0x000f
#define SSB_SPROM8_TXRXC_TXCHAIN_SHIFT 0
#define SSB_SPROM8_TXRXC_RXCHAIN 0x00f0
#define SSB_SPROM8_TXRXC_RXCHAIN_SHIFT 4
#define SSB_SPROM8_TXRXC_SWITCH 0xff00
#define SSB_SPROM8_TXRXC_SWITCH_SHIFT 8
#define SSB_SPROM8_RSSIPARM2G 0x00A4 /* RSSI params for 2GHz */
#define SSB_SPROM8_RSSISMF2G 0x000F
#define SSB_SPROM8_RSSISMC2G 0x00F0
@@ -430,6 +444,7 @@
#define SSB_SPROM8_TRI5GH_SHIFT 8
#define SSB_SPROM8_RXPO 0x00AC /* RX power offsets */
#define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
#define SSB_SPROM8_RXPO2G_SHIFT 0
#define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
#define SSB_SPROM8_RXPO5G_SHIFT 8
#define SSB_SPROM8_FEM2G 0x00AE
@@ -445,10 +460,38 @@
#define SSB_SROM8_FEM_ANTSWLUT 0xF800
#define SSB_SROM8_FEM_ANTSWLUT_SHIFT 11
#define SSB_SPROM8_THERMAL 0x00B2
#define SSB_SPROM8_MPWR_RAWTS 0x00B4
#define SSB_SPROM8_TS_SLP_OPT_CORRX 0x00B6
#define SSB_SPROM8_FOC_HWIQ_IQSWP 0x00B8
#define SSB_SPROM8_PHYCAL_TEMPDELTA 0x00BA
#define SSB_SPROM8_THERMAL_OFFSET 0x00ff
#define SSB_SPROM8_THERMAL_OFFSET_SHIFT 0
#define SSB_SPROM8_THERMAL_TRESH 0xff00
#define SSB_SPROM8_THERMAL_TRESH_SHIFT 8
/* Temp sense related entries */
#define SSB_SPROM8_RAWTS 0x00B4
#define SSB_SPROM8_RAWTS_RAWTEMP 0x01ff
#define SSB_SPROM8_RAWTS_RAWTEMP_SHIFT 0
#define SSB_SPROM8_RAWTS_MEASPOWER 0xfe00
#define SSB_SPROM8_RAWTS_MEASPOWER_SHIFT 9
#define SSB_SPROM8_OPT_CORRX 0x00B6
#define SSB_SPROM8_OPT_CORRX_TEMP_SLOPE 0x00ff
#define SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT 0
#define SSB_SPROM8_OPT_CORRX_TEMPCORRX 0xfc00
#define SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT 10
#define SSB_SPROM8_OPT_CORRX_TEMP_OPTION 0x0300
#define SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT 8
/* FOC: freiquency offset correction, HWIQ: H/W IOCAL enable, IQSWP: IQ CAL swap disable */
#define SSB_SPROM8_HWIQ_IQSWP 0x00B8
#define SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR 0x000f
#define SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT 0
#define SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP 0x0010
#define SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT 4
#define SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL 0x0020
#define SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT 5
#define SSB_SPROM8_TEMPDELTA 0x00BA
#define SSB_SPROM8_TEMPDELTA_PHYCAL 0x00ff
#define SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT 0
#define SSB_SPROM8_TEMPDELTA_PERIOD 0x0f00
#define SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT 8
#define SSB_SPROM8_TEMPDELTA_HYSTERESIS 0xf000
#define SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT 12
/* There are 4 blocks with power info sharing the same layout */
#define SSB_SROM8_PWR_INFO_CORE0 0x00C0
@@ -513,6 +556,16 @@
#define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
#define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
#define SSB_SPROM8_2G_MCSPO 0x0152
#define SSB_SPROM8_5G_MCSPO 0x0162
#define SSB_SPROM8_5GL_MCSPO 0x0172
#define SSB_SPROM8_5GH_MCSPO 0x0182
#define SSB_SPROM8_CDDPO 0x0192
#define SSB_SPROM8_STBCPO 0x0194
#define SSB_SPROM8_BW40PO 0x0196
#define SSB_SPROM8_BWDUPPO 0x0198
/* Values for boardflags_lo read from SPROM */
#define SSB_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
#define SSB_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */