xiaomi-sm8450/android_kernel_xiaomi_sm8450
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

powerpc/powernv: display reason for Malfunction Alert HMI.

Browse Source 
The V2 version of HMI event now carries additional information for
Malfunction Alert. It now contains error information about CORE and NX
checkstop. This patch checks and displays the check stop reason before
panic.

Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
Acked-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Mahesh Salgaonkar
2015-05-05 13:34:58 +05:30
committed by Michael Ellerman
parent 5d83c2b37d
commit c33e11d0dd
2 changed files with 193 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

61
arch/powerpc/include/asm/opal-api.h
View File

@@ -437,6 +437,7 @@ struct OpalMemoryErrorData {
/* HMI interrupt event */
enum OpalHMI_Version {
OpalHMIEvt_V1 = 1,
OpalHMIEvt_V2 = 2,
};
enum OpalHMI_Severity {
@@ -467,6 +468,49 @@ enum OpalHMI_ErrType {
OpalHMI_ERROR_CAPP_RECOVERY,
};
enum OpalHMI_XstopType {
CHECKSTOP_TYPE_UNKNOWN = 0,
CHECKSTOP_TYPE_CORE = 1,
CHECKSTOP_TYPE_NX = 2,
};
enum OpalHMI_CoreXstopReason {
CORE_CHECKSTOP_IFU_REGFILE = 0x00000001,
CORE_CHECKSTOP_IFU_LOGIC = 0x00000002,
CORE_CHECKSTOP_PC_DURING_RECOV = 0x00000004,
CORE_CHECKSTOP_ISU_REGFILE = 0x00000008,
CORE_CHECKSTOP_ISU_LOGIC = 0x00000010,
CORE_CHECKSTOP_FXU_LOGIC = 0x00000020,
CORE_CHECKSTOP_VSU_LOGIC = 0x00000040,
CORE_CHECKSTOP_PC_RECOV_IN_MAINT_MODE = 0x00000080,
CORE_CHECKSTOP_LSU_REGFILE = 0x00000100,
CORE_CHECKSTOP_PC_FWD_PROGRESS = 0x00000200,
CORE_CHECKSTOP_LSU_LOGIC = 0x00000400,
CORE_CHECKSTOP_PC_LOGIC = 0x00000800,
CORE_CHECKSTOP_PC_HYP_RESOURCE = 0x00001000,
CORE_CHECKSTOP_PC_HANG_RECOV_FAILED = 0x00002000,
CORE_CHECKSTOP_PC_AMBI_HANG_DETECTED = 0x00004000,
CORE_CHECKSTOP_PC_DEBUG_TRIG_ERR_INJ = 0x00008000,
CORE_CHECKSTOP_PC_SPRD_HYP_ERR_INJ = 0x00010000,
};
enum OpalHMI_NestAccelXstopReason {
NX_CHECKSTOP_SHM_INVAL_STATE_ERR = 0x00000001,
NX_CHECKSTOP_DMA_INVAL_STATE_ERR_1 = 0x00000002,
NX_CHECKSTOP_DMA_INVAL_STATE_ERR_2 = 0x00000004,
NX_CHECKSTOP_DMA_CH0_INVAL_STATE_ERR = 0x00000008,
NX_CHECKSTOP_DMA_CH1_INVAL_STATE_ERR = 0x00000010,
NX_CHECKSTOP_DMA_CH2_INVAL_STATE_ERR = 0x00000020,
NX_CHECKSTOP_DMA_CH3_INVAL_STATE_ERR = 0x00000040,
NX_CHECKSTOP_DMA_CH4_INVAL_STATE_ERR = 0x00000080,
NX_CHECKSTOP_DMA_CH5_INVAL_STATE_ERR = 0x00000100,
NX_CHECKSTOP_DMA_CH6_INVAL_STATE_ERR = 0x00000200,
NX_CHECKSTOP_DMA_CH7_INVAL_STATE_ERR = 0x00000400,
NX_CHECKSTOP_DMA_CRB_UE = 0x00000800,
NX_CHECKSTOP_DMA_CRB_SUE = 0x00001000,
NX_CHECKSTOP_PBI_ISN_UE = 0x00002000,
};
struct OpalHMIEvent {
uint8_t version; /* 0x00 */
uint8_t severity; /* 0x01 */
@@ -477,6 +521,23 @@ struct OpalHMIEvent {
__be64 hmer;
/* TFMR register. Valid only for TFAC and TFMR_PARITY error type. */
__be64 tfmr;
/* version 2 and later */
union {
/*
* checkstop info (Core/NX).
* Valid for OpalHMI_ERROR_MALFUNC_ALERT.
*/
struct {
uint8_t xstop_type; /* enum OpalHMI_XstopType */
uint8_t reserved_1[3];
__be32 xstop_reason;
union {
__be32 pir; /* for CHECKSTOP_TYPE_CORE */
__be32 chip_id; /* for CHECKSTOP_TYPE_NX */
} u;
} xstop_error;
} u;
};
enum {