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omap1: Fix redundant UARTs pin muxing that can break other hardware support

Selaa lähdekoodia 
Commit 15ac408ee5 removed enabled_uart
and OMAP_TAG_UART. This works for mach-omap2, but causes issues on
mach-omap1 for some boards as the mach-omap1 serial.c was muxing
pins based on the enabled_uart flag for 15xx.

Fix this by muxing pins in board-*.c files for the 15xx boards for
the uart ports that had enabled_uart flag set before the commit
above.

Tested on Amsdtrad Delta only.

Note that in the future we should add support for powering down
the uarts with a timer like mach-omap2/serial.c does. Otherwise
the enabled uarts will be blocking retention-while-idle.

Signed-off-by: Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Janusz Krzysztofik
2009-10-22 14:47:42 -07:00
committed by Tony Lindgren
vanhempi dcc730dc9d
commit c33da3a800
9 muutettua tiedostoa jossa 72 lisäystä ja 26 poistoa
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26
arch/arm/mach-omap1/serial.c
Näytä tiedosto

@@ -131,8 +131,6 @@ void __init omap_serial_init(void)
}
for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
unsigned char reg;
switch (i) {
case 0:
uart1_ck = clk_get(NULL, "uart1_ck");
@@ -143,16 +141,6 @@ void __init omap_serial_init(void)
if (cpu_is_omap15xx())
clk_set_rate(uart1_ck, 12000000);
}
if (cpu_is_omap15xx()) {
omap_cfg_reg(UART1_TX);
omap_cfg_reg(UART1_RTS);
if (machine_is_omap_innovator()) {
reg = fpga_read(OMAP1510_FPGA_POWER);
reg |= OMAP1510_FPGA_PCR_COM1_EN;
fpga_write(reg, OMAP1510_FPGA_POWER);
udelay(10);
}
}
break;
case 1:
uart2_ck = clk_get(NULL, "uart2_ck");
@@ -165,16 +153,6 @@ void __init omap_serial_init(void)
else
clk_set_rate(uart2_ck, 48000000);
}
if (cpu_is_omap15xx()) {
omap_cfg_reg(UART2_TX);
omap_cfg_reg(UART2_RTS);
if (machine_is_omap_innovator()) {
reg = fpga_read(OMAP1510_FPGA_POWER);
reg |= OMAP1510_FPGA_PCR_COM2_EN;
fpga_write(reg, OMAP1510_FPGA_POWER);
udelay(10);
}
}
break;
case 2:
uart3_ck = clk_get(NULL, "uart3_ck");
@@ -185,10 +163,6 @@ void __init omap_serial_init(void)
if (cpu_is_omap15xx())
clk_set_rate(uart3_ck, 12000000);
}
if (cpu_is_omap15xx()) {
omap_cfg_reg(UART3_TX);
omap_cfg_reg(UART3_RX);
}
break;
}
omap_serial_reset(&serial_platform_data[i]);