Merge tag 'for-linus-20140808' of git://git.infradead.org/linux-mtd
Pull MTD updates from Brian Norris: "AMD-compatible CFI driver: - Support OTP programming for Micron M29EW family - Increase buffer write timeout, according to detected flash parameter info NAND - Add helpers for retrieving ONFI timing modes - GPMI: provide option to disable bad block marker swapping (required for Ka-On electronics platforms) SPI NOR - EON EN25QH128 support - Support new Flag Status Register (FSR) on a few Micron flash Common - New sysfs entries for bad block and ECC stats And a few miscellaneous refactorings, cleanups, and driver improvements" * tag 'for-linus-20140808' of git://git.infradead.org/linux-mtd: (31 commits) mtd: gpmi: make blockmark swapping optional mtd: gpmi: remove line breaks from error messages and improve wording mtd: gpmi: remove useless (void *) type casts and spaces between type casts and variables mtd: atmel_nand: NFC: support multiple interrupt handling mtd: atmel_nand: implement the nfc_device_ready() by checking the R/B bit mtd: atmel_nand: add NFC status error check mtd: atmel_nand: make ecc parameters same as definition mtd: nand: add ONFI timing mode to nand_timings converter mtd: nand: define struct nand_timings mtd: cfi_cmdset_0002: fix do_write_buffer() timeout error mtd: denali: use 8 bytes for READID command mtd/ftl: fix the double free of the buffers allocated in build_maps() mtd: phram: Fix whitespace issues mtd: spi-nor: add support for EON EN25QH128 mtd: cfi_cmdset_0002: Add support for locking OTP memory mtd: cfi_cmdset_0002: Add support for writing OTP memory mtd: cfi_cmdset_0002: Invalidate cache after entering/exiting OTP memory mtd: cfi_cmdset_0002: Add support for reading OTP mtd: spi-nor: add support for flag status register on Micron chips mtd: Account for BBT blocks when a partition is being allocated ...
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@@ -222,6 +222,7 @@ struct mtd_info {
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int (*_lock) (struct mtd_info *mtd, loff_t ofs, uint64_t len);
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int (*_unlock) (struct mtd_info *mtd, loff_t ofs, uint64_t len);
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int (*_is_locked) (struct mtd_info *mtd, loff_t ofs, uint64_t len);
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int (*_block_isreserved) (struct mtd_info *mtd, loff_t ofs);
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int (*_block_isbad) (struct mtd_info *mtd, loff_t ofs);
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int (*_block_markbad) (struct mtd_info *mtd, loff_t ofs);
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int (*_suspend) (struct mtd_info *mtd);
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@@ -302,6 +303,7 @@ static inline void mtd_sync(struct mtd_info *mtd)
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int mtd_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
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int mtd_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
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int mtd_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len);
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int mtd_block_isreserved(struct mtd_info *mtd, loff_t ofs);
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int mtd_block_isbad(struct mtd_info *mtd, loff_t ofs);
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int mtd_block_markbad(struct mtd_info *mtd, loff_t ofs);
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@@ -810,6 +810,7 @@ extern struct nand_manufacturers nand_manuf_ids[];
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extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
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extern int nand_default_bbt(struct mtd_info *mtd);
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extern int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);
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extern int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs);
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extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
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extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
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int allowbbt);
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@@ -947,4 +948,56 @@ static inline int jedec_feature(struct nand_chip *chip)
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return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features)
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: 0;
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}
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/**
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* struct nand_sdr_timings - SDR NAND chip timings
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*
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* This struct defines the timing requirements of a SDR NAND chip.
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* These informations can be found in every NAND datasheets and the timings
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* meaning are described in the ONFI specifications:
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* www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing
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* Parameters)
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*
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* All these timings are expressed in picoseconds.
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*/
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struct nand_sdr_timings {
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u32 tALH_min;
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u32 tADL_min;
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u32 tALS_min;
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u32 tAR_min;
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u32 tCEA_max;
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u32 tCEH_min;
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u32 tCH_min;
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u32 tCHZ_max;
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u32 tCLH_min;
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u32 tCLR_min;
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u32 tCLS_min;
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u32 tCOH_min;
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u32 tCS_min;
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u32 tDH_min;
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u32 tDS_min;
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u32 tFEAT_max;
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u32 tIR_min;
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u32 tITC_max;
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u32 tRC_min;
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u32 tREA_max;
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u32 tREH_min;
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u32 tRHOH_min;
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u32 tRHW_min;
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u32 tRHZ_max;
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u32 tRLOH_min;
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u32 tRP_min;
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u32 tRR_min;
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u64 tRST_max;
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u32 tWB_max;
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u32 tWC_min;
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u32 tWH_min;
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u32 tWHR_min;
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u32 tWP_min;
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u32 tWW_min;
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};
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/* get timing characteristics from ONFI timing mode. */
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const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode);
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#endif /* __LINUX_MTD_NAND_H */
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@@ -34,6 +34,7 @@
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#define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */
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#define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */
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#define SPINOR_OP_RDCR 0x35 /* Read configuration register */
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#define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
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/* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
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#define SPINOR_OP_READ4 0x13 /* Read data bytes (low frequency) */
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@@ -66,6 +67,9 @@
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#define SR_QUAD_EN_MX 0x40 /* Macronix Quad I/O */
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/* Flag Status Register bits */
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#define FSR_READY 0x80
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/* Configuration Register bits. */
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#define CR_QUAD_EN_SPAN 0x2 /* Spansion Quad I/O */
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