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pinctrl: uniphier: introduce capability flag

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The core part of the UniPhier pinctrl driver needs to support a new
capability for upcoming UniPhier ARMv8 SoCs.  This sometimes happens
because pinctrl drivers include really SoC-specific stuff.

This commit intends to tidy up SoC-specific parameters of the existing
drivers before adding the new one.  Having just one flag would be
better than adding a new struct member every time a new SoC-specific
capability comes up.

At this time, there is one flag, UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE.
This capability (I'd say rather quirk) was added for PH1-Pro4 and
PH1-Pro5 as requirement from a customer.  For those SoCs, one pin-mux
setting is controlled by the combination of two separate registers; the
LSB bits at register offset (8 * N) and the MSB bits at (8 * N + 4).
Because it is impossible to update two separate registers atomically,
the LOAD_PINCTRL register should be set in order to make the pin-mux
settings really effective.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Masahiro Yamada
2016-05-31 17:05:16 +09:00
committed by Linus Walleij
parent 94bf176b97
commit c2ebf4754b
8 changed files with 34 additions and 31 deletions
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4
drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
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@@ -852,9 +852,7 @@ static struct uniphier_pinctrl_socdata uniphier_ld4_pindata = {
.groups_count = ARRAY_SIZE(uniphier_ld4_groups),
.functions = uniphier_ld4_functions,
.functions_count = ARRAY_SIZE(uniphier_ld4_functions),
.mux_bits = 8,
.reg_stride = 4,
.load_pinctrl = false,
.caps = 0,
};
static int uniphier_ld4_pinctrl_probe(struct platform_device *pdev)