drm/msm: sync generated headers
We haven't sync'd for a while.. pull in updates to get definitions for some fields in pkt7 payloads. Signed-off-by: Rob Clark <robdclark@chromium.org> Acked-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
This commit is contained in:
Rob Clark
@@ -8,19 +8,19 @@ http://github.com/freedreno/envytools/
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git clone https://github.com/freedreno/envytools.git
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The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 37239 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14)
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- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
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- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14)
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- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14)
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- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14)
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- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14)
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- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14)
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- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14)
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- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14)
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- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14)
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- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14)
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Copyright (C) 2013-2018 by the following authors:
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Copyright (C) 2013-2020 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
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@@ -148,7 +148,31 @@ static inline uint32_t DSI_6G_HW_VERSION_STEP(uint32_t val)
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#define DSI_STATUS0_INTERLEAVE_OP_CONTENTION 0x80000000
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#define REG_DSI_FIFO_STATUS 0x00000008
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#define DSI_FIFO_STATUS_VIDEO_MDP_FIFO_OVERFLOW 0x00000001
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#define DSI_FIFO_STATUS_VIDEO_MDP_FIFO_UNDERFLOW 0x00000008
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#define DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW 0x00000080
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#define DSI_FIFO_STATUS_CMD_DMA_FIFO_RD_WATERMARK_REACH 0x00000100
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#define DSI_FIFO_STATUS_CMD_DMA_FIFO_WR_WATERMARK_REACH 0x00000200
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#define DSI_FIFO_STATUS_CMD_DMA_FIFO_UNDERFLOW 0x00000400
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#define DSI_FIFO_STATUS_DLN0_LP_FIFO_EMPTY 0x00001000
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#define DSI_FIFO_STATUS_DLN0_LP_FIFO_FULL 0x00002000
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#define DSI_FIFO_STATUS_DLN0_LP_FIFO_OVERFLOW 0x00004000
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#define DSI_FIFO_STATUS_DLN0_HS_FIFO_EMPTY 0x00010000
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#define DSI_FIFO_STATUS_DLN0_HS_FIFO_FULL 0x00020000
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#define DSI_FIFO_STATUS_DLN0_HS_FIFO_OVERFLOW 0x00040000
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#define DSI_FIFO_STATUS_DLN0_HS_FIFO_UNDERFLOW 0x00080000
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#define DSI_FIFO_STATUS_DLN1_HS_FIFO_EMPTY 0x00100000
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#define DSI_FIFO_STATUS_DLN1_HS_FIFO_FULL 0x00200000
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#define DSI_FIFO_STATUS_DLN1_HS_FIFO_OVERFLOW 0x00400000
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#define DSI_FIFO_STATUS_DLN1_HS_FIFO_UNDERFLOW 0x00800000
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#define DSI_FIFO_STATUS_DLN2_HS_FIFO_EMPTY 0x01000000
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#define DSI_FIFO_STATUS_DLN2_HS_FIFO_FULL 0x02000000
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#define DSI_FIFO_STATUS_DLN2_HS_FIFO_OVERFLOW 0x04000000
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#define DSI_FIFO_STATUS_DLN2_HS_FIFO_UNDERFLOW 0x08000000
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#define DSI_FIFO_STATUS_DLN3_HS_FIFO_EMPTY 0x10000000
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#define DSI_FIFO_STATUS_DLN3_HS_FIFO_FULL 0x20000000
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#define DSI_FIFO_STATUS_DLN3_HS_FIFO_OVERFLOW 0x40000000
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#define DSI_FIFO_STATUS_DLN3_HS_FIFO_UNDERFLOW 0x80000000
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#define REG_DSI_VID_CFG0 0x0000000c
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#define DSI_VID_CFG0_VIRT_CHANNEL__MASK 0x00000003
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@@ -318,38 +342,72 @@ static inline uint32_t DSI_CMD_CFG1_WR_MEM_CONTINUE(uint32_t val)
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#define REG_DSI_DMA_LEN 0x00000048
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#define REG_DSI_CMD_MDP_STREAM_CTRL 0x00000054
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#define DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__MASK 0x0000003f
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#define DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__SHIFT 0
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static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE(uint32_t val)
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#define REG_DSI_CMD_MDP_STREAM0_CTRL 0x00000054
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#define DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__MASK 0x0000003f
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#define DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__SHIFT 0
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static inline uint32_t DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE(uint32_t val)
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{
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return ((val) << DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__MASK;
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return ((val) << DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__MASK;
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}
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#define DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300
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#define DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__SHIFT 8
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static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL(uint32_t val)
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#define DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300
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#define DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__SHIFT 8
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static inline uint32_t DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL(uint32_t val)
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{
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return ((val) << DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__MASK;
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return ((val) << DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__MASK;
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}
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#define DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__MASK 0xffff0000
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#define DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__SHIFT 16
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static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT(uint32_t val)
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#define DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__MASK 0xffff0000
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#define DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__SHIFT 16
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static inline uint32_t DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(uint32_t val)
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{
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return ((val) << DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__MASK;
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return ((val) << DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__MASK;
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}
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#define REG_DSI_CMD_MDP_STREAM_TOTAL 0x00000058
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#define DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__MASK 0x00000fff
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#define DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__SHIFT 0
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static inline uint32_t DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL(uint32_t val)
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#define REG_DSI_CMD_MDP_STREAM0_TOTAL 0x00000058
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#define DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__MASK 0x00000fff
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#define DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__SHIFT 0
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static inline uint32_t DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL(uint32_t val)
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{
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return ((val) << DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__MASK;
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return ((val) << DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__MASK;
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}
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#define DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__MASK 0x0fff0000
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#define DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__SHIFT 16
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static inline uint32_t DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL(uint32_t val)
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#define DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__MASK 0x0fff0000
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#define DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__SHIFT 16
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static inline uint32_t DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL(uint32_t val)
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{
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return ((val) << DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__MASK;
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return ((val) << DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__MASK;
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}
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#define REG_DSI_CMD_MDP_STREAM1_CTRL 0x0000005c
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#define DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__MASK 0x0000003f
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#define DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__SHIFT 0
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static inline uint32_t DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE(uint32_t val)
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{
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return ((val) << DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__MASK;
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}
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#define DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300
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#define DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__SHIFT 8
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static inline uint32_t DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL(uint32_t val)
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{
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return ((val) << DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__MASK;
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}
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#define DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__MASK 0xffff0000
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#define DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__SHIFT 16
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static inline uint32_t DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT(uint32_t val)
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{
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return ((val) << DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__MASK;
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}
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#define REG_DSI_CMD_MDP_STREAM1_TOTAL 0x00000060
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#define DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__MASK 0x0000ffff
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#define DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__SHIFT 0
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static inline uint32_t DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL(uint32_t val)
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{
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return ((val) << DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__MASK;
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}
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#define DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__MASK 0xffff0000
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#define DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__SHIFT 16
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static inline uint32_t DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL(uint32_t val)
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{
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return ((val) << DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__MASK;
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}
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#define REG_DSI_ACK_ERR_STATUS 0x00000064
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@@ -389,6 +447,35 @@ static inline uint32_t DSI_TRIG_CTRL_STREAM(uint32_t val)
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#define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 0x00001000
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#define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1 0x00010000
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#define REG_DSI_LP_TIMER_CTRL 0x000000b4
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#define DSI_LP_TIMER_CTRL_LP_RX_TO__MASK 0x0000ffff
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#define DSI_LP_TIMER_CTRL_LP_RX_TO__SHIFT 0
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static inline uint32_t DSI_LP_TIMER_CTRL_LP_RX_TO(uint32_t val)
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{
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return ((val) << DSI_LP_TIMER_CTRL_LP_RX_TO__SHIFT) & DSI_LP_TIMER_CTRL_LP_RX_TO__MASK;
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}
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#define DSI_LP_TIMER_CTRL_BTA_TO__MASK 0xffff0000
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#define DSI_LP_TIMER_CTRL_BTA_TO__SHIFT 16
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static inline uint32_t DSI_LP_TIMER_CTRL_BTA_TO(uint32_t val)
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{
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return ((val) << DSI_LP_TIMER_CTRL_BTA_TO__SHIFT) & DSI_LP_TIMER_CTRL_BTA_TO__MASK;
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}
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#define REG_DSI_HS_TIMER_CTRL 0x000000b8
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#define DSI_HS_TIMER_CTRL_HS_TX_TO__MASK 0x0000ffff
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#define DSI_HS_TIMER_CTRL_HS_TX_TO__SHIFT 0
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static inline uint32_t DSI_HS_TIMER_CTRL_HS_TX_TO(uint32_t val)
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{
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return ((val) << DSI_HS_TIMER_CTRL_HS_TX_TO__SHIFT) & DSI_HS_TIMER_CTRL_HS_TX_TO__MASK;
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}
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#define DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__MASK 0x000f0000
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#define DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__SHIFT 16
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static inline uint32_t DSI_HS_TIMER_CTRL_TIMER_RESOLUTION(uint32_t val)
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{
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return ((val) << DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__SHIFT) & DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__MASK;
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}
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#define DSI_HS_TIMER_CTRL_HS_TX_TO_STOP_EN 0x10000000
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#define REG_DSI_TIMEOUT_STATUS 0x000000bc
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#define REG_DSI_CLKOUT_TIMING_CTRL 0x000000c0
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@@ -409,6 +496,19 @@ static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(uint32_t val)
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#define DSI_EOT_PACKET_CTRL_TX_EOT_APPEND 0x00000001
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#define DSI_EOT_PACKET_CTRL_RX_EOT_IGNORE 0x00000010
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#define REG_DSI_LANE_STATUS 0x000000a4
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#define DSI_LANE_STATUS_DLN0_STOPSTATE 0x00000001
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#define DSI_LANE_STATUS_DLN1_STOPSTATE 0x00000002
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#define DSI_LANE_STATUS_DLN2_STOPSTATE 0x00000004
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#define DSI_LANE_STATUS_DLN3_STOPSTATE 0x00000008
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#define DSI_LANE_STATUS_CLKLN_STOPSTATE 0x00000010
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#define DSI_LANE_STATUS_DLN0_ULPS_ACTIVE_NOT 0x00000100
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#define DSI_LANE_STATUS_DLN1_ULPS_ACTIVE_NOT 0x00000200
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#define DSI_LANE_STATUS_DLN2_ULPS_ACTIVE_NOT 0x00000400
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#define DSI_LANE_STATUS_DLN3_ULPS_ACTIVE_NOT 0x00000800
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#define DSI_LANE_STATUS_CLKLN_ULPS_ACTIVE_NOT 0x00001000
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#define DSI_LANE_STATUS_DLN0_DIRECTION 0x00010000
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#define REG_DSI_LANE_CTRL 0x000000a8
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#define DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST 0x10000000
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@@ -436,6 +536,21 @@ static inline uint32_t DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(enum dsi_lane_swap val)
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#define DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK 0x00000200
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#define REG_DSI_CLK_STATUS 0x0000011c
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#define DSI_CLK_STATUS_DSI_AON_AHBM_HCLK_ACTIVE 0x00000001
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||||
#define DSI_CLK_STATUS_DSI_DYN_AHBM_HCLK_ACTIVE 0x00000002
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||||
#define DSI_CLK_STATUS_DSI_AON_AHBS_HCLK_ACTIVE 0x00000004
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#define DSI_CLK_STATUS_DSI_DYN_AHBS_HCLK_ACTIVE 0x00000008
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#define DSI_CLK_STATUS_DSI_AON_DSICLK_ACTIVE 0x00000010
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#define DSI_CLK_STATUS_DSI_DYN_DSICLK_ACTIVE 0x00000020
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#define DSI_CLK_STATUS_DSI_AON_BYTECLK_ACTIVE 0x00000040
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#define DSI_CLK_STATUS_DSI_DYN_BYTECLK_ACTIVE 0x00000080
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||||
#define DSI_CLK_STATUS_DSI_AON_ESCCLK_ACTIVE 0x00000100
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#define DSI_CLK_STATUS_DSI_AON_PCLK_ACTIVE 0x00000200
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#define DSI_CLK_STATUS_DSI_DYN_PCLK_ACTIVE 0x00000400
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||||
#define DSI_CLK_STATUS_DSI_DYN_CMD_PCLK_ACTIVE 0x00001000
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||||
#define DSI_CLK_STATUS_DSI_CMD_PCLK_ACTIVE 0x00002000
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||||
#define DSI_CLK_STATUS_DSI_VID_PCLK_ACTIVE 0x00004000
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||||
#define DSI_CLK_STATUS_DSI_CAM_BIST_PCLK_ACT 0x00008000
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||||
#define DSI_CLK_STATUS_PLL_UNLOCKED 0x00010000
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#define REG_DSI_PHY_RESET 0x00000128
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||||
@@ -444,6 +559,51 @@ static inline uint32_t DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(enum dsi_lane_swap val)
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#define REG_DSI_T_CLK_PRE_EXTEND 0x0000017c
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#define DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK 0x00000001
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#define REG_DSI_CMD_MODE_MDP_CTRL2 0x000001b4
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#define DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__MASK 0x0000000f
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||||
#define DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__SHIFT 0
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||||
static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2(enum dsi_cmd_dst_format val)
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{
|
||||
return ((val) << DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__SHIFT) & DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__MASK;
|
||||
}
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||||
#define DSI_CMD_MODE_MDP_CTRL2_R_SEL 0x00000010
|
||||
#define DSI_CMD_MODE_MDP_CTRL2_G_SEL 0x00000020
|
||||
#define DSI_CMD_MODE_MDP_CTRL2_B_SEL 0x00000040
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||||
#define DSI_CMD_MODE_MDP_CTRL2_BYTE_MSB_LSB_FLIP 0x00000080
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||||
#define DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__MASK 0x00000700
|
||||
#define DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__SHIFT 8
|
||||
static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP(enum dsi_rgb_swap val)
|
||||
{
|
||||
return ((val) << DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__SHIFT) & DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__MASK;
|
||||
}
|
||||
#define DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__MASK 0x00007000
|
||||
#define DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__SHIFT 12
|
||||
static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP(enum dsi_rgb_swap val)
|
||||
{
|
||||
return ((val) << DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__SHIFT) & DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__MASK;
|
||||
}
|
||||
#define DSI_CMD_MODE_MDP_CTRL2_BURST_MODE 0x00010000
|
||||
|
||||
#define REG_DSI_CMD_MODE_MDP_STREAM2_CTRL 0x000001b8
|
||||
#define DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__MASK 0x0000003f
|
||||
#define DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__SHIFT 0
|
||||
static inline uint32_t DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__MASK;
|
||||
}
|
||||
#define DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300
|
||||
#define DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__SHIFT 8
|
||||
static inline uint32_t DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__MASK;
|
||||
}
|
||||
#define DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__MASK 0xffff0000
|
||||
#define DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__SHIFT 16
|
||||
static inline uint32_t DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT(uint32_t val)
|
||||
{
|
||||
return ((val) << DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__MASK;
|
||||
}
|
||||
|
||||
#define REG_DSI_RDBK_DATA_CTRL 0x000001d0
|
||||
#define DSI_RDBK_DATA_CTRL_COUNT__MASK 0x00ff0000
|
||||
#define DSI_RDBK_DATA_CTRL_COUNT__SHIFT 16
|
||||
|
||||
Reference in New Issue
Block a user