Merge branch 'devel'
* devel: (33 commits) edac i5000, i5400: fix pointer math in i5000_get_mc_regs() edac: allow specifying the error count with fake_inject edac: add support for Calxeda highbank L2 cache ecc edac: add support for Calxeda highbank memory controller edac: create top-level debugfs directory sb_edac: properly handle error count i7core_edac: properly handle error count edac: edac_mc_handle_error(): add an error_count parameter edac: remove arch-specific parameter for the error handler amd64_edac: Don't pass driver name as an error parameter edac_mc: check for allocation failure in edac_mc_alloc() edac: Increase version to 3.0.0 edac_mc: Cleanup per-dimm_info debug messages edac: Convert debugfX to edac_dbg(X, edac: Use more normal debugging macro style edac: Don't add __func__ or __FILE__ for debugf[0-9] msgs Edac: Add ABI Documentation for the new device nodes edac: move documentation ABI to ABI/testing/sysfs-devices-edac i7core_edac: change the mem allocation scheme to make Documentation/kobject.txt happy edac: change the mem allocation scheme to make Documentation/kobject.txt happy ...
This commit is contained in:
Mauro Carvalho Chehab
@@ -13,9 +13,11 @@
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#define _LINUX_EDAC_H_
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#include <linux/atomic.h>
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#include <linux/device.h>
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#include <linux/kobject.h>
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#include <linux/completion.h>
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#include <linux/workqueue.h>
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#include <linux/debugfs.h>
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struct device;
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@@ -49,7 +51,19 @@ static inline void opstate_init(void)
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#define EDAC_MC_LABEL_LEN 31
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#define MC_PROC_NAME_MAX_LEN 7
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/* memory devices */
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/**
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* enum dev_type - describe the type of memory DRAM chips used at the stick
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* @DEV_UNKNOWN: Can't be determined, or MC doesn't support detect it
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* @DEV_X1: 1 bit for data
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* @DEV_X2: 2 bits for data
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* @DEV_X4: 4 bits for data
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* @DEV_X8: 8 bits for data
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* @DEV_X16: 16 bits for data
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* @DEV_X32: 32 bits for data
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* @DEV_X64: 64 bits for data
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*
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* Typical values are x4 and x8.
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*/
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enum dev_type {
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DEV_UNKNOWN = 0,
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DEV_X1,
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@@ -167,18 +181,30 @@ enum mem_type {
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#define MEM_FLAG_DDR3 BIT(MEM_DDR3)
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#define MEM_FLAG_RDDR3 BIT(MEM_RDDR3)
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/* chipset Error Detection and Correction capabilities and mode */
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/**
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* enum edac-type - Error Detection and Correction capabilities and mode
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* @EDAC_UNKNOWN: Unknown if ECC is available
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* @EDAC_NONE: Doesn't support ECC
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* @EDAC_RESERVED: Reserved ECC type
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* @EDAC_PARITY: Detects parity errors
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* @EDAC_EC: Error Checking - no correction
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* @EDAC_SECDED: Single bit error correction, Double detection
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* @EDAC_S2ECD2ED: Chipkill x2 devices - do these exist?
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* @EDAC_S4ECD4ED: Chipkill x4 devices
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* @EDAC_S8ECD8ED: Chipkill x8 devices
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* @EDAC_S16ECD16ED: Chipkill x16 devices
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*/
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enum edac_type {
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EDAC_UNKNOWN = 0, /* Unknown if ECC is available */
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EDAC_NONE, /* Doesn't support ECC */
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EDAC_RESERVED, /* Reserved ECC type */
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EDAC_PARITY, /* Detects parity errors */
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EDAC_EC, /* Error Checking - no correction */
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EDAC_SECDED, /* Single bit error correction, Double detection */
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EDAC_S2ECD2ED, /* Chipkill x2 devices - do these exist? */
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EDAC_S4ECD4ED, /* Chipkill x4 devices */
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EDAC_S8ECD8ED, /* Chipkill x8 devices */
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EDAC_S16ECD16ED, /* Chipkill x16 devices */
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EDAC_UNKNOWN = 0,
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EDAC_NONE,
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EDAC_RESERVED,
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EDAC_PARITY,
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EDAC_EC,
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EDAC_SECDED,
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EDAC_S2ECD2ED,
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EDAC_S4ECD4ED,
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EDAC_S8ECD8ED,
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EDAC_S16ECD16ED,
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};
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#define EDAC_FLAG_UNKNOWN BIT(EDAC_UNKNOWN)
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@@ -191,18 +217,30 @@ enum edac_type {
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#define EDAC_FLAG_S8ECD8ED BIT(EDAC_S8ECD8ED)
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#define EDAC_FLAG_S16ECD16ED BIT(EDAC_S16ECD16ED)
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/* scrubbing capabilities */
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/**
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* enum scrub_type - scrubbing capabilities
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* @SCRUB_UNKNOWN Unknown if scrubber is available
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* @SCRUB_NONE: No scrubber
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* @SCRUB_SW_PROG: SW progressive (sequential) scrubbing
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* @SCRUB_SW_SRC: Software scrub only errors
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* @SCRUB_SW_PROG_SRC: Progressive software scrub from an error
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* @SCRUB_SW_TUNABLE: Software scrub frequency is tunable
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* @SCRUB_HW_PROG: HW progressive (sequential) scrubbing
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* @SCRUB_HW_SRC: Hardware scrub only errors
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* @SCRUB_HW_PROG_SRC: Progressive hardware scrub from an error
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* SCRUB_HW_TUNABLE: Hardware scrub frequency is tunable
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*/
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enum scrub_type {
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SCRUB_UNKNOWN = 0, /* Unknown if scrubber is available */
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SCRUB_NONE, /* No scrubber */
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SCRUB_SW_PROG, /* SW progressive (sequential) scrubbing */
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SCRUB_SW_SRC, /* Software scrub only errors */
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SCRUB_SW_PROG_SRC, /* Progressive software scrub from an error */
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SCRUB_SW_TUNABLE, /* Software scrub frequency is tunable */
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SCRUB_HW_PROG, /* HW progressive (sequential) scrubbing */
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SCRUB_HW_SRC, /* Hardware scrub only errors */
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SCRUB_HW_PROG_SRC, /* Progressive hardware scrub from an error */
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SCRUB_HW_TUNABLE /* Hardware scrub frequency is tunable */
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SCRUB_UNKNOWN = 0,
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SCRUB_NONE,
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SCRUB_SW_PROG,
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SCRUB_SW_SRC,
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SCRUB_SW_PROG_SRC,
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SCRUB_SW_TUNABLE,
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SCRUB_HW_PROG,
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SCRUB_HW_SRC,
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SCRUB_HW_PROG_SRC,
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SCRUB_HW_TUNABLE
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};
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#define SCRUB_FLAG_SW_PROG BIT(SCRUB_SW_PROG)
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@@ -374,7 +412,44 @@ struct edac_mc_layer {
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#define EDAC_MAX_LAYERS 3
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/**
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* EDAC_DIMM_PTR - Macro responsible to find a pointer inside a pointer array
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* EDAC_DIMM_OFF - Macro responsible to get a pointer offset inside a pointer array
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* for the element given by [layer0,layer1,layer2] position
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*
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* @layers: a struct edac_mc_layer array, describing how many elements
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* were allocated for each layer
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* @n_layers: Number of layers at the @layers array
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* @layer0: layer0 position
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* @layer1: layer1 position. Unused if n_layers < 2
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* @layer2: layer2 position. Unused if n_layers < 3
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*
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* For 1 layer, this macro returns &var[layer0] - &var
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* For 2 layers, this macro is similar to allocate a bi-dimensional array
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* and to return "&var[layer0][layer1] - &var"
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* For 3 layers, this macro is similar to allocate a tri-dimensional array
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* and to return "&var[layer0][layer1][layer2] - &var"
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*
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* A loop could be used here to make it more generic, but, as we only have
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* 3 layers, this is a little faster.
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* By design, layers can never be 0 or more than 3. If that ever happens,
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* a NULL is returned, causing an OOPS during the memory allocation routine,
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* with would point to the developer that he's doing something wrong.
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*/
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#define EDAC_DIMM_OFF(layers, nlayers, layer0, layer1, layer2) ({ \
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int __i; \
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if ((nlayers) == 1) \
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__i = layer0; \
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else if ((nlayers) == 2) \
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__i = (layer1) + ((layers[1]).size * (layer0)); \
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else if ((nlayers) == 3) \
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__i = (layer2) + ((layers[2]).size * ((layer1) + \
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((layers[1]).size * (layer0)))); \
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else \
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__i = -EINVAL; \
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__i; \
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})
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/**
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* EDAC_DIMM_PTR - Macro responsible to get a pointer inside a pointer array
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* for the element given by [layer0,layer1,layer2] position
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*
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* @layers: a struct edac_mc_layer array, describing how many elements
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@@ -391,30 +466,20 @@ struct edac_mc_layer {
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* and to return "&var[layer0][layer1]"
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* For 3 layers, this macro is similar to allocate a tri-dimensional array
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* and to return "&var[layer0][layer1][layer2]"
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*
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* A loop could be used here to make it more generic, but, as we only have
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* 3 layers, this is a little faster.
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* By design, layers can never be 0 or more than 3. If that ever happens,
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* a NULL is returned, causing an OOPS during the memory allocation routine,
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* with would point to the developer that he's doing something wrong.
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*/
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#define EDAC_DIMM_PTR(layers, var, nlayers, layer0, layer1, layer2) ({ \
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typeof(var) __p; \
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if ((nlayers) == 1) \
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__p = &var[layer0]; \
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else if ((nlayers) == 2) \
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__p = &var[(layer1) + ((layers[1]).size * (layer0))]; \
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else if ((nlayers) == 3) \
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__p = &var[(layer2) + ((layers[2]).size * ((layer1) + \
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((layers[1]).size * (layer0))))]; \
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else \
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typeof(*var) __p; \
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int ___i = EDAC_DIMM_OFF(layers, nlayers, layer0, layer1, layer2); \
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if (___i < 0) \
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__p = NULL; \
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else \
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__p = (var)[___i]; \
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__p; \
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})
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/* FIXME: add the proper per-location error counts */
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struct dimm_info {
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struct device dev;
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char label[EDAC_MC_LABEL_LEN + 1]; /* DIMM label on motherboard */
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/* Memory location data */
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@@ -456,6 +521,8 @@ struct rank_info {
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};
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struct csrow_info {
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struct device dev;
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/* Used only by edac_mc_find_csrow_by_page() */
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unsigned long first_page; /* first page number in csrow */
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unsigned long last_page; /* last page number in csrow */
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@@ -469,44 +536,26 @@ struct csrow_info {
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struct mem_ctl_info *mci; /* the parent */
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struct kobject kobj; /* sysfs kobject for this csrow */
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/* channel information for this csrow */
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u32 nr_channels;
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struct rank_info *channels;
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struct rank_info **channels;
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};
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struct mcidev_sysfs_group {
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const char *name; /* group name */
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const struct mcidev_sysfs_attribute *mcidev_attr; /* group attributes */
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};
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struct mcidev_sysfs_group_kobj {
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struct list_head list; /* list for all instances within a mc */
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struct kobject kobj; /* kobj for the group */
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const struct mcidev_sysfs_group *grp; /* group description table */
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struct mem_ctl_info *mci; /* the parent */
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};
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/* mcidev_sysfs_attribute structure
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* used for driver sysfs attributes and in mem_ctl_info
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* sysfs top level entries
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/*
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* struct errcount_attribute - used to store the several error counts
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*/
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struct mcidev_sysfs_attribute {
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/* It should use either attr or grp */
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struct attribute attr;
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const struct mcidev_sysfs_group *grp; /* Points to a group of attributes */
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/* Ops for show/store values at the attribute - not used on group */
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ssize_t (*show)(struct mem_ctl_info *,char *);
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ssize_t (*store)(struct mem_ctl_info *, const char *,size_t);
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struct errcount_attribute_data {
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int n_layers;
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int pos[EDAC_MAX_LAYERS];
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int layer0, layer1, layer2;
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};
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/* MEMORY controller information structure
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*/
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struct mem_ctl_info {
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struct device dev;
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struct bus_type bus;
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struct list_head link; /* for global list of mem_ctl_info structs */
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struct module *owner; /* Module owner of this control struct */
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@@ -548,10 +597,18 @@ struct mem_ctl_info {
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unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci,
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unsigned long page);
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int mc_idx;
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struct csrow_info *csrows;
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struct csrow_info **csrows;
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unsigned nr_csrows, num_cschannel;
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/* Memory Controller hierarchy */
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/*
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* Memory Controller hierarchy
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*
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* There are basically two types of memory controller: the ones that
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* sees memory sticks ("dimms"), and the ones that sees memory ranks.
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* All old memory controllers enumerate memories per rank, but most
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* of the recent drivers enumerate memories per DIMM, instead.
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* When the memory controller is per rank, mem_is_per_rank is true.
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*/
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unsigned n_layers;
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struct edac_mc_layer *layers;
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bool mem_is_per_rank;
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@@ -560,14 +617,14 @@ struct mem_ctl_info {
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* DIMM info. Will eventually remove the entire csrows_info some day
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*/
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unsigned tot_dimms;
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struct dimm_info *dimms;
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struct dimm_info **dimms;
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/*
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* FIXME - what about controllers on other busses? - IDs must be
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* unique. dev pointer should be sufficiently unique, but
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* BUS:SLOT.FUNC numbers may not be unique.
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*/
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struct device *dev;
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struct device *pdev;
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const char *mod_name;
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const char *mod_ver;
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const char *ctl_name;
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@@ -586,12 +643,6 @@ struct mem_ctl_info {
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struct completion complete;
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/* edac sysfs device control */
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struct kobject edac_mci_kobj;
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/* list for all grp instances within a mc */
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struct list_head grp_kobj_list;
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/* Additional top controller level attributes, but specified
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* by the low level driver.
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*
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@@ -609,6 +660,13 @@ struct mem_ctl_info {
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/* the internal state of this controller instance */
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int op_state;
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#ifdef CONFIG_EDAC_DEBUG
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struct dentry *debugfs;
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u8 fake_inject_layer[EDAC_MAX_LAYERS];
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u32 fake_inject_ue;
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u16 fake_inject_count;
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#endif
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};
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#endif
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