drm/amd: Add abm level drm property
Adaptive Backlight Management (ABM) is a feature that reduces backlight level to save power, while increasing pixel contrast and pixel luminance to maintain readability and image quality. ABM will adjust in response to the pixel luminance of the displayed content. ABM is made available as a drm property on eDP monitors called "abm level", which ranges from 0 to 4. When this property is set to 0, ABM is off. Levels 1 to 4 represent different ranges of backlight reduction. At higher levels both the backlight reduction and pixel adjustment will be greater. ABM requires DMCU firmware, which is currently available for Raven ASICs only. If the feature does not work, please ensure your firmware is up to date. v2: Fix commit message, only attach property if DMCU loaded v3: Store ABM level in crtc state to accommodate dc v4: Fix ABM saving on dpms cycle Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher

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bbf854dc35
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c1ee92f94c
@@ -1686,6 +1686,15 @@ void dc_resume(struct dc *dc)
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core_link_resume(dc->links[i]);
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}
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bool dc_is_dmcu_initialized(struct dc *dc)
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{
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struct dmcu *dmcu = dc->res_pool->dmcu;
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if (dmcu)
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return dmcu->funcs->is_dmcu_initialized(dmcu);
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return false;
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}
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bool dc_submit_i2c(
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struct dc *dc,
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uint32_t link_index,
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@@ -1810,4 +1819,4 @@ void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx
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info->dcfClockDeepSleep = (unsigned int)state->bw.dcn.clk.dcfclk_deep_sleep_khz;
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info->fClock = (unsigned int)state->bw.dcn.clk.fclk_khz;
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info->phyClock = (unsigned int)state->bw.dcn.clk.phyclk_khz;
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}
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}
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@@ -742,5 +742,6 @@ void dc_set_power_state(
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struct dc *dc,
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enum dc_acpi_cm_power_state power_state);
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void dc_resume(struct dc *dc);
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bool dc_is_dmcu_initialized(struct dc *dc);
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#endif /* DC_INTERFACE_H_ */
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