Merge tag 'pinctrl-v3.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control changes from Linus Walleij:
"Here is a stash of pin control changes I have collected for the v3.19
series. Mainly new hardware support, with Intels new embedded SoC as
the especially interesting thing standing out, fully using the
subsystem.
- Force conversion of the ux500 pin control device trees and parsers
to use the generic pin control bindings.
- New driver and device tree bindings for the Qualcomm PMIC MPP pin
controller and GPIO.
- Some ACPI infrastructure for pin controllers.
- New driver for the Intel CherryView/Braswell pin controller, the
first Intel pin controller to fully take advantage of the pin
control subsystem.
- Support the Freescale i.MX VF610 variant.
- Support the sunxi A80 variant.
- Support the Samsung Exynos 4415 and Exynos 7 variants.
- Split out Intel pin controllers to their own subdirectory.
- A large slew of rockchip pin control updates, including
suspend/resume support.
- A large slew of Samsung Exynos pin controller updates.
- Various minor updates and fixes"
* tag 'pinctrl-v3.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (49 commits)
pinctrl: at91: enhance (debugfs) at91_gpio_dbg_show
pinctrl: meson: add device tree bindings documentation
gpio: tz1090: Fix error handling of irq_of_parse_and_map
pinctrl: tz1090-pinctrl.txt: Fix typo in binding
pinctrl: pinconf-generic: Declare dt_params/conf_items const
pinctrl: exynos: Add support for Exynos4415
pinctrl: exynos: Add initial driver data for Exynos7
pinctrl: exynos: Add irq_chip instance for Exynos7 wakeup interrupts
pinctrl: exynos: Consolidate irq domain callbacks
pinctrl: exynos: Generalize the eint16_31 demux code
pinctrl: samsung: Separate per-bank init and runtime data
pinctrl: samsung: Constify samsung_pin_ctrl struct
pinctrl: samsung: Constify samsung_pin_bank_type struct
pinctrl: samsung: Drop unused label field in samsung_pin_ctrl struct
pinctrl: samsung: Make samsung_pinctrl_get_soc_data use ERR_PTR()
pinctrl: Add Intel Cherryview/Braswell pin controller support
gpio / ACPI: Add knowledge about pin controllers to acpi_get_gpiod()
pinctrl: Fix path error in documentation
pinctrl: rockchip: save and restore gpio6_c6 pinmux in suspend/resume
pinctrl: rockchip: add suspend/resume functions
...
This commit is contained in:
Linus Torvalds
142
include/dt-bindings/pinctrl/qcom,pmic-gpio.h
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142
include/dt-bindings/pinctrl/qcom,pmic-gpio.h
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/*
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* This header provides constants for the Qualcomm PMIC GPIO binding.
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*/
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#ifndef _DT_BINDINGS_PINCTRL_QCOM_PMIC_GPIO_H
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#define _DT_BINDINGS_PINCTRL_QCOM_PMIC_GPIO_H
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#define PMIC_GPIO_PULL_UP_30 0
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#define PMIC_GPIO_PULL_UP_1P5 1
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#define PMIC_GPIO_PULL_UP_31P5 2
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#define PMIC_GPIO_PULL_UP_1P5_30 3
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#define PMIC_GPIO_STRENGTH_NO 0
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#define PMIC_GPIO_STRENGTH_HIGH 1
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#define PMIC_GPIO_STRENGTH_MED 2
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#define PMIC_GPIO_STRENGTH_LOW 3
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/*
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* Note: PM8018 GPIO3 and GPIO4 are supporting
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* only S3 and L2 options (1.8V)
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*/
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#define PM8018_GPIO_L6 0
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#define PM8018_GPIO_L5 1
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#define PM8018_GPIO_S3 2
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#define PM8018_GPIO_L14 3
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#define PM8018_GPIO_L2 4
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#define PM8018_GPIO_L4 5
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#define PM8018_GPIO_VDD 6
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/*
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* Note: PM8038 GPIO7 and GPIO8 are supporting
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* only L11 and L4 options (1.8V)
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*/
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#define PM8038_GPIO_VPH 0
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#define PM8038_GPIO_BB 1
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#define PM8038_GPIO_L11 2
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#define PM8038_GPIO_L15 3
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#define PM8038_GPIO_L4 4
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#define PM8038_GPIO_L3 5
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#define PM8038_GPIO_L17 6
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#define PM8058_GPIO_VPH 0
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#define PM8058_GPIO_BB 1
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#define PM8058_GPIO_S3 2
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#define PM8058_GPIO_L3 3
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#define PM8058_GPIO_L7 4
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#define PM8058_GPIO_L6 5
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#define PM8058_GPIO_L5 6
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#define PM8058_GPIO_L2 7
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#define PM8917_GPIO_VPH 0
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#define PM8917_GPIO_S4 2
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#define PM8917_GPIO_L15 3
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#define PM8917_GPIO_L4 4
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#define PM8917_GPIO_L3 5
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#define PM8917_GPIO_L17 6
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#define PM8921_GPIO_VPH 0
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#define PM8921_GPIO_BB 1
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#define PM8921_GPIO_S4 2
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#define PM8921_GPIO_L15 3
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#define PM8921_GPIO_L4 4
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#define PM8921_GPIO_L3 5
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#define PM8921_GPIO_L17 6
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/*
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* Note: PM8941 gpios from 15 to 18 are supporting
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* only S3 and L6 options (1.8V)
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*/
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#define PM8941_GPIO_VPH 0
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#define PM8941_GPIO_L1 1
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#define PM8941_GPIO_S3 2
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#define PM8941_GPIO_L6 3
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/*
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* Note: PMA8084 gpios from 15 to 18 are supporting
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* only S4 and L6 options (1.8V)
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*/
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#define PMA8084_GPIO_VPH 0
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#define PMA8084_GPIO_L1 1
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#define PMA8084_GPIO_S4 2
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#define PMA8084_GPIO_L6 3
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/* To be used with "function" */
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#define PMIC_GPIO_FUNC_NORMAL "normal"
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#define PMIC_GPIO_FUNC_PAIRED "paired"
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#define PMIC_GPIO_FUNC_FUNC1 "func1"
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#define PMIC_GPIO_FUNC_FUNC2 "func2"
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#define PMIC_GPIO_FUNC_DTEST1 "dtest1"
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#define PMIC_GPIO_FUNC_DTEST2 "dtest2"
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#define PMIC_GPIO_FUNC_DTEST3 "dtest3"
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#define PMIC_GPIO_FUNC_DTEST4 "dtest4"
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#define PM8038_GPIO1_2_LPG_DRV PMIC_GPIO_FUNC_FUNC1
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#define PM8038_GPIO3_5V_BOOST_EN PMIC_GPIO_FUNC_FUNC1
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#define PM8038_GPIO4_SSBI_ALT_CLK PMIC_GPIO_FUNC_FUNC1
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#define PM8038_GPIO5_6_EXT_REG_EN PMIC_GPIO_FUNC_FUNC1
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#define PM8038_GPIO10_11_EXT_REG_EN PMIC_GPIO_FUNC_FUNC1
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#define PM8038_GPIO6_7_CLK PMIC_GPIO_FUNC_FUNC1
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#define PM8038_GPIO9_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1
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#define PM8038_GPIO6_12_KYPD_DRV PMIC_GPIO_FUNC_FUNC2
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#define PM8058_GPIO7_8_MP3_CLK PMIC_GPIO_FUNC_FUNC1
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#define PM8058_GPIO7_8_BCLK_19P2MHZ PMIC_GPIO_FUNC_FUNC2
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#define PM8058_GPIO9_26_KYPD_DRV PMIC_GPIO_FUNC_FUNC1
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#define PM8058_GPIO21_23_UART_TX PMIC_GPIO_FUNC_FUNC2
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#define PM8058_GPIO24_26_LPG_DRV PMIC_GPIO_FUNC_FUNC2
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#define PM8058_GPIO33_BCLK_19P2MHZ PMIC_GPIO_FUNC_FUNC1
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#define PM8058_GPIO34_35_MP3_CLK PMIC_GPIO_FUNC_FUNC1
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#define PM8058_GPIO36_BCLK_19P2MHZ PMIC_GPIO_FUNC_FUNC1
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#define PM8058_GPIO37_UPL_OUT PMIC_GPIO_FUNC_FUNC1
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#define PM8058_GPIO37_UART_M_RX PMIC_GPIO_FUNC_FUNC2
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#define PM8058_GPIO38_XO_SLEEP_CLK PMIC_GPIO_FUNC_FUNC1
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#define PM8058_GPIO38_39_CLK_32KHZ PMIC_GPIO_FUNC_FUNC2
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#define PM8058_GPIO39_MP3_CLK PMIC_GPIO_FUNC_FUNC1
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#define PM8058_GPIO40_EXT_BB_EN PMIC_GPIO_FUNC_FUNC1
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#define PM8917_GPIO9_18_KEYP_DRV PMIC_GPIO_FUNC_FUNC1
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#define PM8917_GPIO20_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1
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#define PM8917_GPIO21_23_UART_TX PMIC_GPIO_FUNC_FUNC2
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#define PM8917_GPIO25_26_EXT_REG_EN PMIC_GPIO_FUNC_FUNC1
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#define PM8917_GPIO37_38_XO_SLEEP_CLK PMIC_GPIO_FUNC_FUNC1
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#define PM8917_GPIO37_38_MP3_CLK PMIC_GPIO_FUNC_FUNC2
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#define PM8941_GPIO9_14_KYPD_DRV PMIC_GPIO_FUNC_FUNC1
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#define PM8941_GPIO15_18_DIV_CLK PMIC_GPIO_FUNC_FUNC1
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#define PM8941_GPIO15_18_SLEEP_CLK PMIC_GPIO_FUNC_FUNC2
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#define PM8941_GPIO23_26_KYPD_DRV PMIC_GPIO_FUNC_FUNC1
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#define PM8941_GPIO23_26_LPG_DRV_HI PMIC_GPIO_FUNC_FUNC2
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#define PM8941_GPIO31_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1
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#define PM8941_GPIO33_36_LPG_DRV_3D PMIC_GPIO_FUNC_FUNC1
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#define PM8941_GPIO33_36_LPG_DRV_HI PMIC_GPIO_FUNC_FUNC2
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#define PMA8084_GPIO4_5_LPG_DRV PMIC_GPIO_FUNC_FUNC1
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#define PMA8084_GPIO7_10_LPG_DRV PMIC_GPIO_FUNC_FUNC1
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#define PMA8084_GPIO5_14_KEYP_DRV PMIC_GPIO_FUNC_FUNC2
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#define PMA8084_GPIO19_21_KEYP_DRV PMIC_GPIO_FUNC_FUNC2
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#define PMA8084_GPIO15_18_DIV_CLK PMIC_GPIO_FUNC_FUNC1
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#define PMA8084_GPIO15_18_SLEEP_CLK PMIC_GPIO_FUNC_FUNC2
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#define PMA8084_GPIO22_BAT_ALRM_OUT PMIC_GPIO_FUNC_FUNC1
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#endif
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44
include/dt-bindings/pinctrl/qcom,pmic-mpp.h
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44
include/dt-bindings/pinctrl/qcom,pmic-mpp.h
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/*
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* This header provides constants for the Qualcomm PMIC's
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* Multi-Purpose Pin binding.
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*/
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#ifndef _DT_BINDINGS_PINCTRL_QCOM_PMIC_MPP_H
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#define _DT_BINDINGS_PINCTRL_QCOM_PMIC_MPP_H
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/* power-source */
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#define PM8841_MPP_VPH 0
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#define PM8841_MPP_S3 2
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#define PM8941_MPP_VPH 0
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#define PM8941_MPP_L1 1
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#define PM8941_MPP_S3 2
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#define PM8941_MPP_L6 3
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#define PMA8084_MPP_VPH 0
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#define PMA8084_MPP_L1 1
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#define PMA8084_MPP_S4 2
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#define PMA8084_MPP_L6 3
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/*
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* Analog Input - Set the source for analog input.
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* To be used with "qcom,amux-route" property
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*/
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#define PMIC_MPP_AMUX_ROUTE_CH5 0
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#define PMIC_MPP_AMUX_ROUTE_CH6 1
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#define PMIC_MPP_AMUX_ROUTE_CH7 2
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#define PMIC_MPP_AMUX_ROUTE_CH8 3
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#define PMIC_MPP_AMUX_ROUTE_ABUS1 4
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#define PMIC_MPP_AMUX_ROUTE_ABUS2 5
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#define PMIC_MPP_AMUX_ROUTE_ABUS3 6
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#define PMIC_MPP_AMUX_ROUTE_ABUS4 7
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/* To be used with "function" */
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#define PMIC_MPP_FUNC_NORMAL "normal"
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#define PMIC_MPP_FUNC_PAIRED "paired"
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#define PMIC_MPP_FUNC_DTEST1 "dtest1"
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#define PMIC_MPP_FUNC_DTEST2 "dtest2"
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#define PMIC_MPP_FUNC_DTEST3 "dtest3"
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#define PMIC_MPP_FUNC_DTEST4 "dtest4"
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#endif
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