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rtlwifi: rtl8188ee: Update driver to match Realtek release of 06282014

Browse Source 
Not only does this patch update the driver to match the latest Realtek release,
it is an important step in getting the internal code source at Realtek to match
the code in the kernel. The primary reason for this is to make it easier for
Realtek to maintain the kernel source without requiring an intermediate like me.

In this process of merging the two source repositories, there are a lot
of changes in both, and this commit is rather large.

Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Larry Finger
2014-09-22 09:39:25 -05:00
committed by John W. Linville
parent f3a97e9381
commit c151aed6aa
25 changed files with 4859 additions and 4244 deletions
Download Patch File Download Diff File Expand all files Collapse all files

66
drivers/net/wireless/rtlwifi/rtl8188ee/def.h
View File

@@ -11,10 +11,6 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
@@ -111,7 +107,6 @@
#define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3)
/* [15:12] IC version(CUT): A-cut=0, B-cut=1, C-cut=2, D-cut=3
* [7] Manufacturer: TSMC=0, UMC=1
* [6:4] RF type: 1T1R=0, 1T2R=1, 2T2R=2
@@ -130,7 +125,6 @@
#define D_CUT_VERSION ((BIT(12)|BIT(13)))
#define E_CUT_VERSION BIT(14)
/* MASK */
#define IC_TYPE_MASK (BIT(0)|BIT(1)|BIT(2))
#define CHIP_TYPE_MASK BIT(3)
@@ -147,7 +141,6 @@
#define GET_CVID_ROM_VERSION(version) ((version) & ROM_VERSION_MASK)
#define GET_CVID_CUT_VERSION(version) ((version) & CUT_VERSION_MASK)
#define IS_81XXC(version) \
((GET_CVID_IC_TYPE(version) == 0) ? true : false)
#define IS_8723_SERIES(version) \
@@ -174,7 +167,7 @@
#define IS_81xxC_VENDOR_UMC_A_CUT(version) \
(IS_81XXC(version) ? ((IS_CHIP_VENDOR_UMC(version)) ? \
((GET_CVID_CUT_VERSION(version)) ? false : true) : false) : false)
#define IS_81xxC_VENDOR_UMC_B_CUT(version) \
#define IS_81XXC_VENDOR_UMC_B_CUT(version) \
(IS_81XXC(version) ? (IS_CHIP_VENDOR_UMC(version) ? \
((GET_CVID_CUT_VERSION(version) == B_CUT_VERSION) ? true \
: false) : false) : false)
@@ -225,44 +218,37 @@ enum power_polocy_config {
};
enum interface_select_pci {
INTF_SEL1_MINICARD,
INTF_SEL0_PCIE,
INTF_SEL2_RSV,
INTF_SEL3_RSV,
INTF_SEL1_MINICARD = 0,
INTF_SEL0_PCIE = 1,
INTF_SEL2_RSV = 2,
INTF_SEL3_RSV = 3,
};
enum hal_fw_c2h_cmd_id {
HAL_FW_C2H_CMD_Read_MACREG,
HAL_FW_C2H_CMD_Read_BBREG,
HAL_FW_C2H_CMD_Read_RFREG,
HAL_FW_C2H_CMD_Read_EEPROM,
HAL_FW_C2H_CMD_Read_EFUSE,
HAL_FW_C2H_CMD_Read_CAM,
HAL_FW_C2H_CMD_Get_BasicRate,
HAL_FW_C2H_CMD_Get_DataRate,
HAL_FW_C2H_CMD_Survey,
HAL_FW_C2H_CMD_SurveyDone,
HAL_FW_C2H_CMD_JoinBss,
HAL_FW_C2H_CMD_AddSTA,
HAL_FW_C2H_CMD_DelSTA,
HAL_FW_C2H_CMD_AtimDone,
HAL_FW_C2H_CMD_TX_Report,
HAL_FW_C2H_CMD_CCX_Report,
HAL_FW_C2H_CMD_DTM_Report,
HAL_FW_C2H_CMD_TX_Rate_Statistics,
HAL_FW_C2H_CMD_C2HLBK,
HAL_FW_C2H_CMD_C2HDBG,
HAL_FW_C2H_CMD_C2HFEEDBACK,
HAL_FW_C2H_CMD_READ_MACREG = 0,
HAL_FW_C2H_CMD_READ_BBREG = 1,
HAL_FW_C2H_CMD_READ_RFREG = 2,
HAL_FW_C2H_CMD_READ_EEPROM = 3,
HAL_FW_C2H_CMD_READ_EFUSE = 4,
HAL_FW_C2H_CMD_READ_CAM = 5,
HAL_FW_C2H_CMD_GET_BASICRATE = 6,
HAL_FW_C2H_CMD_GET_DATARATE = 7,
HAL_FW_C2H_CMD_SURVEY = 8,
HAL_FW_C2H_CMD_SURVEYDONE = 9,
HAL_FW_C2H_CMD_JOINBSS = 10,
HAL_FW_C2H_CMD_ADDSTA = 11,
HAL_FW_C2H_CMD_DELSTA = 12,
HAL_FW_C2H_CMD_ATIMDONE = 13,
HAL_FW_C2H_CMD_TX_REPORT = 14,
HAL_FW_C2H_CMD_CCX_REPORT = 15,
HAL_FW_C2H_CMD_DTM_REPORT = 16,
HAL_FW_C2H_CMD_TX_RATE_STATISTICS = 17,
HAL_FW_C2H_CMD_C2HLBK = 18,
HAL_FW_C2H_CMD_C2HDBG = 19,
HAL_FW_C2H_CMD_C2HFEEDBACK = 20,
HAL_FW_C2H_CMD_MAX
};
enum wake_on_wlan_mode {
ewowlandisable,
ewakeonmagicpacketonly,
ewakeonpatternmatchonly,
ewakeonbothtypepacket
};
enum rtl_desc_qsel {
QSLT_BK = 0x2,
QSLT_BE = 0x0,

791
drivers/net/wireless/rtlwifi/rtl8188ee/dm.c
View File

File diff suppressed because it is too large Load Diff

19
drivers/net/wireless/rtlwifi/rtl8188ee/dm.h
View File

@@ -156,7 +156,6 @@
#define DM_REG_SLEEP_11N 0xEE0
#define DM_REG_PMPD_ANAEN_11N 0xEEC
/*MAC REG LIST*/
#define DM_REG_BB_RST_11N 0x02
#define DM_REG_ANTSEL_PIN_11N 0x4C
@@ -168,8 +167,9 @@
#define DM_REG_EDCA_BK_11N 0x50C
#define DM_REG_TXPAUSE_11N 0x522
#define DM_REG_RESP_TX_11N 0x6D8
#define DM_REG_ANT_TRAIN_1 0x7b0
#define DM_REG_ANT_TRAIN_2 0x7b4
#define DM_REG_ANT_TRAIN_PARA1_11N 0x7b0
#define DM_REG_ANT_TRAIN_PARA2_11N 0x7b4
/*DIG Related*/
#define DM_BIT_IGI_11N 0x0000007F
@@ -208,7 +208,7 @@
#define DM_DIG_BACKOFF_MIN -4
#define DM_DIG_BACKOFF_DEFAULT 10
#define RXPATHSELECTION_SS_TH_LOW 30
#define RXPATHSELECTION_SS_TH_W 30
#define RXPATHSELECTION_DIFF_TH 18
#define DM_RATR_STA_INIT 0
@@ -238,10 +238,12 @@ struct swat_t {
u8 failure_cnt;
u8 try_flag;
u8 stop_trying;
long pre_rssi;
long trying_threshold;
u8 cur_antenna;
u8 pre_antenna;
};
enum FAT_STATE {
@@ -310,8 +312,9 @@ enum pwr_track_control_method {
void rtl88e_dm_set_tx_ant_by_tx_info(struct ieee80211_hw *hw,
u8 *pdesc, u32 mac_id);
void rtl88e_dm_ant_sel_statistics(struct ieee80211_hw *hw, u8 antsel_tr_mux,
u32 mac_id, u32 rx_pwdb_all);
void rtl88e_dm_ant_sel_statistics(struct ieee80211_hw *hw,
u8 antsel_tr_mux, u32 mac_id,
u32 rx_pwdb_all);
void rtl88e_dm_fast_antenna_training_callback(unsigned long data);
void rtl88e_dm_init(struct ieee80211_hw *hw);
void rtl88e_dm_watchdog(struct ieee80211_hw *hw);
@@ -320,7 +323,5 @@ void rtl88e_dm_init_edca_turbo(struct ieee80211_hw *hw);
void rtl88e_dm_check_txpower_tracking(struct ieee80211_hw *hw);
void rtl88e_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw);
void rtl88e_dm_txpower_track_adjust(struct ieee80211_hw *hw,
u8 type, u8 *pdirection,
u32 *poutwrite_val);
u8 type, u8 *pdirection, u32 *poutwrite_val);
#endif

217
drivers/net/wireless/rtlwifi/rtl8188ee/fw.c
View File

@@ -11,10 +11,6 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
@@ -34,8 +30,6 @@
#include "def.h"
#include "fw.h"
#include <linux/kmemleak.h>
static void _rtl88e_enable_fw_download(struct ieee80211_hw *hw, bool enable)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
@@ -62,26 +56,26 @@ static void _rtl88e_fw_block_write(struct ieee80211_hw *hw,
const u8 *buffer, u32 size)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u32 blk_sz = sizeof(u32);
u8 *buf_ptr = (u8 *)buffer;
u32 blocksize = sizeof(u32);
u8 *bufferptr = (u8 *)buffer;
u32 *pu4BytePtr = (u32 *)buffer;
u32 i, offset, blk_cnt, remain;
u32 i, offset, blockcount, remainsize;
blk_cnt = size / blk_sz;
remain = size % blk_sz;
blockcount = size / blocksize;
remainsize = size % blocksize;
for (i = 0; i < blk_cnt; i++) {
offset = i * blk_sz;
for (i = 0; i < blockcount; i++) {
offset = i * blocksize;
rtl_write_dword(rtlpriv, (FW_8192C_START_ADDRESS + offset),
*(pu4BytePtr + i));
}
if (remain) {
offset = blk_cnt * blk_sz;
buf_ptr += offset;
for (i = 0; i < remain; i++) {
if (remainsize) {
offset = blockcount * blocksize;
bufferptr += offset;
for (i = 0; i < remainsize; i++) {
rtl_write_byte(rtlpriv, (FW_8192C_START_ADDRESS +
offset + i), *(buf_ptr + i));
offset + i), *(bufferptr + i));
}
}
}
@@ -119,32 +113,33 @@ static void _rtl88e_write_fw(struct ieee80211_hw *hw,
enum version_8188e version, u8 *buffer, u32 size)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u8 *buf_ptr = buffer;
u32 page_no, remain;
u8 *bufferptr = (u8 *)buffer;
u32 pagenums, remainsize;
u32 page, offset;
RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "FW size is %d bytes,\n", size);
_rtl88e_fill_dummy(buf_ptr, &size);
_rtl88e_fill_dummy(bufferptr, &size);
page_no = size / FW_8192C_PAGE_SIZE;
remain = size % FW_8192C_PAGE_SIZE;
pagenums = size / FW_8192C_PAGE_SIZE;
remainsize = size % FW_8192C_PAGE_SIZE;
if (page_no > 8) {
if (pagenums > 8) {
RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
"Page numbers should not greater then 8\n");
}
for (page = 0; page < page_no; page++) {
for (page = 0; page < pagenums; page++) {
offset = page * FW_8192C_PAGE_SIZE;
_rtl88e_fw_page_write(hw, page, (buf_ptr + offset),
_rtl88e_fw_page_write(hw, page, (bufferptr + offset),
FW_8192C_PAGE_SIZE);
}
if (remain) {
offset = page_no * FW_8192C_PAGE_SIZE;
page = page_no;
_rtl88e_fw_page_write(hw, page, (buf_ptr + offset), remain);
if (remainsize) {
offset = pagenums * FW_8192C_PAGE_SIZE;
page = pagenums;
_rtl88e_fw_page_write(hw, page, (bufferptr + offset),
remainsize);
}
}
@@ -199,7 +194,8 @@ exit:
return err;
}
int rtl88e_download_fw(struct ieee80211_hw *hw, bool buse_wake_on_wlan_fw)
int rtl88e_download_fw(struct ieee80211_hw *hw,
bool buse_wake_on_wlan_fw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
@@ -237,9 +233,14 @@ int rtl88e_download_fw(struct ieee80211_hw *hw, bool buse_wake_on_wlan_fw)
_rtl88e_enable_fw_download(hw, false);
err = _rtl88e_fw_free_to_go(hw);
if (err) {
RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
"Firmware is not ready to run!\n");
} else {
RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD,
"Firmware is ready to run!\n");
}
RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG,
"Firmware is%s ready to run!\n", err ? " not" : "");
return 0;
}
@@ -266,9 +267,9 @@ static void _rtl88e_fill_h2c_command(struct ieee80211_hw *hw,
bool isfw_read = false;
u8 buf_index = 0;
bool write_sucess = false;
u8 wait_h2c_limit = 100;
u8 wait_h2c_limmit = 100;
u8 wait_writeh2c_limit = 100;
u8 boxc[4], boxext[2];
u8 boxcontent[4], boxextcontent[4];
u32 h2c_waitcounter = 0;
unsigned long flag;
u8 idx;
@@ -331,18 +332,17 @@ static void _rtl88e_fill_h2c_command(struct ieee80211_hw *hw,
box_extreg = REG_HMEBOX_EXT_3;
break;
default:
RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
"switch case not processed\n");
RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
"switch case not process\n");
break;
}
isfw_read = _rtl88e_check_fw_read_last_h2c(hw, boxnum);
while (!isfw_read) {
wait_h2c_limit--;
if (wait_h2c_limit == 0) {
wait_h2c_limmit--;
if (wait_h2c_limmit == 0) {
RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
"Waiting too long for FW read "
"clear HMEBox(%d)!\n", boxnum);
"Waiting too long for FW read clear HMEBox(%d)!\n",
boxnum);
break;
}
@@ -351,20 +351,20 @@ static void _rtl88e_fill_h2c_command(struct ieee80211_hw *hw,
isfw_read = _rtl88e_check_fw_read_last_h2c(hw, boxnum);
u1b_tmp = rtl_read_byte(rtlpriv, 0x130);
RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
"Waiting for FW read clear HMEBox(%d)!!! "
"0x130 = %2x\n", boxnum, u1b_tmp);
"Waiting for FW read clear HMEBox(%d)!!! 0x130 = %2x\n",
boxnum, u1b_tmp);
}
if (!isfw_read) {
RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
"Write H2C register BOX[%d] fail!!!!! "
"Fw do not read.\n", boxnum);
"Write H2C register BOX[%d] fail!!!!! Fw do not read.\n",
boxnum);
break;
}
memset(boxc, 0, sizeof(boxc));
memset(boxext, 0, sizeof(boxext));
boxc[0] = element_id;
memset(boxcontent, 0, sizeof(boxcontent));
memset(boxextcontent, 0, sizeof(boxextcontent));
boxcontent[0] = element_id;
RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
"Write element_id box_reg(%4x) = %2x\n",
box_reg, element_id);
@@ -373,33 +373,38 @@ static void _rtl88e_fill_h2c_command(struct ieee80211_hw *hw,
case 1:
case 2:
case 3:
/*boxc[0] &= ~(BIT(7));*/
memcpy((u8 *)(boxc) + 1, cmd_b + buf_index, cmd_len);
/*boxcontent[0] &= ~(BIT(7));*/
memcpy((u8 *)(boxcontent) + 1,
cmd_b + buf_index, cmd_len);
for (idx = 0; idx < 4; idx++)
rtl_write_byte(rtlpriv, box_reg+idx, boxc[idx]);
for (idx = 0; idx < 4; idx++) {
rtl_write_byte(rtlpriv, box_reg + idx,
boxcontent[idx]);
}
break;
case 4:
case 5:
case 6:
case 7:
/*boxc[0] |= (BIT(7));*/
memcpy((u8 *)(boxext), cmd_b + buf_index+3, cmd_len-3);
memcpy((u8 *)(boxc) + 1, cmd_b + buf_index, 3);
/*boxcontent[0] |= (BIT(7));*/
memcpy((u8 *)(boxextcontent),
cmd_b + buf_index+3, cmd_len-3);
memcpy((u8 *)(boxcontent) + 1,
cmd_b + buf_index, 3);
for (idx = 0; idx < 2; idx++) {
rtl_write_byte(rtlpriv, box_extreg + idx,
boxext[idx]);
boxextcontent[idx]);
}
for (idx = 0; idx < 4; idx++) {
rtl_write_byte(rtlpriv, box_reg + idx,
boxc[idx]);
boxcontent[idx]);
}
break;
default:
RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
"switch case not processed\n");
RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
"switch case not process\n");
break;
}
@@ -422,18 +427,19 @@ static void _rtl88e_fill_h2c_command(struct ieee80211_hw *hw,
}
void rtl88e_fill_h2c_cmd(struct ieee80211_hw *hw,
u8 element_id, u32 cmd_len, u8 *cmd_b)
u8 element_id, u32 cmd_len, u8 *cmdbuffer)
{
struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
u32 tmp_cmdbuf[2];
if (rtlhal->fw_ready == false) {
RT_ASSERT(false, "fail H2C cmd - Fw download fail!!!\n");
if (!rtlhal->fw_ready) {
RT_ASSERT(false,
"return H2C cmd because of Fw download fail!!!\n");
return;
}
memset(tmp_cmdbuf, 0, 8);
memcpy(tmp_cmdbuf, cmd_b, cmd_len);
memcpy(tmp_cmdbuf, cmdbuffer, cmd_len);
_rtl88e_fill_h2c_command(hw, element_id, cmd_len, (u8 *)&tmp_cmdbuf);
return;
@@ -448,7 +454,8 @@ void rtl88e_firmware_selfreset(struct ieee80211_hw *hw)
rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1b_tmp & (~BIT(2))));
rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1b_tmp | BIT(2)));
RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
"8051Reset88E(): 8051 reset success.\n");
"8051Reset88E(): 8051 reset success\n");
}
void rtl88e_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode)
@@ -456,14 +463,14 @@ void rtl88e_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode)
struct rtl_priv *rtlpriv = rtl_priv(hw);
u8 u1_h2c_set_pwrmode[H2C_88E_PWEMODE_LENGTH] = { 0 };
struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
u8 power_state = 0;
u8 rlbm, power_state = 0;
RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "FW LPS mode = %d\n", mode);
SET_H2CCMD_PWRMODE_PARM_MODE(u1_h2c_set_pwrmode, ((mode) ? 1 : 0));
SET_H2CCMD_PWRMODE_PARM_RLBM(u1_h2c_set_pwrmode, 0);
rlbm = 0;/*YJ, temp, 120316. FW now not support RLBM=2.*/
SET_H2CCMD_PWRMODE_PARM_RLBM(u1_h2c_set_pwrmode, rlbm);
SET_H2CCMD_PWRMODE_PARM_SMART_PS(u1_h2c_set_pwrmode,
(rtlpriv->mac80211.p2p) ?
ppsc->smart_ps : 1);
(rtlpriv->mac80211.p2p) ? ppsc->smart_ps : 1);
SET_H2CCMD_PWRMODE_PARM_AWAKE_INTERVAL(u1_h2c_set_pwrmode,
ppsc->reg_max_lps_awakeintvl);
SET_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(u1_h2c_set_pwrmode, 0);
@@ -471,13 +478,14 @@ void rtl88e_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode)
power_state |= FW_PWR_STATE_ACTIVE;
else
power_state |= FW_PWR_STATE_RF_OFF;
SET_H2CCMD_PWRMODE_PARM_PWR_STATE(u1_h2c_set_pwrmode, power_state);
RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
"rtl92c_set_fw_pwrmode(): u1_h2c_set_pwrmode\n",
u1_h2c_set_pwrmode, H2C_88E_PWEMODE_LENGTH);
rtl88e_fill_h2c_cmd(hw, H2C_88E_SETPWRMODE, H2C_88E_PWEMODE_LENGTH,
u1_h2c_set_pwrmode);
rtl88e_fill_h2c_cmd(hw, H2C_88E_SETPWRMODE,
H2C_88E_PWEMODE_LENGTH, u1_h2c_set_pwrmode);
}
void rtl88e_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, u8 mstatus)
@@ -499,8 +507,9 @@ void rtl88e_set_fw_ap_off_load_cmd(struct ieee80211_hw *hw,
SET_H2CCMD_AP_OFFLOAD_HIDDEN(u1_apoffload_parm, mac->hiddenssid);
SET_H2CCMD_AP_OFFLOAD_DENYANY(u1_apoffload_parm, 0);
rtl88e_fill_h2c_cmd(hw, H2C_88E_AP_OFFLOAD, H2C_88E_AP_OFFLOAD_LENGTH,
u1_apoffload_parm);
rtl88e_fill_h2c_cmd(hw, H2C_88E_AP_OFFLOAD,
H2C_88E_AP_OFFLOAD_LENGTH, u1_apoffload_parm);
}
static bool _rtl88e_cmd_send_packet(struct ieee80211_hw *hw,
@@ -511,6 +520,7 @@ static bool _rtl88e_cmd_send_packet(struct ieee80211_hw *hw,
struct rtl8192_tx_ring *ring;
struct rtl_tx_desc *pdesc;
struct sk_buff *pskb = NULL;
u8 own;
unsigned long flags;
ring = &rtlpci->tx_ring[BEACON_QUEUE];
@@ -522,6 +532,7 @@ static bool _rtl88e_cmd_send_packet(struct ieee80211_hw *hw,
spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
pdesc = &ring->desc[0];
own = (u8)rtlpriv->cfg->ops->get_desc((u8 *)pdesc, true, HW_DESC_OWN);
rtlpriv->cfg->ops->fill_tx_cmddesc(hw, (u8 *)pdesc, 1, 1, skb);
@@ -656,14 +667,15 @@ void rtl88e_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool b_dl_finished)
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
struct sk_buff *skb = NULL;
u32 totalpacketlen;
u8 u1RsvdPageLoc[5] = { 0 };
bool rtstatus;
u8 u1rsvdpageloc[5] = { 0 };
bool b_dlok = false;
u8 *beacon;
u8 *pspoll;
u8 *p_pspoll;
u8 *nullfunc;
u8 *probersp;
u8 *p_probersp;
/*---------------------------------------------------------
* (1) beacon
*---------------------------------------------------------
@@ -676,12 +688,12 @@ void rtl88e_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool b_dl_finished)
* (2) ps-poll
*--------------------------------------------------------
*/
pspoll = &reserved_page_packet[PSPOLL_PG * 128];
SET_80211_PS_POLL_AID(pspoll, (mac->assoc_id | 0xc000));
SET_80211_PS_POLL_BSSID(pspoll, mac->bssid);
SET_80211_PS_POLL_TA(pspoll, mac->mac_addr);
p_pspoll = &reserved_page_packet[PSPOLL_PG * 128];
SET_80211_PS_POLL_AID(p_pspoll, (mac->assoc_id | 0xc000));
SET_80211_PS_POLL_BSSID(p_pspoll, mac->bssid);
SET_80211_PS_POLL_TA(p_pspoll, mac->mac_addr);
SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(u1RsvdPageLoc, PSPOLL_PG);
SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(u1rsvdpageloc, PSPOLL_PG);
/*--------------------------------------------------------
* (3) null data
@@ -692,18 +704,18 @@ void rtl88e_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool b_dl_finished)
SET_80211_HDR_ADDRESS2(nullfunc, mac->mac_addr);
SET_80211_HDR_ADDRESS3(nullfunc, mac->bssid);
SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(u1RsvdPageLoc, NULL_PG);
SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(u1rsvdpageloc, NULL_PG);
/*---------------------------------------------------------
* (4) probe response
*----------------------------------------------------------
*/
probersp = &reserved_page_packet[PROBERSP_PG * 128];
SET_80211_HDR_ADDRESS1(probersp, mac->bssid);
SET_80211_HDR_ADDRESS2(probersp, mac->mac_addr);
SET_80211_HDR_ADDRESS3(probersp, mac->bssid);
p_probersp = &reserved_page_packet[PROBERSP_PG * 128];
SET_80211_HDR_ADDRESS1(p_probersp, mac->bssid);
SET_80211_HDR_ADDRESS2(p_probersp, mac->mac_addr);
SET_80211_HDR_ADDRESS3(p_probersp, mac->bssid);
SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(u1RsvdPageLoc, PROBERSP_PG);
SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(u1rsvdpageloc, PROBERSP_PG);
totalpacketlen = TOTAL_RESERVED_PKT_LEN;
@@ -712,33 +724,36 @@ void rtl88e_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool b_dl_finished)
&reserved_page_packet[0], totalpacketlen);
RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
"rtl88e_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL\n",
u1RsvdPageLoc, 3);
u1rsvdpageloc, 3);
skb = dev_alloc_skb(totalpacketlen);
if (!skb)
return;
kmemleak_not_leak(skb);
memcpy(skb_put(skb, totalpacketlen),
&reserved_page_packet, totalpacketlen);
if (_rtl88e_cmd_send_packet(hw, skb)) {
rtstatus = _rtl88e_cmd_send_packet(hw, skb);
if (rtstatus)
b_dlok = true;
if (b_dlok) {
RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
"Set RSVD page location to Fw.\n");
RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
"H2C_RSVDPAGE:\n", u1RsvdPageLoc, 3);
"H2C_RSVDPAGE:\n", u1rsvdpageloc, 3);
rtl88e_fill_h2c_cmd(hw, H2C_88E_RSVDPAGE,
sizeof(u1RsvdPageLoc), u1RsvdPageLoc);
sizeof(u1rsvdpageloc), u1rsvdpageloc);
} else
RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
"Set RSVD page location to Fw FAIL!!!!!!.\n");
}
/*Shoud check FW support p2p or not.*/
/*Should check FW support p2p or not.*/
static void rtl88e_set_p2p_ctw_period_cmd(struct ieee80211_hw *hw, u8 ctwindow)
{
u8 u1_ctwindow_period[1] = { ctwindow};
rtl88e_fill_h2c_cmd(hw, H2C_88E_P2P_PS_CTW_CMD, 1, u1_ctwindow_period);
}
void rtl88e_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw, u8 p2p_ps_state)
@@ -755,7 +770,7 @@ void rtl88e_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw, u8 p2p_ps_state)
switch (p2p_ps_state) {
case P2P_PS_DISABLE:
RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "P2P_PS_DISABLE\n");
memset(p2p_ps_offload, 0, sizeof(struct p2p_ps_offload_t));
memset(p2p_ps_offload, 0, 1);
break;
case P2P_PS_ENABLE:
RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "P2P_PS_ENABLE\n");
@@ -765,6 +780,7 @@ void rtl88e_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw, u8 p2p_ps_state)
ctwindow = p2pinfo->ctwindow;
rtl88e_set_p2p_ctw_period_cmd(hw, ctwindow);
}
/* hw only support 2 set of NoA */
for (i = 0 ; i < p2pinfo->noa_num; i++) {
/* To control the register setting for which NOA*/
@@ -804,7 +820,7 @@ void rtl88e_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw, u8 p2p_ps_state)
if (P2P_ROLE_GO == rtlpriv->mac80211.p2p) {
p2p_ps_offload->role = 1;
p2p_ps_offload->allstasleep = 0;
p2p_ps_offload->allstasleep = -1;
} else {
p2p_ps_offload->role = 0;
}
@@ -827,4 +843,5 @@ void rtl88e_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw, u8 p2p_ps_state)
rtl88e_fill_h2c_cmd(hw, H2C_88E_P2P_PS_OFFLOAD, 1,
(u8 *)p2p_ps_offload);
}

19
drivers/net/wireless/rtlwifi/rtl8188ee/fw.h
View File

@@ -56,7 +56,8 @@
/* Fw PS state for RPWM.
*BIT[2:0] = HW state
* BIT[3] = Protocol PS state, 1: register active state, 0: register sleep state
*BIT[3] = Protocol PS state,
*1: register active state , 0: register sleep state
*BIT[4] = sub-state
*/
#define FW_PS_GO_ON BIT(0)
@@ -98,10 +99,13 @@
#define FW_PS_STATE_S2 (FW_PS_RF_OFF)
#define FW_PS_STATE_S3 (FW_PS_ALL_ON)
#define FW_PS_STATE_S4 ((FW_PS_ST_ACTIVE) | (FW_PS_ALL_ON))
/* ((FW_PS_RF_ON) | (FW_PS_REGISTER_ACTIVE))*/
#define FW_PS_STATE_ALL_ON_88E (FW_PS_CLOCK_ON)
/* (FW_PS_RF_ON)*/
#define FW_PS_STATE_RF_ON_88E (FW_PS_CLOCK_ON)
/* 0x0*/
#define FW_PS_STATE_RF_OFF_88E (FW_PS_CLOCK_ON)
/* (FW_PS_STATE_RF_OFF)*/
#define FW_PS_STATE_RF_OFF_LOW_PWR_88E (FW_PS_CLOCK_OFF)
#define FW_PS_STATE_ALL_ON_92C (FW_PS_STATE_S4)
@@ -146,7 +150,7 @@ struct rtl92c_firmware_header {
u32 rsvd5;
};
enum rtl8192c_h2c_cmd {
enum rtl8188e_h2c_cmd {
H2C_88E_RSVDPAGE = 0,
H2C_88E_JOINBSSRPT = 1,
H2C_88E_SCAN = 2,
@@ -289,13 +293,12 @@ enum rtl8192c_h2c_cmd {
int rtl88e_download_fw(struct ieee80211_hw *hw,
bool buse_wake_on_wlan_fw);
void rtl88e_fill_h2c_cmd(struct ieee80211_hw *hw, u8 element_id,
u32 cmd_len, u8 *p_cmdbuffer);
u32 cmd_len, u8 *cmdbuffer);
void rtl88e_firmware_selfreset(struct ieee80211_hw *hw);
void rtl88e_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode);
void rtl88e_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw,
u8 mstatus);
void rtl88e_set_fw_ap_off_load_cmd(struct ieee80211_hw *hw, u8 enable);
void rtl88e_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, u8 mstatus);
void rtl88e_set_fw_ap_off_load_cmd(struct ieee80211_hw *hw,
u8 ap_offload_enable);
void rtl88e_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool b_dl_finished);
void rtl88e_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw, u8 p2p_ps_state);
#endif

1104
drivers/net/wireless/rtlwifi/rtl8188ee/hw.c
View File

File diff suppressed because it is too large Load Diff

41
drivers/net/wireless/rtlwifi/rtl8188ee/led.c
View File

@@ -32,7 +32,7 @@
#include "reg.h"
#include "led.h"
static void rtl88ee_init_led(struct ieee80211_hw *hw,
static void _rtl88ee_init_led(struct ieee80211_hw *hw,
struct rtl_led *pled, enum rtl_led_pin ledpin)
{
pled->hw = hw;
@@ -53,16 +53,16 @@ void rtl88ee_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled)
break;
case LED_PIN_LED0:
ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG2);
rtl_write_byte(rtlpriv, REG_LEDCFG2,
(ledcfg & 0xf0) | BIT(5) | BIT(6));
rtl_write_byte(rtlpriv,
REG_LEDCFG2, (ledcfg & 0xf0) | BIT(5) | BIT(6));
break;
case LED_PIN_LED1:
ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG1);
rtl_write_byte(rtlpriv, REG_LEDCFG1, ledcfg & 0x10);
break;
default:
RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
"switch case not processed\n");
RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
"switch case not process\n");
break;
}
pled->ledon = true;
@@ -73,7 +73,6 @@ void rtl88ee_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
u8 ledcfg;
u8 val;
RT_TRACE(rtlpriv, COMP_LED, DBG_LOUD,
"LedAddr:%X ledpin=%d\n", REG_LEDCFG2, pled->ledpin);
@@ -84,15 +83,15 @@ void rtl88ee_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
case LED_PIN_LED0:
ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG2);
ledcfg &= 0xf0;
val = ledcfg | BIT(3) | BIT(5) | BIT(6);
if (pcipriv->ledctl.led_opendrain == true) {
rtl_write_byte(rtlpriv, REG_LEDCFG2, val);
if (pcipriv->ledctl.led_opendrain) {
rtl_write_byte(rtlpriv, REG_LEDCFG2,
(ledcfg | BIT(3) | BIT(5) | BIT(6)));
ledcfg = rtl_read_byte(rtlpriv, REG_MAC_PINMUX_CFG);
val = ledcfg & 0xFE;
rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, val);
} else {
rtl_write_byte(rtlpriv, REG_LEDCFG2, val);
}
rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG,
(ledcfg & 0xFE));
} else
rtl_write_byte(rtlpriv, REG_LEDCFG2,
(ledcfg | BIT(3) | BIT(5) | BIT(6)));
break;
case LED_PIN_LED1:
ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG1);
@@ -100,8 +99,8 @@ void rtl88ee_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
rtl_write_byte(rtlpriv, REG_LEDCFG1, (ledcfg | BIT(3)));
break;
default:
RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
"switch case not processed\n");
RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
"switch case not process\n");
break;
}
pled->ledon = false;
@@ -110,17 +109,15 @@ void rtl88ee_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
void rtl88ee_init_sw_leds(struct ieee80211_hw *hw)
{
struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
rtl88ee_init_led(hw, &(pcipriv->ledctl.sw_led0), LED_PIN_LED0);
rtl88ee_init_led(hw, &(pcipriv->ledctl.sw_led1), LED_PIN_LED1);
_rtl88ee_init_led(hw, &pcipriv->ledctl.sw_led0, LED_PIN_LED0);
_rtl88ee_init_led(hw, &pcipriv->ledctl.sw_led1, LED_PIN_LED1);
}
static void rtl88ee_sw_led_control(struct ieee80211_hw *hw,
static void _rtl88ee_sw_led_control(struct ieee80211_hw *hw,
enum led_ctl_mode ledaction)
{
struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
switch (ledaction) {
case LED_CTL_POWER_ON:
case LED_CTL_LINK:
@@ -153,5 +150,5 @@ void rtl88ee_led_control(struct ieee80211_hw *hw,
}
RT_TRACE(rtlpriv, COMP_LED, DBG_TRACE, "ledaction %d,\n",
ledaction);
rtl88ee_sw_led_control(hw, ledaction);
_rtl88ee_sw_led_control(hw, ledaction);
}

4
drivers/net/wireless/rtlwifi/rtl8188ee/led.h
View File

@@ -11,10 +11,6 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*

1957
drivers/net/wireless/rtlwifi/rtl8188ee/phy.c
View File

File diff suppressed because it is too large Load Diff

14
drivers/net/wireless/rtlwifi/rtl8188ee/phy.h
View File

@@ -11,10 +11,6 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
@@ -30,7 +26,9 @@
#ifndef __RTL92C_PHY_H__
#define __RTL92C_PHY_H__
/*It must always set to 4, otherwise read efuse table secquence will be wrong.*/
/* MAX_TX_COUNT must always set to 4, otherwise read efuse
* table secquence will be wrong.
*/
#define MAX_TX_COUNT 4
#define MAX_PRECMD_CNT 16
@@ -46,7 +44,7 @@
#define IQK_BB_REG_NUM 9
#define MAX_TOLERANCE 5
#define IQK_DELAY_TIME 10
#define IDX_MAP 15
#define INDEX_MAPPING_NUM 15
#define APK_BB_REG_NUM 5
#define APK_AFE_REG_NUM 16
@@ -160,7 +158,6 @@ struct r_antenna_select_cck {
u8 r_ccktx_enable:4;
};
struct efuse_contents {
u8 mac_addr[ETH_ALEN];
u8 cck_tx_power_idx[6];
@@ -217,12 +214,15 @@ void rtl88e_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
void rtl88e_phy_get_txpower_level(struct ieee80211_hw *hw,
long *powerlevel);
void rtl88e_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel);
void rtl88e_phy_scan_operation_backup(struct ieee80211_hw *hw,
u8 operation);
void rtl88e_phy_set_bw_mode_callback(struct ieee80211_hw *hw);
void rtl88e_phy_set_bw_mode(struct ieee80211_hw *hw,
enum nl80211_channel_type ch_type);
void rtl88e_phy_sw_chnl_callback(struct ieee80211_hw *hw);
u8 rtl88e_phy_sw_chnl(struct ieee80211_hw *hw);
void rtl88e_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery);
void rtl92c_phy_ap_calibrate(struct ieee80211_hw *hw, char delta);
void rtl88e_phy_lc_calibrate(struct ieee80211_hw *hw);
void rtl88e_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain);
bool rtl88e_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,

24
drivers/net/wireless/rtlwifi/rtl8188ee/pwrseq.c
View File

@@ -11,10 +11,6 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
@@ -32,21 +28,21 @@
/* drivers should parse below arrays and do the corresponding actions */
/*3 Power on Array*/
struct wlan_pwr_cfg rtl8188e_power_on_flow[RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS +
RTL8188E_TRANS_END_STEPS] = {
struct wlan_pwr_cfg rtl8188E_power_on_flow[RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS
+ RTL8188E_TRANS_END_STEPS] = {
RTL8188E_TRANS_CARDEMU_TO_ACT
RTL8188E_TRANS_END
};
/*3Radio off GPIO Array */
struct wlan_pwr_cfg rtl8188e_radio_off_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS
struct wlan_pwr_cfg rtl8188E_radio_off_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS
+ RTL8188E_TRANS_END_STEPS] = {
RTL8188E_TRANS_ACT_TO_CARDEMU
RTL8188E_TRANS_END
};
/*3Card Disable Array*/
struct wlan_pwr_cfg rtl8188e_card_disable_flow
struct wlan_pwr_cfg rtl8188E_card_disable_flow
[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS +
RTL8188E_TRANS_END_STEPS] = {
@@ -56,7 +52,7 @@ struct wlan_pwr_cfg rtl8188e_card_disable_flow
};
/*3 Card Enable Array*/
struct wlan_pwr_cfg rtl8188e_card_enable_flow
struct wlan_pwr_cfg rtl8188E_card_enable_flow
[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS +
RTL8188E_TRANS_END_STEPS] = {
@@ -66,7 +62,7 @@ struct wlan_pwr_cfg rtl8188e_card_enable_flow
};
/*3Suspend Array*/
struct wlan_pwr_cfg rtl8188e_suspend_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS
struct wlan_pwr_cfg rtl8188E_suspend_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS
+ RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS
+ RTL8188E_TRANS_END_STEPS] = {
RTL8188E_TRANS_ACT_TO_CARDEMU
@@ -75,7 +71,7 @@ struct wlan_pwr_cfg rtl8188e_suspend_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS
};
/*3 Resume Array*/
struct wlan_pwr_cfg rtl8188e_resume_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS
struct wlan_pwr_cfg rtl8188E_resume_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS
+ RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS
+ RTL8188E_TRANS_END_STEPS] = {
RTL8188E_TRANS_SUS_TO_CARDEMU
@@ -84,7 +80,7 @@ struct wlan_pwr_cfg rtl8188e_resume_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS
};
/*3HWPDN Array*/
struct wlan_pwr_cfg rtl8188e_hwpdn_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS
struct wlan_pwr_cfg rtl8188E_hwpdn_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS
+ RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS
+ RTL8188E_TRANS_END_STEPS] = {
RTL8188E_TRANS_ACT_TO_CARDEMU
@@ -93,7 +89,7 @@ struct wlan_pwr_cfg rtl8188e_hwpdn_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS
};
/*3 Enter LPS */
struct wlan_pwr_cfg rtl8188e_enter_lps_flow[RTL8188E_TRANS_ACT_TO_LPS_STEPS
struct wlan_pwr_cfg rtl8188E_enter_lps_flow[RTL8188E_TRANS_ACT_TO_LPS_STEPS
+ RTL8188E_TRANS_END_STEPS] = {
/*FW behavior*/
RTL8188E_TRANS_ACT_TO_LPS
@@ -101,7 +97,7 @@ struct wlan_pwr_cfg rtl8188e_enter_lps_flow[RTL8188E_TRANS_ACT_TO_LPS_STEPS
};
/*3 Leave LPS */
struct wlan_pwr_cfg rtl8188e_leave_lps_flow[RTL8188E_TRANS_LPS_TO_ACT_STEPS
struct wlan_pwr_cfg rtl8188E_leave_lps_flow[RTL8188E_TRANS_LPS_TO_ACT_STEPS
+ RTL8188E_TRANS_END_STEPS] = {
/*FW behavior*/
RTL8188E_TRANS_LPS_TO_ACT

325
drivers/net/wireless/rtlwifi/rtl8188ee/pwrseq.h
View File

@@ -11,10 +11,6 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
@@ -30,27 +26,27 @@
#ifndef __RTL8723E_PWRSEQ_H__
#define __RTL8723E_PWRSEQ_H__
/*
Check document WM-20110607-Paul-RTL8188E_Power_Architecture-R02.vsd
There are 6 HW Power States:
0: POFF--Power Off
1: PDN--Power Down
2: CARDEMU--Card Emulation
3: ACT--Active Mode
4: LPS--Low Power State
5: SUS--Suspend
The transision from different states are defined below
TRANS_CARDEMU_TO_ACT
TRANS_ACT_TO_CARDEMU
TRANS_CARDEMU_TO_SUS
TRANS_SUS_TO_CARDEMU
TRANS_CARDEMU_TO_PDN
TRANS_ACT_TO_LPS
TRANS_LPS_TO_ACT
TRANS_END
PWR SEQ Version: rtl8188e_PwrSeq_V09.h
#include "pwrseqcmd.h"
/* Check document WM-20110607-Paul-RTL8188E_Power_Architecture-R02.vsd
* There are 6 HW Power States:
* 0: POFF--Power Off
* 1: PDN--Power Down
* 2: CARDEMU--Card Emulation
* 3: ACT--Active Mode
* 4: LPS--Low Power State
* 5: SUS--Suspend
*
* The transision from different states are defined below
* TRANS_CARDEMU_TO_ACT
* TRANS_ACT_TO_CARDEMU
* TRANS_CARDEMU_TO_SUS
* TRANS_SUS_TO_CARDEMU
* TRANS_CARDEMU_TO_PDN
* TRANS_ACT_TO_LPS
* TRANS_LPS_TO_ACT
*
* TRANS_END
* PWR SEQ Version: rtl8188E_PwrSeq_V09.h
*/
#define RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS 10
@@ -63,264 +59,253 @@
#define RTL8188E_TRANS_LPS_TO_ACT_STEPS 15
#define RTL8188E_TRANS_END_STEPS 1
/* The following macros have the following format:
* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value
* comments },
*/
#define RTL8188E_TRANS_CARDEMU_TO_ACT \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
/* wait till 0x04[17] = 1 power ready*/ \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)}, \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1) \
/* wait till 0x04[17] = 1 power ready*/}, \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
/* 0x02[1:0] = 0 reset BB*/ \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0)|BIT(1), 0}, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0)|BIT(1), 0 \
/* 0x02[1:0] = 0 reset BB*/}, \
{0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
/*0x24[23] = 2b'01 schmit trigger */ \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)}, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7) \
/*0x24[23] = 2b'01 schmit trigger */}, \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
/* 0x04[15] = 0 disable HWPDN (control by DRV)*/ \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0}, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0 \
/* 0x04[15] = 0 disable HWPDN (control by DRV)*/}, \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
/*0x04[12:11] = 2b'00 disable WL suspend*/ \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4)|BIT(3), 0}, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4)|BIT(3), 0 \
/*0x04[12:11] = 2b'00 disable WL suspend*/}, \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
/*0x04[8] = 1 polling until return 0*/ \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0) \
/*0x04[8] = 1 polling until return 0*/}, \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
/*wait till 0x04[8] = 0*/ \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0}, \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0 \
/*wait till 0x04[8] = 0*/}, \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, /*LDO normal mode*/\
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0 \
/*LDO normal mode*/}, \
{0x0074, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, /*SDIO Driving*/\
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4) \
/*SDIO Driving*/},
#define RTL8188E_TRANS_ACT_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/\
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
/*0x1F[7:0] = 0 turn off RF*/}, \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, /*LDO Sleep mode*/\
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4) \
/*LDO Sleep mode*/}, \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
/*0x04[9] = 1 turn off MAC by HW state machine*/ \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1) \
/*0x04[9] = 1 turn off MAC by HW state machine*/}, \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
/*wait till 0x04[9] = 0 polling until return 0 to disable*/ \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0}, \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0 \
/*wait till 0x04[9] = 0 polling until return 0 to disable*/},
#define RTL8188E_TRANS_CARDEMU_TO_SUS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, \
/*0x04[12:11] = 2b'01enable WL suspend*/ \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3) \
/*0x04[12:11] = 2b'01enable WL suspend*/}, \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
/*0x04[12:11] = 2b'11enable WL suspend for PCIe*/ \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)|BIT(4)},\
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)|BIT(4) \
/*0x04[12:11] = 2b'11enable WL suspend for PCIe*/}, \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, \
/* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */\
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, BIT(7)}, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, BIT(7) \
/* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */},\
{0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, \
/*Clear SIC_EN register 0x40[12] = 1'b0 */ \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0 \
/*Clear SIC_EN register 0x40[12] = 1'b0 */}, \
{0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, \
/*Set USB suspend enable local register 0xfe10[4]= 1 */ \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4) \
/*Set USB suspend enable local register 0xfe10[4]=1 */}, \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
/*Set SDIO suspend local register*/ \
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0) \
/*Set SDIO suspend local register*/}, \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
/*wait power state to suspend*/ \
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0},
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0 \
/*wait power state to suspend*/},
#define RTL8188E_TRANS_SUS_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
/*Set SDIO suspend local register*/ \
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, \
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0 \
/*Set SDIO suspend local register*/}, \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
/*wait power state to suspend*/ \
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)}, \
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1) \
/*wait power state to suspend*/}, \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
/*0x04[12:11] = 2b'01enable WL suspend*/ \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0},
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), 0 \
/*0x04[12:11] = 2b'01enable WL suspend*/},
#define RTL8188E_TRANS_CARDEMU_TO_CARDDIS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
{0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
/*0x24[23] = 2b'01 schmit trigger */ \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)}, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7) \
/*0x24[23] = 2b'01 schmit trigger */}, \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, \
/*0x04[12:11] = 2b'01 enable WL suspend*/ \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) \
/*0x04[12:11] = 2b'01 enable WL suspend*/}, \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, \
/* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */\
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
/* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */},\
{0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, \
/*Clear SIC_EN register 0x40[12] = 1'b0 */ \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0 \
/*Clear SIC_EN register 0x40[12] = 1'b0 */}, \
{0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, \
/*Set USB suspend enable local register 0xfe10[4]= 1 */ \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4) \
/*Set USB suspend enable local register 0xfe10[4]=1 */}, \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
/*Set SDIO suspend local register*/ \
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0) \
/*Set SDIO suspend local register*/}, \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
PWR_CMD_POLLING, BIT(1), 0}, /*wait power state to suspend*/
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0 \
/*wait power state to suspend*/},
#define RTL8188E_TRANS_CARDDIS_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
PWR_BASEADDR_SDIO,\
PWR_CMD_WRITE, BIT(0), 0}, /*Set SDIO suspend local register*/ \
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0 \
/*Set SDIO suspend local register*/}, \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
PWR_BASEADDR_SDIO,\
PWR_CMD_POLLING, BIT(1), BIT(1)}, /*wait power state to suspend*/\
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1) \
/*wait power state to suspend*/}, \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, \
PWR_CMD_WRITE, BIT(3)|BIT(4), 0}, \
/*0x04[12:11] = 2b'01enable WL suspend*/
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0 \
/*0x04[12:11] = 2b'01enable WL suspend*/},
#define RTL8188E_TRANS_CARDEMU_TO_PDN \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0},/* 0x04[16] = 0*/ \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0/* 0x04[16] = 0*/}, \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)},/* 0x04[15] = 1*/
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7) \
/* 0x04[15] = 1*/},
#define RTL8188E_TRANS_PDN_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},/* 0x04[15] = 0*/
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0/* 0x04[15] = 0*/},
#define RTL8188E_TRANS_ACT_TO_LPS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F \
/*Tx Pause*/}, \
{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
/*zero if no pkt is tx*/\
PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
/*Should be zero if no packet is transmitting*/}, \
{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
/*Should be zero if no packet is transmitting*/ \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
/*Should be zero if no packet is transmitting*/}, \
{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
/*Should be zero if no packet is transmitting*/ \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
/*Should be zero if no packet is transmitting*/}, \
{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
/*Should be zero if no packet is transmitting*/ \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
/*Should be zero if no packet is transmitting*/}, \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
/*CCK and OFDM are disabled, and clock are gated*/ \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0 \
/*CCK and OFDM are disabled,and clock are gated*/}, \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/\
PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US \
/*Delay 1us*/}, \
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/ \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F \
/*Reset MAC TRX*/}, \
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
/*check if removed later*/ \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0 \
/*check if removed later*/}, \
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
/*Respond TxOK to scheduler*/ \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), BIT(5)}, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), BIT(5) \
/*Respond TxOK to scheduler*/},
#define RTL8188E_TRANS_LPS_TO_ACT \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/ \
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84 \
/*SDIO RPWM*/}, \
{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/ \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84 \
/*USB RPWM*/}, \
{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/ \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84 \
/*PCIe RPWM*/}, \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/ \
PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS \
/*Delay*/}, \
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
/*. 0x08[4] = 0 switch TSF to 40M*/ \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0 \
/*. 0x08[4] = 0 switch TSF to 40M*/}, \
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
/*Polling 0x109[7]= 0 TSF in 40M*/ \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(7), 0}, \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(7), 0 \
/*Polling 0x109[7]=0 TSF in 40M*/}, \
{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
/*. 0x29[7:6] = 2b'00 enable BB clock*/ \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6)|BIT(7), 0}, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6)|BIT(7), 0 \
/*. 0x29[7:6] = 2b'00 enable BB clock*/}, \
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
/*. 0x101[1] = 1*/\
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1) \
/*. 0x101[1] = 1*/}, \
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
/*. 0x100[7:0] = 0xFF enable WMAC TRX*/\
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF \
/*. 0x100[7:0] = 0xFF enable WMAC TRX*/}, \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
/*. 0x02[1:0] = 2b'11 enable BB macro*/\
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1)|BIT(0), BIT(1)|BIT(0)}, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1)|BIT(0), BIT(1)|BIT(0) \
/*. 0x02[1:0] = 2b'11 enable BB macro*/}, \
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
/*. 0x522 = 0*/},
#define RTL8188E_TRANS_END \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
0, PWR_CMD_END, 0, 0}
extern struct wlan_pwr_cfg rtl8188e_power_on_flow
extern struct wlan_pwr_cfg rtl8188E_power_on_flow
[RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS +
RTL8188E_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8188e_radio_off_flow
extern struct wlan_pwr_cfg rtl8188E_radio_off_flow
[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
RTL8188E_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8188e_card_disable_flow
extern struct wlan_pwr_cfg rtl8188E_card_disable_flow
[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS +
RTL8188E_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8188e_card_enable_flow
extern struct wlan_pwr_cfg rtl8188E_card_enable_flow
[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS +
RTL8188E_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8188e_suspend_flow
extern struct wlan_pwr_cfg rtl8188E_suspend_flow
[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS +
RTL8188E_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8188e_resume_flow
extern struct wlan_pwr_cfg rtl8188E_resume_flow
[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS +
RTL8188E_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8188e_hwpdn_flow
extern struct wlan_pwr_cfg rtl8188E_hwpdn_flow
[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS +
RTL8188E_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8188e_enter_lps_flow
extern struct wlan_pwr_cfg rtl8188E_enter_lps_flow
[RTL8188E_TRANS_ACT_TO_LPS_STEPS +
RTL8188E_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8188e_leave_lps_flow
extern struct wlan_pwr_cfg rtl8188E_leave_lps_flow
[RTL8188E_TRANS_LPS_TO_ACT_STEPS +
RTL8188E_TRANS_END_STEPS];
/* RTL8723 Power Configuration CMDs for PCIe interface */
#define RTL8188E_NIC_PWR_ON_FLOW rtl8188e_power_on_flow
#define RTL8188E_NIC_RF_OFF_FLOW rtl8188e_radio_off_flow
#define RTL8188E_NIC_DISABLE_FLOW rtl8188e_card_disable_flow
#define RTL8188E_NIC_ENABLE_FLOW rtl8188e_card_enable_flow
#define RTL8188E_NIC_SUSPEND_FLOW rtl8188e_suspend_flow
#define RTL8188E_NIC_RESUME_FLOW rtl8188e_resume_flow
#define RTL8188E_NIC_PDN_FLOW rtl8188e_hwpdn_flow
#define RTL8188E_NIC_LPS_ENTER_FLOW rtl8188e_enter_lps_flow
#define RTL8188E_NIC_LPS_LEAVE_FLOW rtl8188e_leave_lps_flow
#define RTL8188E_NIC_PWR_ON_FLOW rtl8188E_power_on_flow
#define RTL8188E_NIC_RF_OFF_FLOW rtl8188E_radio_off_flow
#define RTL8188E_NIC_DISABLE_FLOW rtl8188E_card_disable_flow
#define RTL8188E_NIC_ENABLE_FLOW rtl8188E_card_enable_flow
#define RTL8188E_NIC_SUSPEND_FLOW rtl8188E_suspend_flow
#define RTL8188E_NIC_RESUME_FLOW rtl8188E_resume_flow
#define RTL8188E_NIC_PDN_FLOW rtl8188E_hwpdn_flow
#define RTL8188E_NIC_LPS_ENTER_FLOW rtl8188E_enter_lps_flow
#define RTL8188E_NIC_LPS_LEAVE_FLOW rtl8188E_leave_lps_flow
#endif

99
drivers/net/wireless/rtlwifi/rtl8188ee/pwrseqcmd.c
View File

@@ -11,10 +11,6 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
@@ -39,69 +35,68 @@
*
* 2011.07.07, added by Roger.
*/
bool rtl88_hal_pwrseqcmdparsing(struct rtl_priv *rtlpriv, u8 cut_version,
bool rtl_hal_pwrseqcmdparsing(struct rtl_priv *rtlpriv, u8 cut_version,
u8 fab_version, u8 interface_type,
struct wlan_pwr_cfg pwrcfgcmd[])
{
struct wlan_pwr_cfg cmd = {0};
bool polling_bit = false;
struct wlan_pwr_cfg pwr_cfg_cmd = {0};
bool b_polling_bit = false;
u32 ary_idx = 0;
u8 val = 0;
u8 value = 0;
u32 offset = 0;
u32 polling_count = 0;
u32 max_polling_cnt = 5000;
do {
cmd = pwrcfgcmd[ary_idx];
pwr_cfg_cmd = pwrcfgcmd[ary_idx];
RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
"rtl88_hal_pwrseqcmdparsing(): offset(%#x), cut_msk(%#x), fab_msk(%#x),"
"interface_msk(%#x), base(%#x), cmd(%#x), msk(%#x), val(%#x)\n",
GET_PWR_CFG_OFFSET(cmd),
GET_PWR_CFG_CUT_MASK(cmd),
GET_PWR_CFG_FAB_MASK(cmd),
GET_PWR_CFG_INTF_MASK(cmd),
GET_PWR_CFG_BASE(cmd),
GET_PWR_CFG_CMD(cmd),
GET_PWR_CFG_MASK(cmd),
GET_PWR_CFG_VALUE(cmd));
"rtl_hal_pwrseqcmdparsing(): offset(%#x),cut_msk(%#x), fab_msk(%#x), interface_msk(%#x), base(%#x), cmd(%#x), msk(%#x), value(%#x)\n",
GET_PWR_CFG_OFFSET(pwr_cfg_cmd),
GET_PWR_CFG_CUT_MASK(pwr_cfg_cmd),
GET_PWR_CFG_FAB_MASK(pwr_cfg_cmd),
GET_PWR_CFG_INTF_MASK(pwr_cfg_cmd),
GET_PWR_CFG_BASE(pwr_cfg_cmd),
GET_PWR_CFG_CMD(pwr_cfg_cmd),
GET_PWR_CFG_MASK(pwr_cfg_cmd),
GET_PWR_CFG_VALUE(pwr_cfg_cmd));
if ((GET_PWR_CFG_FAB_MASK(cmd) & fab_version) &&
(GET_PWR_CFG_CUT_MASK(cmd) & cut_version) &&
(GET_PWR_CFG_INTF_MASK(cmd) & interface_type)) {
switch (GET_PWR_CFG_CMD(cmd)) {
if ((GET_PWR_CFG_FAB_MASK(pwr_cfg_cmd)&fab_version) &&
(GET_PWR_CFG_CUT_MASK(pwr_cfg_cmd)&cut_version) &&
(GET_PWR_CFG_INTF_MASK(pwr_cfg_cmd)&interface_type)) {
switch (GET_PWR_CFG_CMD(pwr_cfg_cmd)) {
case PWR_CMD_READ:
RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
"rtl88_hal_pwrseqcmdparsing(): PWR_CMD_READ\n");
"rtl_hal_pwrseqcmdparsing(): PWR_CMD_READ\n");
break;
case PWR_CMD_WRITE: {
case PWR_CMD_WRITE:
RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
"rtl88_hal_pwrseqcmdparsing(): PWR_CMD_WRITE\n");
offset = GET_PWR_CFG_OFFSET(cmd);
"rtl_hal_pwrseqcmdparsing(): PWR_CMD_WRITE\n");
offset = GET_PWR_CFG_OFFSET(pwr_cfg_cmd);
/*Read the val from system register*/
val = rtl_read_byte(rtlpriv, offset);
val &= (~(GET_PWR_CFG_MASK(cmd)));
val |= (GET_PWR_CFG_VALUE(cmd) &
GET_PWR_CFG_MASK(cmd));
/*Read the value from system register*/
value = rtl_read_byte(rtlpriv, offset);
value &= (~(GET_PWR_CFG_MASK(pwr_cfg_cmd)));
value |= (GET_PWR_CFG_VALUE(pwr_cfg_cmd)
& GET_PWR_CFG_MASK(pwr_cfg_cmd));
/*Write the val back to sytem register*/
rtl_write_byte(rtlpriv, offset, val);
}
/*Write the back to sytem register*/
rtl_write_byte(rtlpriv, offset, value);
break;
case PWR_CMD_POLLING:
RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
"rtl88_hal_pwrseqcmdparsing(): PWR_CMD_POLLING\n");
polling_bit = false;
offset = GET_PWR_CFG_OFFSET(cmd);
"rtl_hal_pwrseqcmdparsing(): PWR_CMD_POLLING\n");
b_polling_bit = false;
offset = GET_PWR_CFG_OFFSET(pwr_cfg_cmd);
do {
val = rtl_read_byte(rtlpriv, offset);
value = rtl_read_byte(rtlpriv, offset);
val = val & GET_PWR_CFG_MASK(cmd);
if (val == (GET_PWR_CFG_VALUE(cmd) &
GET_PWR_CFG_MASK(cmd)))
polling_bit = true;
value &= GET_PWR_CFG_MASK(pwr_cfg_cmd);
if (value ==
(GET_PWR_CFG_VALUE(pwr_cfg_cmd) &
GET_PWR_CFG_MASK(pwr_cfg_cmd)))
b_polling_bit = true;
else
udelay(10);
@@ -111,28 +106,28 @@ bool rtl88_hal_pwrseqcmdparsing(struct rtl_priv *rtlpriv, u8 cut_version,
"polling fail in pwrseqcmd\n");
return false;
}
} while (!polling_bit);
} while (!b_polling_bit);
break;
case PWR_CMD_DELAY:
RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
"rtl88_hal_pwrseqcmdparsing(): PWR_CMD_DELAY\n");
if (GET_PWR_CFG_VALUE(cmd) == PWRSEQ_DELAY_US)
udelay(GET_PWR_CFG_OFFSET(cmd));
"rtl_hal_pwrseqcmdparsing(): PWR_CMD_DELAY\n");
if (GET_PWR_CFG_VALUE(pwr_cfg_cmd) ==
PWRSEQ_DELAY_US)
udelay(GET_PWR_CFG_OFFSET(pwr_cfg_cmd));
else
mdelay(GET_PWR_CFG_OFFSET(cmd));
mdelay(GET_PWR_CFG_OFFSET(pwr_cfg_cmd));
break;
case PWR_CMD_END:
RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
"rtl88_hal_pwrseqcmdparsing(): PWR_CMD_END\n");
"rtl_hal_pwrseqcmdparsing(): PWR_CMD_END\n");
return true;
default:
RT_ASSERT(false,
"rtl88_hal_pwrseqcmdparsing(): Unknown CMD!!\n");
"rtl_hal_pwrseqcmdparsing(): Unknown CMD!!\n");
break;
}
}
ary_idx++;
} while (1);

19
drivers/net/wireless/rtlwifi/rtl8188ee/pwrseqcmd.h
View File

@@ -75,18 +75,19 @@ struct wlan_pwr_cfg {
u8 cmd:4;
u8 msk;
u8 value;
};
#define GET_PWR_CFG_OFFSET(__PWR) (__PWR.offset)
#define GET_PWR_CFG_CUT_MASK(__PWR) (__PWR.cut_msk)
#define GET_PWR_CFG_FAB_MASK(__PWR) (__PWR.fab_msk)
#define GET_PWR_CFG_INTF_MASK(__PWR) (__PWR.interface_msk)
#define GET_PWR_CFG_BASE(__PWR) (__PWR.base)
#define GET_PWR_CFG_CMD(__PWR) (__PWR.cmd)
#define GET_PWR_CFG_MASK(__PWR) (__PWR.msk)
#define GET_PWR_CFG_VALUE(__PWR) (__PWR.value)
#define GET_PWR_CFG_OFFSET(__PWR_CMD) __PWR_CMD.offset
#define GET_PWR_CFG_CUT_MASK(__PWR_CMD) __PWR_CMD.cut_msk
#define GET_PWR_CFG_FAB_MASK(__PWR_CMD) __PWR_CMD.fab_msk
#define GET_PWR_CFG_INTF_MASK(__PWR_CMD) __PWR_CMD.interface_msk
#define GET_PWR_CFG_BASE(__PWR_CMD) __PWR_CMD.base
#define GET_PWR_CFG_CMD(__PWR_CMD) __PWR_CMD.cmd
#define GET_PWR_CFG_MASK(__PWR_CMD) __PWR_CMD.msk
#define GET_PWR_CFG_VALUE(__PWR_CMD) __PWR_CMD.value
bool rtl88_hal_pwrseqcmdparsing(struct rtl_priv *rtlpriv, u8 cut_version,
bool rtl_hal_pwrseqcmdparsing(struct rtl_priv *rtlpriv, u8 cut_version,
u8 fab_version, u8 interface_type,
struct wlan_pwr_cfg pwrcfgcmd[]);

262
drivers/net/wireless/rtlwifi/rtl8188ee/reg.h
View File

@@ -11,10 +11,6 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
@@ -50,9 +46,8 @@
#define REG_LDOHCI12_CTRL 0x0022
#define REG_LPLDO_CTRL 0x0023
#define REG_AFE_XTAL_CTRL 0x0024
#define REG_AFE_LDO_CTRL 0x0027 /* 1.5v for 8188EE test
* chip, 1.4v for MP chip
*/
/* 1.5v for 8188EE test chip, 1.4v for MP chip */
#define REG_AFE_LDO_CTRL 0x0027
#define REG_AFE_PLL_CTRL 0x0028
#define REG_EFUSE_CTRL 0x0030
#define REG_EFUSE_TEST 0x0034
@@ -81,7 +76,6 @@
#define REG_WOL_EVENT 0x0081
#define REG_MCUTSTCFG 0x0084
#define REG_HIMR 0x00B0
#define REG_HISR 0x00B4
#define REG_HIMRE 0x00B8
@@ -152,14 +146,15 @@
#define REG_RQPN_NPQ 0x0214
#define REG_RXDMA_AGG_PG_TH 0x0280
#define REG_FW_UPD_RDPTR 0x0284 /* FW shall update this
* register before FW * write
* RXPKT_RELEASE_POLL to 1
*/
#define REG_RXDMA_CONTROL 0x0286 /* Control the RX DMA.*/
#define REG_RXPKT_NUM 0x0287 /* The number of packets
* in RXPKTBUF.
/* FW shall update this register before
* FW write RXPKT_RELEASE_POLL to 1
*/
#define REG_FW_UPD_RDPTR 0x0284
/* Control the RX DMA.*/
#define REG_RXDMA_CONTROL 0x0286
/* The number of packets in RXPKTBUF. */
#define REG_RXPKT_NUM 0x0287
#define REG_PCIE_CTRL_REG 0x0300
#define REG_INT_MIG 0x0304
#define REG_BCNQ_DESA 0x0308
@@ -181,7 +176,6 @@
#define REG_UART_TX_DESA 0x0370
#define REG_UART_RX_DESA 0x0378
#define REG_HDAQ_DESA_NODEF 0x0000
#define REG_CMDQ_DESA_NODEF 0x0000
@@ -194,7 +188,6 @@
#define REG_BCNQ_INFORMATION 0x0418
#define REG_TXPKT_EMPTY 0x041A
#define REG_CPU_MGQ_INFORMATION 0x041C
#define REG_FWHW_TXQ_CTRL 0x0420
#define REG_HWSEQ_CTRL 0x0423
@@ -392,15 +385,18 @@
#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2)
#define GPIO_MOD (REG_GPIO_PIN_CTRL+3)
/* 8723/8188E Host System Interrupt Mask Register (offset 0x58, 32 byte) */
/*8723/8188E Host System Interrupt
*Mask Register (offset 0x58, 32 byte)
*/
#define HSIMR_GPIO12_0_INT_EN BIT(0)
#define HSIMR_SPS_OCP_INT_EN BIT(5)
#define HSIMR_RON_INT_EN BIT(6)
#define HSIMR_PDN_INT_EN BIT(7)
#define HSIMR_GPIO9_INT_EN BIT(25)
/* 8723/8188E Host System Interrupt Status Register (offset 0x5C, 32 byte) */
/* 8723/8188E Host System Interrupt
* Status Register (offset 0x5C, 32 byte)
*/
#define HSISR_GPIO12_0_INT BIT(0)
#define HSISR_SPS_OCP_INT BIT(5)
#define HSISR_RON_INT_EN BIT(6)
@@ -411,7 +407,6 @@
#define MSR_ADHOC 0x01
#define MSR_INFRA 0x02
#define MSR_AP 0x03
#define MSR_MASK 0x03
#define RRSR_RSC_OFFSET 21
#define RRSR_SHORT_OFFSET 23
@@ -544,80 +539,100 @@
**********************************************/
#define IMR_DISABLED 0x0
/* IMR DW0(0x0060-0063) Bit 0-31 */
#define IMR_TXCCK BIT(30) /* TXRPT interrupt when CCX bit of
* the packet is set
*/
#define IMR_PSTIMEOUT BIT(29) /* Power Save Time Out Interrupt */
#define IMR_GTINT4 BIT(28) /* When GTIMER4 expires,
* this bit is set to 1
*/
#define IMR_GTINT3 BIT(27) /* When GTIMER3 expires,
* this bit is set to 1
*/
#define IMR_TBDER BIT(26) /* Transmit Beacon0 Error */
#define IMR_TBDOK BIT(25) /* Transmit Beacon0 OK */
#define IMR_TSF_BIT32_TOGGLE BIT(24) /* TSF Timer BIT32 toggle ind int */
#define IMR_BCNDMAINT0 BIT(20) /* Beacon DMA Interrupt 0 */
#define IMR_BCNDOK0 BIT(16) /* Beacon Queue DMA OK0 */
#define IMR_HSISR_IND_ON_INT BIT(15) /* HSISR Indicator (HSIMR & HSISR is
* true, this bit is set to 1)
*/
#define IMR_BCNDMAINT_E BIT(14) /* Beacon DMA Int Extension for Win7 */
#define IMR_ATIMEND BIT(12) /* CTWidnow End or ATIM Window End */
#define IMR_HISR1_IND_INT BIT(11) /* HISR1 Indicator (HISR1 & HIMR1 is
* true, this bit is set to 1)
*/
#define IMR_C2HCMD BIT(10) /* CPU to Host Command INT Status,
* Write 1 clear
*/
#define IMR_CPWM2 BIT(9) /* CPU power Mode exchange INT Status,
* Write 1 clear
*/
#define IMR_CPWM BIT(8) /* CPU power Mode exchange INT Status,
* Write 1 clear
*/
#define IMR_HIGHDOK BIT(7) /* High Queue DMA OK */
#define IMR_MGNTDOK BIT(6) /* Management Queue DMA OK */
#define IMR_BKDOK BIT(5) /* AC_BK DMA OK */
#define IMR_BEDOK BIT(4) /* AC_BE DMA OK */
#define IMR_VIDOK BIT(3) /* AC_VI DMA OK */
#define IMR_VODOK BIT(2) /* AC_VO DMA OK */
#define IMR_RDU BIT(1) /* Rx Descriptor Unavailable */
#define IMR_ROK BIT(0) /* Receive DMA OK */
/* TXRPT interrupt when CCX bit of the packet is set */
#define IMR_TXCCK BIT(30)
/* Power Save Time Out Interrupt */
#define IMR_PSTIMEOUT BIT(29)
/* When GTIMER4 expires, this bit is set to 1 */
#define IMR_GTINT4 BIT(28)
/* When GTIMER3 expires, this bit is set to 1 */
#define IMR_GTINT3 BIT(27)
/* Transmit Beacon0 Error */
#define IMR_TBDER BIT(26)
/* Transmit Beacon0 OK */
#define IMR_TBDOK BIT(25)
/* TSF Timer BIT32 toggle indication interrupt */
#define IMR_TSF_BIT32_TOGGLE BIT(24)
/* Beacon DMA Interrupt 0 */
#define IMR_BCNDMAINT0 BIT(20)
/* Beacon Queue DMA OK0 */
#define IMR_BCNDOK0 BIT(16)
/* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */
#define IMR_HSISR_IND_ON_INT BIT(15)
/* Beacon DMA Interrupt Extension for Win7 */
#define IMR_BCNDMAINT_E BIT(14)
/* CTWidnow End or ATIM Window End */
#define IMR_ATIMEND BIT(12)
/* HISR1 Indicator (HISR1 & HIMR1 is true, this bit is set to 1)*/
#define IMR_HISR1_IND_INT BIT(11)
/* CPU to Host Command INT Status, Write 1 clear */
#define IMR_C2HCMD BIT(10)
/* CPU power Mode exchange INT Status, Write 1 clear */
#define IMR_CPWM2 BIT(9)
/* CPU power Mode exchange INT Status, Write 1 clear */
#define IMR_CPWM BIT(8)
/* High Queue DMA OK */
#define IMR_HIGHDOK BIT(7)
/* Management Queue DMA OK */
#define IMR_MGNTDOK BIT(6)
/* AC_BK DMA OK */
#define IMR_BKDOK BIT(5)
/* AC_BE DMA OK */
#define IMR_BEDOK BIT(4)
/* AC_VI DMA OK */
#define IMR_VIDOK BIT(3)
/* AC_VO DMA OK */
#define IMR_VODOK BIT(2)
/* Rx Descriptor Unavailable */
#define IMR_RDU BIT(1)
/* Receive DMA OK */
#define IMR_ROK BIT(0)
/* IMR DW1(0x00B4-00B7) Bit 0-31 */
#define IMR_BCNDMAINT7 BIT(27) /* Beacon DMA Interrupt 7 */
#define IMR_BCNDMAINT6 BIT(26) /* Beacon DMA Interrupt 6 */
#define IMR_BCNDMAINT5 BIT(25) /* Beacon DMA Interrupt 5 */
#define IMR_BCNDMAINT4 BIT(24) /* Beacon DMA Interrupt 4 */
#define IMR_BCNDMAINT3 BIT(23) /* Beacon DMA Interrupt 3 */
#define IMR_BCNDMAINT2 BIT(22) /* Beacon DMA Interrupt 2 */
#define IMR_BCNDMAINT1 BIT(21) /* Beacon DMA Interrupt 1 */
#define IMR_BCNDOK7 BIT(20) /* Beacon Queue DMA OK Interrup 7 */
#define IMR_BCNDOK6 BIT(19) /* Beacon Queue DMA OK Interrup 6 */
#define IMR_BCNDOK5 BIT(18) /* Beacon Queue DMA OK Interrup 5 */
#define IMR_BCNDOK4 BIT(17) /* Beacon Queue DMA OK Interrup 4 */
#define IMR_BCNDOK3 BIT(16) /* Beacon Queue DMA OK Interrup 3 */
#define IMR_BCNDOK2 BIT(15) /* Beacon Queue DMA OK Interrup 2 */
#define IMR_BCNDOK1 BIT(14) /* Beacon Queue DMA OK Interrup 1 */
#define IMR_ATIMEND_E BIT(13) /* ATIM Window End Extension for Win7 */
#define IMR_TXERR BIT(11) /* Tx Err Flag Int Status,
* write 1 clear.
*/
#define IMR_RXERR BIT(10) /* Rx Err Flag INT Status,
* Write 1 clear
*/
#define IMR_TXFOVW BIT(9) /* Transmit FIFO Overflow */
#define IMR_RXFOVW BIT(8) /* Receive FIFO Overflow */
/* Beacon DMA Interrupt 7 */
#define IMR_BCNDMAINT7 BIT(27)
/* Beacon DMA Interrupt 6 */
#define IMR_BCNDMAINT6 BIT(26)
/* Beacon DMA Interrupt 5 */
#define IMR_BCNDMAINT5 BIT(25)
/* Beacon DMA Interrupt 4 */
#define IMR_BCNDMAINT4 BIT(24)
/* Beacon DMA Interrupt 3 */
#define IMR_BCNDMAINT3 BIT(23)
/* Beacon DMA Interrupt 2 */
#define IMR_BCNDMAINT2 BIT(22)
/* Beacon DMA Interrupt 1 */
#define IMR_BCNDMAINT1 BIT(21)
/* Beacon Queue DMA OK Interrup 7 */
#define IMR_BCNDOK7 BIT(20)
/* Beacon Queue DMA OK Interrup 6 */
#define IMR_BCNDOK6 BIT(19)
/* Beacon Queue DMA OK Interrup 5 */
#define IMR_BCNDOK5 BIT(18)
/* Beacon Queue DMA OK Interrup 4 */
#define IMR_BCNDOK4 BIT(17)
/* Beacon Queue DMA OK Interrup 3 */
#define IMR_BCNDOK3 BIT(16)
/* Beacon Queue DMA OK Interrup 2 */
#define IMR_BCNDOK2 BIT(15)
/* Beacon Queue DMA OK Interrup 1 */
#define IMR_BCNDOK1 BIT(14)
/* ATIM Window End Extension for Win7 */
#define IMR_ATIMEND_E BIT(13)
/* Tx Error Flag Interrupt Status, write 1 clear. */
#define IMR_TXERR BIT(11)
/* Rx Error Flag INT Status, Write 1 clear */
#define IMR_RXERR BIT(10)
/* Transmit FIFO Overflow */
#define IMR_TXFOVW BIT(9)
/* Receive FIFO Overflow */
#define IMR_RXFOVW BIT(8)
#define HWSET_MAX_SIZE 512
#define EFUSE_MAX_SECTION 64
#define EFUSE_REAL_CONTENT_LEN 256
#define EFUSE_OOB_PROTECT_BYTES 18 /* PG data exclude header,
* dummy 7 bytes frome CP
* test and reserved 1byte.
*/
/* PG data exclude header, dummy 7 bytes frome CP test and reserved 1byte.*/
#define EFUSE_OOB_PROTECT_BYTES 18
#define EEPROM_DEFAULT_TSSI 0x0
#define EEPROM_DEFAULT_TXPOWERDIFF 0x0
@@ -1271,7 +1286,7 @@
#define RPMAC_CCKPLCPHEADER 0x144
#define RPMAC_CCKCRC16 0x148
#define RPMAC_OFDMRXCRC32OK 0x170
#define RPMAC_OFDMRXCRC32Er 0x174
#define RPMAC_OFDMRXCRC32ER 0x174
#define RPMAC_OFDMRXPARITYER 0x178
#define RPMAC_OFDMRXCRC8ER 0x17c
#define RPMAC_CCKCRXRC16ER 0x180
@@ -1309,8 +1324,8 @@
#define RFPGA0_XAB_RFINTERFACESW 0x870
#define RFPGA0_XCD_RFINTERFACESW 0x874
#define rFPGA0_XAB_RFPARAMETER 0x878
#define rFPGA0_XCD_RFPARAMETER 0x87c
#define RFPGA0_XAB_RFPARAMETER 0x878
#define RFPGA0_XCD_RFPARAMETER 0x87c
#define RFPGA0_ANALOGPARAMETER1 0x880
#define RFPGA0_ANALOGPARAMETER2 0x884
@@ -1358,7 +1373,6 @@
#define RCCK0_FACOUNTERUPPER 0xa58
#define RCCK0_CCA_CNT 0xa60
/* PageB(0xB00) */
#define RPDP_ANTA 0xb00
#define RPDP_ANTA_4 0xb04
@@ -1372,7 +1386,7 @@
#define RPDP_ANTA_24 0xb24
#define RCONFIG_PMPD_ANTA 0xb28
#define RCONFIG_RAM64X16 0xb2c
#define RCONFIG_RAM64x16 0xb2c
#define RBNDA 0xb30
#define RHSSIPAR 0xb34
@@ -1396,14 +1410,14 @@
#define RBNDB 0xba0
#define RAPK 0xbd8
#define rPm_Rx0_AntA 0xbdc
#define rPm_Rx1_AntA 0xbe0
#define rPm_Rx2_AntA 0xbe4
#define rPm_Rx3_AntA 0xbe8
#define rPm_Rx0_AntB 0xbec
#define rPm_Rx1_AntB 0xbf0
#define rPm_Rx2_AntB 0xbf4
#define rPm_Rx3_AntB 0xbf8
#define RPM_RX0_ANTA 0xbdc
#define RPM_RX1_ANTA 0xbe0
#define RPM_RX2_ANTA 0xbe4
#define RPM_RX3_ANTA 0xbe8
#define RPM_RX0_ANTB 0xbec
#define RPM_RX1_ANTB 0xbf0
#define RPM_RX2_ANTB 0xbf4
#define RPM_RX3_ANTB 0xbf8
/*Page C*/
#define ROFDM0_LSTF 0xc00
@@ -1413,13 +1427,13 @@
#define ROFDM0_TRSWISOLATION 0xc0c
#define ROFDM0_XARXAFE 0xc10
#define ROFDM0_XARXIQIMBAL 0xc14
#define ROFDM0_XARXIQIMBALANCE 0xc14
#define ROFDM0_XBRXAFE 0xc18
#define ROFDM0_XBRXIQIMBAL 0xc1c
#define ROFDM0_XBRXIQIMBALANCE 0xc1c
#define ROFDM0_XCRXAFE 0xc20
#define ROFDM0_XCRXIQIMBAL 0xc24
#define ROFDM0_XCRXIQIMBANLANCE 0xc24
#define ROFDM0_XDRXAFE 0xc28
#define ROFDM0_XDRXIQIMBAL 0xc2c
#define ROFDM0_XDRXIQIMBALANCE 0xc2c
#define ROFDM0_RXDETECTOR1 0xc30
#define ROFDM0_RXDETECTOR2 0xc34
@@ -1428,8 +1442,8 @@
#define ROFDM0_RXDSP 0xc40
#define ROFDM0_CFOANDDAGC 0xc44
#define ROFDM0_CCADROPTHRES 0xc48
#define ROFDM0_ECCATHRES 0xc4c
#define ROFDM0_CCADROPTHRESHOLD 0xc48
#define ROFDM0_ECCATHRESHOLD 0xc4c
#define ROFDM0_XAAGCCORE1 0xc50
#define ROFDM0_XAAGCCORE2 0xc54
@@ -1445,13 +1459,13 @@
#define ROFDM0_AGCRSSITABLE 0xc78
#define ROFDM0_HTSTFAGC 0xc7c
#define ROFDM0_XATXIQIMBAL 0xc80
#define ROFDM0_XATXIQIMBALANCE 0xc80
#define ROFDM0_XATXAFE 0xc84
#define ROFDM0_XBTXIQIMBAL 0xc88
#define ROFDM0_XBTXIQIMBALANCE 0xc88
#define ROFDM0_XBTXAFE 0xc8c
#define ROFDM0_XCTXIQIMBAL 0xc90
#define ROFDM0_XCTXIQIMBALANCE 0xc90
#define ROFDM0_XCTXAFE 0xc94
#define ROFDM0_XDTXIQIMBAL 0xc98
#define ROFDM0_XDTXIQIMBALANCE 0xc98
#define ROFDM0_XDTXAFE 0xc9c
#define ROFDM0_RXIQEXTANTA 0xca0
@@ -1467,7 +1481,6 @@
#define ROFDM0_FRAMESYNC 0xcf0
#define ROFDM0_DFSREPORT 0xcf4
#define ROFDM1_LSTF 0xd00
#define ROFDM1_TRXPATHENABLE 0xd04
@@ -1835,7 +1848,7 @@
#define BPSD_ANTENNA_PATH 0x30
#define BPSD_IQ_SWITCH 0x40
#define BPSD_RX_TRIGGER 0x400000
#define BPSD_TX_TRIGGERCW 0x80000000
#define BPSD_TX_TRIGGER 0x80000000
#define BPSD_SINE_TONE_SCALE 0x7f000000
#define BPSD_REPORT 0xffff
@@ -1990,7 +2003,7 @@
#define BCFOSUMWEIGHT 0x80
#define BDAGCENABLE 0x10000
#define BTXIQIMB_A 0x3ff
#define BTXIQIMB_B 0xfc00
#define BTXIQIMB_b 0xfc00
#define BTXIQIMB_C 0x3f0000
#define BTXIQIMB_D 0xffc00000
#define BTXIDCOFFSET 0xff
@@ -2216,6 +2229,22 @@
#define BWORD1 0xc
#define BWORD 0xf
#define MASKBYTE0 0xff
#define MASKBYTE1 0xff00
#define MASKBYTE2 0xff0000
#define MASKBYTE3 0xff000000
#define MASKHWORD 0xffff0000
#define MASKLWORD 0x0000ffff
#define MASKDWORD 0xffffffff
#define MASK12BITS 0xfff
#define MASKH4BITS 0xf0000000
#define MASKOFDM_D 0xffc00000
#define MASKCCK 0x3f3f3f3f
#define MASK4BITS 0x0f
#define MASK20BITS 0xfffff
#define RFREG_OFFSET_MASK 0xfffff
#define BENABLE 0x1
#define BDISABLE 0x0
@@ -2225,7 +2254,7 @@
#define TCHECK_TXSTATUS 500
#define TUPDATE_RXCOUNTER 100
#define REG_UN_USED_REGISTER 0x01bf
#define REG_UN_used_register 0x01bf
/* WOL bit information */
#define HAL92C_WOL_PTK_UPDATE_EVENT BIT(0)
@@ -2239,5 +2268,4 @@
#define WOL_REASON_DISASSOC BIT(2)
#define WOL_REASON_DEAUTH BIT(3)
#define WOL_REASON_FW_DISCONNECT BIT(4)
#endif

246
drivers/net/wireless/rtlwifi/rtl8188ee/rf.c
View File

@@ -11,10 +11,6 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
@@ -34,6 +30,8 @@
#include "rf.h"
#include "dm.h"
static bool _rtl88e_phy_rf6052_config_parafile(struct ieee80211_hw *hw);
void rtl88e_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
@@ -60,7 +58,7 @@ void rtl88e_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth)
}
void rtl88e_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
u8 *plevel)
u8 *ppowerlevel)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_phy *rtlphy = &(rtlpriv->phy);
@@ -82,32 +80,36 @@ void rtl88e_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
if (turbo_scanoff) {
for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
tx_agc[idx1] = plevel[idx1] |
(plevel[idx1] << 8) |
(plevel[idx1] << 16) |
(plevel[idx1] << 24);
tx_agc[idx1] = ppowerlevel[idx1] |
(ppowerlevel[idx1] << 8) |
(ppowerlevel[idx1] << 16) |
(ppowerlevel[idx1] << 24);
}
}
} else {
for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
tx_agc[idx1] = plevel[idx1] | (plevel[idx1] << 8) |
(plevel[idx1] << 16) |
(plevel[idx1] << 24);
tx_agc[idx1] = ppowerlevel[idx1] |
(ppowerlevel[idx1] << 8) |
(ppowerlevel[idx1] << 16) |
(ppowerlevel[idx1] << 24);
}
if (rtlefuse->eeprom_regulatory == 0) {
tmpval = (rtlphy->mcs_offset[0][6]) +
(rtlphy->mcs_offset[0][7] << 8);
tmpval =
(rtlphy->mcs_txpwrlevel_origoffset[0][6]) +
(rtlphy->mcs_txpwrlevel_origoffset[0][7] <<
8);
tx_agc[RF90_PATH_A] += tmpval;
tmpval = (rtlphy->mcs_offset[0][14]) +
(rtlphy->mcs_offset[0][15] << 24);
tmpval = (rtlphy->mcs_txpwrlevel_origoffset[0][14]) +
(rtlphy->mcs_txpwrlevel_origoffset[0][15] <<
24);
tx_agc[RF90_PATH_B] += tmpval;
}
}
for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
ptr = (u8 *)(&(tx_agc[idx1]));
ptr = (u8 *)(&tx_agc[idx1]);
for (idx2 = 0; idx2 < 4; idx2++) {
if (*ptr > RF6052_MAX_TX_PWR)
*ptr = RF6052_MAX_TX_PWR;
@@ -131,6 +133,8 @@ void rtl88e_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
tmpval = tx_agc[RF90_PATH_A] >> 8;
/*tmpval = tmpval & 0xff00ffff;*/
rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);
RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
@@ -153,21 +157,22 @@ void rtl88e_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
}
static void rtl88e_phy_get_power_base(struct ieee80211_hw *hw,
u8 *pwrlvlofdm, u8 *pwrlvlbw20,
u8 *pwrlvlbw40, u8 channel,
u8 *ppowerlevel_ofdm,
u8 *ppowerlevel_bw20,
u8 *ppowerlevel_bw40, u8 channel,
u32 *ofdmbase, u32 *mcsbase)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_phy *rtlphy = &(rtlpriv->phy);
u32 base0, base1;
u32 powerbase0, powerbase1;
u8 i, powerlevel[2];
for (i = 0; i < 2; i++) {
base0 = pwrlvlofdm[i];
powerbase0 = ppowerlevel_ofdm[i];
base0 = (base0 << 24) | (base0 << 16) |
(base0 << 8) | base0;
*(ofdmbase + i) = base0;
powerbase0 = (powerbase0 << 24) | (powerbase0 << 16) |
(powerbase0 << 8) | powerbase0;
*(ofdmbase + i) = powerbase0;
RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
" [OFDM power base index rf(%c) = 0x%x]\n",
((i == 0) ? 'A' : 'B'), *(ofdmbase + i));
@@ -175,14 +180,15 @@ static void rtl88e_phy_get_power_base(struct ieee80211_hw *hw,
for (i = 0; i < 2; i++) {
if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20)
powerlevel[i] = pwrlvlbw20[i];
powerlevel[i] = ppowerlevel_bw20[i];
else
powerlevel[i] = pwrlvlbw40[i];
base1 = powerlevel[i];
base1 = (base1 << 24) |
(base1 << 16) | (base1 << 8) | base1;
powerlevel[i] = ppowerlevel_bw40[i];
*(mcsbase + i) = base1;
powerbase1 = powerlevel[i];
powerbase1 = (powerbase1 << 24) |
(powerbase1 << 16) | (powerbase1 << 8) | powerbase1;
*(mcsbase + i) = powerbase1;
RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
" [MCS power base index rf(%c) = 0x%x]\n",
@@ -190,110 +196,140 @@ static void rtl88e_phy_get_power_base(struct ieee80211_hw *hw,
}
}
static void get_txpwr_by_reg(struct ieee80211_hw *hw, u8 chan, u8 index,
u32 *base0, u32 *base1, u32 *outval)
static void _rtl88e_get_txpower_writeval_by_regulatory(struct ieee80211_hw *hw,
u8 channel, u8 index,
u32 *powerbase0,
u32 *powerbase1,
u32 *p_outwriteval)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_phy *rtlphy = &(rtlpriv->phy);
struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
u8 i, chg = 0, pwr_lim[4], pwr_diff = 0, cust_pwr_dif;
u32 writeval, cust_lim, rf, tmp;
u8 ch = chan - 1;
u8 j;
u8 i, chnlgroup = 0, pwr_diff_limit[4], pwr_diff = 0, customer_pwr_diff;
u32 writeval, customer_limit, rf;
for (rf = 0; rf < 2; rf++) {
j = index + (rf ? 8 : 0);
tmp = ((index < 2) ? base0[rf] : base1[rf]);
switch (rtlefuse->eeprom_regulatory) {
case 0:
chg = 0;
chnlgroup = 0;
writeval = rtlphy->mcs_offset[chg][j] + tmp;
writeval =
rtlphy->mcs_txpwrlevel_origoffset
[chnlgroup][index + (rf ? 8 : 0)]
+ ((index < 2) ? powerbase0[rf] : powerbase1[rf]);
RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
"RTK better performance, "
"writeval(%c) = 0x%x\n",
"RTK better performance, writeval(%c) = 0x%x\n",
((rf == 0) ? 'A' : 'B'), writeval);
break;
case 1:
if (rtlphy->pwrgroup_cnt == 1) {
chg = 0;
chnlgroup = 0;
} else {
chg = chan / 3;
if (chan == 14)
chg = 5;
if (channel < 3)
chnlgroup = 0;
else if (channel < 6)
chnlgroup = 1;
else if (channel < 9)
chnlgroup = 2;
else if (channel < 12)
chnlgroup = 3;
else if (channel < 14)
chnlgroup = 4;
else if (channel == 14)
chnlgroup = 5;
}
writeval = rtlphy->mcs_offset[chg][j] + tmp;
writeval =
rtlphy->mcs_txpwrlevel_origoffset[chnlgroup]
[index + (rf ? 8 : 0)] + ((index < 2) ?
powerbase0[rf] :
powerbase1[rf]);
RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
"Realtek regulatory, 20MHz, writeval(%c) = 0x%x\n",
((rf == 0) ? 'A' : 'B'), writeval);
break;
case 2:
writeval = ((index < 2) ? base0[rf] : base1[rf]);
writeval =
((index < 2) ? powerbase0[rf] : powerbase1[rf]);
RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
"Better regulatory, writeval(%c) = 0x%x\n",
((rf == 0) ? 'A' : 'B'), writeval);
break;
case 3:
chg = 0;
chnlgroup = 0;
if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
"customer's limit, 40MHz rf(%c) = 0x%x\n",
((rf == 0) ? 'A' : 'B'),
rtlefuse->pwrgroup_ht40[rf][ch]);
rtlefuse->pwrgroup_ht40[rf][channel -
1]);
} else {
RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
"customer's limit, 20MHz rf(%c) = 0x%x\n",
((rf == 0) ? 'A' : 'B'),
rtlefuse->pwrgroup_ht20[rf][ch]);
rtlefuse->pwrgroup_ht20[rf][channel -
1]);
}
if (index < 2)
pwr_diff = rtlefuse->txpwr_legacyhtdiff[rf][ch];
pwr_diff =
rtlefuse->txpwr_legacyhtdiff[rf][channel-1];
else if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20)
pwr_diff = rtlefuse->txpwr_ht20diff[rf][ch];
pwr_diff =
rtlefuse->txpwr_ht20diff[rf][channel-1];
if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40)
cust_pwr_dif = rtlefuse->pwrgroup_ht40[rf][ch];
customer_pwr_diff =
rtlefuse->pwrgroup_ht40[rf][channel-1];
else
cust_pwr_dif = rtlefuse->pwrgroup_ht20[rf][ch];
customer_pwr_diff =
rtlefuse->pwrgroup_ht20[rf][channel-1];
if (pwr_diff > cust_pwr_dif)
if (pwr_diff > customer_pwr_diff)
pwr_diff = 0;
else
pwr_diff = cust_pwr_dif - pwr_diff;
pwr_diff = customer_pwr_diff - pwr_diff;
for (i = 0; i < 4; i++) {
pwr_lim[i] = (u8)((rtlphy->mcs_offset[chg][j] &
(0x7f << (i * 8))) >> (i * 8));
pwr_diff_limit[i] =
(u8)((rtlphy->mcs_txpwrlevel_origoffset
[chnlgroup][index +
(rf ? 8 : 0)] & (0x7f <<
(i * 8))) >> (i * 8));
if (pwr_lim[i] > pwr_diff)
pwr_lim[i] = pwr_diff;
if (pwr_diff_limit[i] > pwr_diff)
pwr_diff_limit[i] = pwr_diff;
}
cust_lim = (pwr_lim[3] << 24) | (pwr_lim[2] << 16) |
(pwr_lim[1] << 8) | (pwr_lim[0]);
customer_limit = (pwr_diff_limit[3] << 24) |
(pwr_diff_limit[2] << 16) |
(pwr_diff_limit[1] << 8) | (pwr_diff_limit[0]);
RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
"Customer's limit rf(%c) = 0x%x\n",
((rf == 0) ? 'A' : 'B'), cust_lim);
((rf == 0) ? 'A' : 'B'), customer_limit);
writeval = cust_lim + tmp;
writeval = customer_limit +
((index < 2) ? powerbase0[rf] : powerbase1[rf]);
RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
"Customer, writeval rf(%c)= 0x%x\n",
((rf == 0) ? 'A' : 'B'), writeval);
break;
default:
chg = 0;
writeval = rtlphy->mcs_offset[chg][j] + tmp;
chnlgroup = 0;
writeval =
rtlphy->mcs_txpwrlevel_origoffset[chnlgroup]
[index + (rf ? 8 : 0)]
+ ((index < 2) ? powerbase0[rf] : powerbase1[rf]);
RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
"RTK better performance, writeval "
"rf(%c) = 0x%x\n",
"RTK better performance, writeval rf(%c) = 0x%x\n",
((rf == 0) ? 'A' : 'B'), writeval);
break;
}
@@ -302,12 +338,13 @@ static void get_txpwr_by_reg(struct ieee80211_hw *hw, u8 chan, u8 index,
writeval = writeval - 0x06060606;
else if (rtlpriv->dm.dynamic_txhighpower_lvl ==
TXHIGHPWRLEVEL_BT2)
writeval -= 0x0c0c0c0c;
*(outval + rf) = writeval;
writeval = writeval - 0x0c0c0c0c;
*(p_outwriteval + rf) = writeval;
}
}
static void write_ofdm_pwr(struct ieee80211_hw *hw, u8 index, u32 *pvalue)
static void _rtl88e_write_ofdm_power_reg(struct ieee80211_hw *hw,
u8 index, u32 *value)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u16 regoffset_a[6] = {
@@ -325,7 +362,7 @@ static void write_ofdm_pwr(struct ieee80211_hw *hw, u8 index, u32 *pvalue)
u16 regoffset;
for (rf = 0; rf < 2; rf++) {
writeval = pvalue[rf];
writeval = value[rf];
for (i = 0; i < 4; i++) {
pwr_val[i] = (u8)((writeval & (0x7f <<
(i * 8))) >> (i * 8));
@@ -348,23 +385,26 @@ static void write_ofdm_pwr(struct ieee80211_hw *hw, u8 index, u32 *pvalue)
}
void rtl88e_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
u8 *pwrlvlofdm,
u8 *pwrlvlbw20,
u8 *pwrlvlbw40, u8 chan)
u8 *ppowerlevel_ofdm,
u8 *ppowerlevel_bw20,
u8 *ppowerlevel_bw40, u8 channel)
{
u32 writeval[2], base0[2], base1[2];
u32 writeval[2], powerbase0[2], powerbase1[2];
u8 index;
u8 direction;
u32 pwrtrac_value;
rtl88e_phy_get_power_base(hw, pwrlvlofdm, pwrlvlbw20,
pwrlvlbw40, chan, &base0[0],
&base1[0]);
rtl88e_phy_get_power_base(hw, ppowerlevel_ofdm,
ppowerlevel_bw20, ppowerlevel_bw40,
channel, &powerbase0[0], &powerbase1[0]);
rtl88e_dm_txpower_track_adjust(hw, 1, &direction, &pwrtrac_value);
for (index = 0; index < 6; index++) {
get_txpwr_by_reg(hw, chan, index, &base0[0], &base1[0],
_rtl88e_get_txpower_writeval_by_regulatory(hw,
channel, index,
&powerbase0[0],
&powerbase1[0],
&writeval[0]);
if (direction == 1) {
writeval[0] += pwrtrac_value;
@@ -373,15 +413,28 @@ void rtl88e_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
writeval[0] -= pwrtrac_value;
writeval[1] -= pwrtrac_value;
}
write_ofdm_pwr(hw, index, &writeval[0]);
_rtl88e_write_ofdm_power_reg(hw, index, &writeval[0]);
}
}
static bool rf6052_conf_para(struct ieee80211_hw *hw)
bool rtl88e_phy_rf6052_config(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_phy *rtlphy = &(rtlpriv->phy);
u32 u4val = 0;
if (rtlphy->rf_type == RF_1T1R)
rtlphy->num_total_rfpath = 1;
else
rtlphy->num_total_rfpath = 2;
return _rtl88e_phy_rf6052_config_parafile(hw);
}
static bool _rtl88e_phy_rf6052_config_parafile(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_phy *rtlphy = &rtlpriv->phy;
u32 u4_regvalue = 0;
u8 rfpath;
bool rtstatus = true;
struct bb_reg_def *pphyreg;
@@ -392,12 +445,12 @@ static bool rf6052_conf_para(struct ieee80211_hw *hw)
switch (rfpath) {
case RF90_PATH_A:
case RF90_PATH_C:
u4val = rtl_get_bbreg(hw, pphyreg->rfintfs,
u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs,
BRFSI_RFENV);
break;
case RF90_PATH_B:
case RF90_PATH_D:
u4val = rtl_get_bbreg(hw, pphyreg->rfintfs,
u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs,
BRFSI_RFENV << 16);
break;
}
@@ -433,12 +486,13 @@ static bool rf6052_conf_para(struct ieee80211_hw *hw)
switch (rfpath) {
case RF90_PATH_A:
case RF90_PATH_C:
rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV, u4val);
rtl_set_bbreg(hw, pphyreg->rfintfs,
BRFSI_RFENV, u4_regvalue);
break;
case RF90_PATH_B:
case RF90_PATH_D:
rtl_set_bbreg(hw, pphyreg->rfintfs, BRFSI_RFENV << 16,
u4val);
rtl_set_bbreg(hw, pphyreg->rfintfs,
BRFSI_RFENV << 16, u4_regvalue);
break;
}
@@ -447,21 +501,9 @@ static bool rf6052_conf_para(struct ieee80211_hw *hw)
"Radio[%d] Fail!!", rfpath);
return false;
}
}
RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "\n");
return rtstatus;
}
bool rtl88e_phy_rf6052_config(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_phy *rtlphy = &(rtlpriv->phy);
if (rtlphy->rf_type == RF_1T1R)
rtlphy->num_total_rfpath = 1;
else
rtlphy->num_total_rfpath = 2;
return rf6052_conf_para(hw);
}

7
drivers/net/wireless/rtlwifi/rtl8188ee/rf.h
View File

@@ -11,10 +11,6 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
@@ -40,7 +36,8 @@ void rtl88e_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
void rtl88e_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
u8 *ppowerlevel_ofdm,
u8 *ppowerlevel_bw20,
u8 *ppowerlevel_bw40, u8 channel);
u8 *ppowerlevel_bw40,
u8 channel);
bool rtl88e_phy_rf6052_config(struct ieee80211_hw *hw);
#endif

37
drivers/net/wireless/rtlwifi/rtl8188ee/sw.c
View File

@@ -11,10 +11,6 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
@@ -30,7 +26,6 @@
#include "../wifi.h"
#include "../core.h"
#include "../pci.h"
#include "../base.h"
#include "reg.h"
#include "def.h"
#include "phy.h"
@@ -143,6 +138,8 @@ int rtl88e_init_sw_vars(struct ieee80211_hw *hw)
rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
if (rtlpriv->cfg->mod_params->disable_watchdog)
pr_info("watchdog disabled\n");
if (!rtlpriv->psc.inactiveps)
pr_info("rtl8188ee: Power Save off (module option)\n");
if (!rtlpriv->psc.fwctrl_lps)
@@ -218,6 +215,12 @@ void rtl88e_deinit_sw_vars(struct ieee80211_hw *hw)
del_timer_sync(&rtlpriv->works.fast_antenna_training_timer);
}
/* get bt coexist status */
bool rtl88e_get_btc_status(void)
{
return false;
}
static struct rtl_hal_ops rtl8188ee_hal_ops = {
.init_sw_vars = rtl88e_init_sw_vars,
.deinit_sw_vars = rtl88e_deinit_sw_vars,
@@ -246,11 +249,12 @@ static struct rtl_hal_ops rtl8188ee_hal_ops = {
.set_bw_mode = rtl88e_phy_set_bw_mode,
.switch_channel = rtl88e_phy_sw_chnl,
.dm_watchdog = rtl88e_dm_watchdog,
.scan_operation_backup = rtl_phy_scan_operation_backup,
.scan_operation_backup = rtl88e_phy_scan_operation_backup,
.set_rf_power_state = rtl88e_phy_set_rf_power_state,
.led_control = rtl88ee_led_control,
.set_desc = rtl88ee_set_desc,
.get_desc = rtl88ee_get_desc,
.is_tx_desc_closed = rtl88ee_is_tx_desc_closed,
.tx_polling = rtl88ee_tx_polling,
.enable_hw_sec = rtl88ee_enable_hw_security_config,
.set_key = rtl88ee_set_key,
@@ -259,14 +263,17 @@ static struct rtl_hal_ops rtl8188ee_hal_ops = {
.set_bbreg = rtl88e_phy_set_bb_reg,
.get_rfreg = rtl88e_phy_query_rf_reg,
.set_rfreg = rtl88e_phy_set_rf_reg,
.get_btc_status = rtl88e_get_btc_status,
.rx_command_packet = rtl88ee_rx_command_packet,
};
static struct rtl_mod_params rtl88ee_mod_params = {
.sw_crypto = false,
.inactiveps = true,
.inactiveps = false,
.swctrl_lps = false,
.fwctrl_lps = true,
.msi_support = false,
.fwctrl_lps = false,
.msi_support = true,
.debug = DBG_EMERG,
};
@@ -274,6 +281,7 @@ static struct rtl_hal_cfg rtl88ee_hal_cfg = {
.bar_id = 2,
.write_readback = true,
.name = "rtl88e_pci",
.fw_name = "rtlwifi/rtl8188efw.bin",
.ops = &rtl8188ee_hal_ops,
.mod_params = &rtl88ee_mod_params,
@@ -285,6 +293,9 @@ static struct rtl_hal_cfg rtl88ee_hal_cfg = {
.maps[MAC_RCR_ACRC32] = ACRC32,
.maps[MAC_RCR_ACF] = ACF,
.maps[MAC_RCR_AAP] = AAP,
.maps[MAC_HIMR] = REG_HIMR,
.maps[MAC_HIMRE] = REG_HIMRE,
.maps[MAC_HSISR] = REG_HSISR,
.maps[EFUSE_ACCESS] = REG_EFUSE_ACCESS,
@@ -345,6 +356,7 @@ static struct rtl_hal_cfg rtl88ee_hal_cfg = {
.maps[RTL_IMR_VIDOK] = IMR_VIDOK,
.maps[RTL_IMR_VODOK] = IMR_VODOK,
.maps[RTL_IMR_ROK] = IMR_ROK,
.maps[RTL_IMR_HSISR_IND] = IMR_HSISR_IND_ON_INT,
.maps[RTL_IBSS_INT_MASKS] = (IMR_BCNDMAINT0 | IMR_TBDOK | IMR_TBDER),
.maps[RTL_RC_CCK_RATE1M] = DESC92C_RATE1M,
@@ -364,7 +376,7 @@ static struct rtl_hal_cfg rtl88ee_hal_cfg = {
.maps[RTL_RC_HT_RATEMCS15] = DESC92C_RATEMCS15,
};
static const struct pci_device_id rtl88ee_pci_ids[] = {
static struct pci_device_id rtl88ee_pci_ids[] = {
{RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8179, rtl88ee_hal_cfg)},
{},
};
@@ -384,12 +396,15 @@ module_param_named(ips, rtl88ee_mod_params.inactiveps, bool, 0444);
module_param_named(swlps, rtl88ee_mod_params.swctrl_lps, bool, 0444);
module_param_named(fwlps, rtl88ee_mod_params.fwctrl_lps, bool, 0444);
module_param_named(msi, rtl88ee_mod_params.msi_support, bool, 0444);
module_param_named(disable_watchdog, rtl88ee_mod_params.disable_watchdog,
bool, 0444);
MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");
MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n");
MODULE_PARM_DESC(msi, "Set to 1 to use MSI interrupts mode (default 0)\n");
MODULE_PARM_DESC(msi, "Set to 1 to use MSI interrupts mode (default 1)\n");
MODULE_PARM_DESC(debug, "Set debug level (0-5) (default 0)");
MODULE_PARM_DESC(disable_watchdog, "Set to 1 to disable the watchdog (default 0)\n");
static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);

6
drivers/net/wireless/rtlwifi/rtl8188ee/sw.h
View File

@@ -11,10 +11,6 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
@@ -32,5 +28,7 @@
int rtl88e_init_sw_vars(struct ieee80211_hw *hw);
void rtl88e_deinit_sw_vars(struct ieee80211_hw *hw);
bool rtl88e_get_btc_status(void);
#endif

6
drivers/net/wireless/rtlwifi/rtl8188ee/table.c
View File

@@ -11,10 +11,6 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
@@ -30,7 +26,6 @@
*****************************************************************************/
#include "table.h"
u32 RTL8188EEPHY_REG_1TARRAY[] = {
0x800, 0x80040000,
0x804, 0x00000003,
@@ -640,4 +635,5 @@ u32 RTL8188EEAGCTAB_1TARRAY[] = {
0xC78, 0x407D0001,
0xC78, 0x407E0001,
0xC78, 0x407F0001,
};

4
drivers/net/wireless/rtlwifi/rtl8188ee/table.h
View File

@@ -11,10 +11,6 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*

376
drivers/net/wireless/rtlwifi/rtl8188ee/trx.c
View File

@@ -11,10 +11,6 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
@@ -37,6 +33,7 @@
#include "trx.h"
#include "led.h"
#include "dm.h"
#include "phy.h"
static u8 _rtl88ee_map_hwqueue_to_fwqueue(struct sk_buff *skb, u8 hw_queue)
{
@@ -50,6 +47,164 @@ static u8 _rtl88ee_map_hwqueue_to_fwqueue(struct sk_buff *skb, u8 hw_queue)
return skb->priority;
}
/* mac80211's rate_idx is like this:
*
* 2.4G band:rx_status->band == IEEE80211_BAND_2GHZ
*
* B/G rate:
* (rx_status->flag & RX_FLAG_HT) = 0,
* DESC92C_RATE1M-->DESC92C_RATE54M ==> idx is 0-->11,
*
* N rate:
* (rx_status->flag & RX_FLAG_HT) = 1,
* DESC92C_RATEMCS0-->DESC92C_RATEMCS15 ==> idx is 0-->15
*
* 5G band:rx_status->band == IEEE80211_BAND_5GHZ
* A rate:
* (rx_status->flag & RX_FLAG_HT) = 0,
* DESC92C_RATE6M-->DESC92C_RATE54M ==> idx is 0-->7,
*
* N rate:
* (rx_status->flag & RX_FLAG_HT) = 1,
* DESC92C_RATEMCS0-->DESC92C_RATEMCS15 ==> idx is 0-->15
*/
static int _rtl88ee_rate_mapping(struct ieee80211_hw *hw,
bool isht, u8 desc_rate)
{
int rate_idx;
if (!isht) {
if (IEEE80211_BAND_2GHZ == hw->conf.chandef.chan->band) {
switch (desc_rate) {
case DESC92C_RATE1M:
rate_idx = 0;
break;
case DESC92C_RATE2M:
rate_idx = 1;
break;
case DESC92C_RATE5_5M:
rate_idx = 2;
break;
case DESC92C_RATE11M:
rate_idx = 3;
break;
case DESC92C_RATE6M:
rate_idx = 4;
break;
case DESC92C_RATE9M:
rate_idx = 5;
break;
case DESC92C_RATE12M:
rate_idx = 6;
break;
case DESC92C_RATE18M:
rate_idx = 7;
break;
case DESC92C_RATE24M:
rate_idx = 8;
break;
case DESC92C_RATE36M:
rate_idx = 9;
break;
case DESC92C_RATE48M:
rate_idx = 10;
break;
case DESC92C_RATE54M:
rate_idx = 11;
break;
default:
rate_idx = 0;
break;
}
} else {
switch (desc_rate) {
case DESC92C_RATE6M:
rate_idx = 0;
break;
case DESC92C_RATE9M:
rate_idx = 1;
break;
case DESC92C_RATE12M:
rate_idx = 2;
break;
case DESC92C_RATE18M:
rate_idx = 3;
break;
case DESC92C_RATE24M:
rate_idx = 4;
break;
case DESC92C_RATE36M:
rate_idx = 5;
break;
case DESC92C_RATE48M:
rate_idx = 6;
break;
case DESC92C_RATE54M:
rate_idx = 7;
break;
default:
rate_idx = 0;
break;
}
}
} else {
switch (desc_rate) {
case DESC92C_RATEMCS0:
rate_idx = 0;
break;
case DESC92C_RATEMCS1:
rate_idx = 1;
break;
case DESC92C_RATEMCS2:
rate_idx = 2;
break;
case DESC92C_RATEMCS3:
rate_idx = 3;
break;
case DESC92C_RATEMCS4:
rate_idx = 4;
break;
case DESC92C_RATEMCS5:
rate_idx = 5;
break;
case DESC92C_RATEMCS6:
rate_idx = 6;
break;
case DESC92C_RATEMCS7:
rate_idx = 7;
break;
case DESC92C_RATEMCS8:
rate_idx = 8;
break;
case DESC92C_RATEMCS9:
rate_idx = 9;
break;
case DESC92C_RATEMCS10:
rate_idx = 10;
break;
case DESC92C_RATEMCS11:
rate_idx = 11;
break;
case DESC92C_RATEMCS12:
rate_idx = 12;
break;
case DESC92C_RATEMCS13:
rate_idx = 13;
break;
case DESC92C_RATEMCS14:
rate_idx = 14;
break;
case DESC92C_RATEMCS15:
rate_idx = 15;
break;
default:
rate_idx = 0;
break;
}
}
return rate_idx;
}
static void _rtl88ee_query_rxphystatus(struct ieee80211_hw *hw,
struct rtl_stats *pstatus, u8 *pdesc,
struct rx_fwinfo_88e *p_drvinfo,
@@ -59,7 +214,8 @@ static void _rtl88ee_query_rxphystatus(struct ieee80211_hw *hw,
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
struct phy_sts_cck_8192s_t *cck_buf;
struct phy_status_rpt *phystrpt = (struct phy_status_rpt *)p_drvinfo;
struct phy_status_rpt *phystrpt =
(struct phy_status_rpt *)p_drvinfo;
struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
char rx_pwr_all = 0, rx_pwr[4];
u8 rf_rx_num = 0, evm, pwdb_all;
@@ -72,11 +228,11 @@ static void _rtl88ee_query_rxphystatus(struct ieee80211_hw *hw,
pstatus->packet_matchbssid = bpacket_match_bssid;
pstatus->packet_toself = bpacket_toself;
pstatus->packet_beacon = packet_beacon;
pstatus->rx_mimo_sig_qual[0] = -1;
pstatus->rx_mimo_sig_qual[1] = -1;
pstatus->rx_mimo_signalquality[0] = -1;
pstatus->rx_mimo_signalquality[1] = -1;
if (is_cck) {
u8 cck_hipwr;
u8 cck_highpwr;
u8 cck_agc_rpt;
/* CCK Driver info Structure is not the same as OFDM packet. */
cck_buf = (struct phy_sts_cck_8192s_t *)p_drvinfo;
@@ -87,34 +243,41 @@ static void _rtl88ee_query_rxphystatus(struct ieee80211_hw *hw,
* hardware (for rate adaptive)
*/
if (ppsc->rfpwr_state == ERFON)
cck_hipwr = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2,
cck_highpwr =
(u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2,
BIT(9));
else
cck_hipwr = false;
cck_highpwr = false;
lan_idx = ((cck_agc_rpt & 0xE0) >> 5);
vga_idx = (cck_agc_rpt & 0x1f);
switch (lan_idx) {
case 7:
if (vga_idx <= 27)
/*VGA_idx = 27~2*/
rx_pwr_all = -100 + 2*(27-vga_idx);
else
rx_pwr_all = -100;
break;
case 6:
rx_pwr_all = -48 + 2 * (2 - vga_idx); /*VGA_idx = 2~0*/
/*VGA_idx = 2~0*/
rx_pwr_all = -48 + 2*(2-vga_idx);
break;
case 5:
rx_pwr_all = -42 + 2 * (7 - vga_idx); /*VGA_idx = 7~5*/
/*VGA_idx = 7~5*/
rx_pwr_all = -42 + 2*(7-vga_idx);
break;
case 4:
rx_pwr_all = -36 + 2 * (7 - vga_idx); /*VGA_idx = 7~4*/
/*VGA_idx = 7~4*/
rx_pwr_all = -36 + 2*(7-vga_idx);
break;
case 3:
rx_pwr_all = -24 + 2 * (7 - vga_idx); /*VGA_idx = 7~0*/
/*VGA_idx = 7~0*/
rx_pwr_all = -24 + 2*(7-vga_idx);
break;
case 2:
if (cck_hipwr)
if (cck_highpwr)
/*VGA_idx = 5~0*/
rx_pwr_all = -12 + 2*(5-vga_idx);
else
rx_pwr_all = -6 + 2*(5-vga_idx);
@@ -130,10 +293,8 @@ static void _rtl88ee_query_rxphystatus(struct ieee80211_hw *hw,
}
rx_pwr_all += 6;
pwdb_all = rtl_query_rxpwrpercentage(rx_pwr_all);
/* CCK gain is smaller than OFDM/MCS gain,
* so we add gain diff by experiences,
* the val is 6
*/
/* CCK gain is smaller than OFDM/MCS gain, */
/* so we add gain diff by experiences, the val is 6 */
pwdb_all += 6;
if (pwdb_all > 100)
pwdb_all = 100;
@@ -148,7 +309,7 @@ static void _rtl88ee_query_rxphystatus(struct ieee80211_hw *hw,
pwdb_all -= 8;
else if (pwdb_all > 4 && pwdb_all <= 14)
pwdb_all -= 4;
if (cck_hipwr == false) {
if (!cck_highpwr) {
if (pwdb_all >= 80)
pwdb_all = ((pwdb_all-80)<<1) +
((pwdb_all-80)>>1) + 80;
@@ -165,9 +326,9 @@ static void _rtl88ee_query_rxphystatus(struct ieee80211_hw *hw,
if (bpacket_match_bssid) {
u8 sq;
if (pstatus->rx_pwdb_all > 40) {
if (pstatus->rx_pwdb_all > 40)
sq = 100;
} else {
else {
sq = cck_buf->sq_rpt;
if (sq > 64)
sq = 0;
@@ -178,8 +339,8 @@ static void _rtl88ee_query_rxphystatus(struct ieee80211_hw *hw,
}
pstatus->signalquality = sq;
pstatus->rx_mimo_sig_qual[0] = sq;
pstatus->rx_mimo_sig_qual[1] = -1;
pstatus->rx_mimo_signalquality[0] = sq;
pstatus->rx_mimo_signalquality[1] = -1;
}
} else {
rtlpriv->dm.rfpath_rxenable[0] =
@@ -191,14 +352,16 @@ static void _rtl88ee_query_rxphystatus(struct ieee80211_hw *hw,
if (rtlpriv->dm.rfpath_rxenable[i])
rf_rx_num++;
rx_pwr[i] = ((p_drvinfo->gain_trsw[i] & 0x3f) * 2)-110;
rx_pwr[i] = ((p_drvinfo->gain_trsw[i] &
0x3f) * 2) - 110;
/* Translate DBM to percentage. */
rssi = rtl_query_rxpwrpercentage(rx_pwr[i]);
total_rssi += rssi;
/* Get Rx snr value in DB */
rtlpriv->stats.rx_snr_db[i] = p_drvinfo->rxsnr[i] / 2;
rtlpriv->stats.rx_snr_db[i] =
(long)(p_drvinfo->rxsnr[i] / 2);
/* Record Signal Strength for next packet */
if (bpacket_match_bssid)
@@ -227,11 +390,13 @@ static void _rtl88ee_query_rxphystatus(struct ieee80211_hw *hw,
if (bpacket_match_bssid) {
/* Fill value in RFD, Get the first
* spatial stream only
* spatial stream onlyi
*/
if (i == 0)
pstatus->signalquality = evm & 0xff;
pstatus->rx_mimo_sig_qual[i] = evm & 0xff;
pstatus->signalquality =
(u8)(evm & 0xff);
pstatus->rx_mimo_signalquality[i] =
(u8)(evm & 0xff);
}
}
}
@@ -256,34 +421,39 @@ static void _rtl88ee_smart_antenna(struct ieee80211_hw *hw,
{
struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
u8 ant_mux;
struct fast_ant_training *pfat = &(rtldm->fat_table);
u8 antsel_tr_mux;
struct fast_ant_training *pfat_table = &rtldm->fat_table;
if (rtlefuse->antenna_div_type == CG_TRX_SMART_ANTDIV) {
if (pfat->fat_state == FAT_TRAINING_STATE) {
if (pfat_table->fat_state == FAT_TRAINING_STATE) {
if (pstatus->packet_toself) {
ant_mux = (pfat->antsel_rx_keep_2 << 2) |
(pfat->antsel_rx_keep_1 << 1) |
pfat->antsel_rx_keep_0;
pfat->ant_sum[ant_mux] += pstatus->rx_pwdb_all;
pfat->ant_cnt[ant_mux]++;
antsel_tr_mux =
(pfat_table->antsel_rx_keep_2 << 2) |
(pfat_table->antsel_rx_keep_1 << 1) |
pfat_table->antsel_rx_keep_0;
pfat_table->ant_sum[antsel_tr_mux] +=
pstatus->rx_pwdb_all;
pfat_table->ant_cnt[antsel_tr_mux]++;
}
}
} else if ((rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV) ||
(rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV)) {
if (pstatus->packet_toself || pstatus->packet_matchbssid) {
ant_mux = (pfat->antsel_rx_keep_2 << 2) |
(pfat->antsel_rx_keep_1 << 1) |
pfat->antsel_rx_keep_0;
rtl88e_dm_ant_sel_statistics(hw, ant_mux, 0,
antsel_tr_mux = (pfat_table->antsel_rx_keep_2 << 2) |
(pfat_table->antsel_rx_keep_1 << 1) |
pfat_table->antsel_rx_keep_0;
rtl88e_dm_ant_sel_statistics(hw, antsel_tr_mux, 0,
pstatus->rx_pwdb_all);
}
}
}
static void _rtl88ee_translate_rx_signal_stuff(struct ieee80211_hw *hw,
struct sk_buff *skb, struct rtl_stats *pstatus,
u8 *pdesc, struct rx_fwinfo_88e *p_drvinfo)
struct sk_buff *skb,
struct rtl_stats *pstatus,
u8 *pdesc,
struct rx_fwinfo_88e *p_drvinfo)
{
struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
@@ -292,42 +462,42 @@ static void _rtl88ee_translate_rx_signal_stuff(struct ieee80211_hw *hw,
u8 *praddr;
u8 *psaddr;
__le16 fc;
u16 type, ufc;
bool match_bssid, packet_toself, packet_beacon = false, addr;
bool packet_matchbssid, packet_toself, packet_beacon;
tmp_buf = skb->data + pstatus->rx_drvinfo_size + pstatus->rx_bufshift;
hdr = (struct ieee80211_hdr *)tmp_buf;
fc = hdr->frame_control;
ufc = le16_to_cpu(fc);
type = WLAN_FC_GET_TYPE(fc);
praddr = hdr->addr1;
psaddr = ieee80211_get_SA(hdr);
memcpy(pstatus->psaddr, psaddr, ETH_ALEN);
addr = ether_addr_equal(mac->bssid,
(ufc & IEEE80211_FCTL_TODS) ? hdr->addr1 :
(ufc & IEEE80211_FCTL_FROMDS) ? hdr->addr2 :
hdr->addr3);
match_bssid = ((IEEE80211_FTYPE_CTL != type) && (!pstatus->hwerror) &&
(!pstatus->crc) && (!pstatus->icv)) && addr;
packet_matchbssid = ((!ieee80211_is_ctl(fc)) &&
(ether_addr_equal(mac->bssid, ieee80211_has_tods(fc) ?
hdr->addr1 : ieee80211_has_fromds(fc) ?
hdr->addr2 : hdr->addr3)) &&
(!pstatus->hwerror) &&
(!pstatus->crc) && (!pstatus->icv));
addr = ether_addr_equal(praddr, rtlefuse->dev_addr);
packet_toself = match_bssid && addr;
packet_toself = packet_matchbssid &&
(ether_addr_equal(praddr, rtlefuse->dev_addr));
if (ieee80211_is_beacon(fc))
if (ieee80211_is_beacon(hdr->frame_control))
packet_beacon = true;
else
packet_beacon = false;
_rtl88ee_query_rxphystatus(hw, pstatus, pdesc, p_drvinfo,
match_bssid, packet_toself, packet_beacon);
packet_matchbssid, packet_toself,
packet_beacon);
_rtl88ee_smart_antenna(hw, pstatus);
rtl_process_phyinfo(hw, tmp_buf, pstatus);
}
static void insert_em(struct rtl_tcb_desc *ptcb_desc, u8 *virtualaddress)
static void _rtl88ee_insert_emcontent(struct rtl_tcb_desc *ptcb_desc,
u8 *virtualaddress)
{
u32 dwtmp = 0;
memset(virtualaddress, 0, 8);
SET_EARLYMODE_PKTNUM(virtualaddress, ptcb_desc->empkt_num);
@@ -420,11 +590,14 @@ bool rtl88ee_rx_query_desc(struct ieee80211_hw *hw,
status->wake_match = 0;
if (status->wake_match)
RT_TRACE(rtlpriv, COMP_RXDESC, DBG_LOUD,
"Get Wakeup Packet!! WakeMatch =%d\n",
"GGGGGGGGGGGGGet Wakeup Packet!! WakeMatch=%d\n",
status->wake_match);
rx_status->freq = hw->conf.chandef.chan->center_freq;
rx_status->band = hw->conf.chandef.chan->band;
hdr = (struct ieee80211_hdr *)(skb->data + status->rx_drvinfo_size
+ status->rx_bufshift);
if (status->crc)
rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
@@ -445,18 +618,18 @@ bool rtl88ee_rx_query_desc(struct ieee80211_hw *hw,
* to decrypt it
*/
if (status->decrypted) {
hdr = (struct ieee80211_hdr *)(skb->data +
status->rx_drvinfo_size + status->rx_bufshift);
if (!hdr) {
/* During testing, hdr was NULL */
WARN_ON_ONCE(true);
pr_err("decrypted is true but hdr NULL, from skb %p\n",
rtl_get_hdr(skb));
return false;
}
if ((_ieee80211_is_robust_mgmt_frame(hdr)) &&
if ((!_ieee80211_is_robust_mgmt_frame(hdr)) &&
(ieee80211_has_protected(hdr->frame_control)))
rx_status->flag &= ~RX_FLAG_DECRYPTED;
else
rx_status->flag |= RX_FLAG_DECRYPTED;
else
rx_status->flag &= ~RX_FLAG_DECRYPTED;
}
/* rate_idx: index of data rate into band's
@@ -464,19 +637,18 @@ bool rtl88ee_rx_query_desc(struct ieee80211_hw *hw,
* are use (RX_FLAG_HT)
* Notice: this is diff with windows define
*/
rx_status->rate_idx = rtlwifi_rate_mapping(hw, status->is_ht,
status->rate, false);
rx_status->rate_idx = _rtl88ee_rate_mapping(hw,
status->is_ht, status->rate);
rx_status->mactime = status->timestamp_low;
if (phystatus == true) {
p_drvinfo = (struct rx_fwinfo_88e *)(skb->data +
status->rx_bufshift);
_rtl88ee_translate_rx_signal_stuff(hw, skb, status, pdesc,
_rtl88ee_translate_rx_signal_stuff(hw,
skb, status, pdesc,
p_drvinfo);
}
/*rx_status->qual = status->signal; */
rx_status->signal = status->recvsignalpower + 10;
if (status->packet_report_type == TX_REPORT2) {
status->macid_valid_entry[0] =
@@ -489,15 +661,17 @@ bool rtl88ee_rx_query_desc(struct ieee80211_hw *hw,
void rtl88ee_tx_fill_desc(struct ieee80211_hw *hw,
struct ieee80211_hdr *hdr, u8 *pdesc_tx,
u8 *pbd_desc_tx, struct ieee80211_tx_info *info,
struct ieee80211_sta *sta, struct sk_buff *skb,
u8 *txbd, struct ieee80211_tx_info *info,
struct ieee80211_sta *sta,
struct sk_buff *skb,
u8 hw_queue, struct rtl_tcb_desc *ptcb_desc)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
u8 *pdesc = pdesc_tx;
u8 *pdesc = (u8 *)pdesc_tx;
u16 seq_number;
__le16 fc = hdr->frame_control;
unsigned int buf_len = 0;
@@ -548,7 +722,8 @@ void rtl88ee_tx_fill_desc(struct ieee80211_hw *hw,
RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
"Insert 8 byte.pTcb->EMPktNum:%d\n",
ptcb_desc->empkt_num);
insert_em(ptcb_desc, (u8 *)(skb->data));
_rtl88ee_insert_emcontent(ptcb_desc,
(u8 *)(skb->data));
}
} else {
SET_TX_DESC_OFFSET(pdesc, USB_HWDESC_HEADER_LEN);
@@ -560,6 +735,7 @@ void rtl88ee_tx_fill_desc(struct ieee80211_hw *hw,
short_gi = (ptcb_desc->use_shortgi) ? 1 : 0;
else
short_gi = (ptcb_desc->use_shortpreamble) ? 1 : 0;
SET_TX_DESC_DATA_SHORTGI(pdesc, short_gi);
if (info->flags & IEEE80211_TX_CTL_AMPDU) {
@@ -581,11 +757,11 @@ void rtl88ee_tx_fill_desc(struct ieee80211_hw *hw,
(ptcb_desc->rts_use_shortpreamble ? 1 : 0) :
(ptcb_desc->rts_use_shortgi ? 1 : 0)));
if (ptcb_desc->btx_enable_sw_calc_duration)
if (ptcb_desc->tx_enable_sw_calc_duration)
SET_TX_DESC_NAV_USE_HDR(pdesc, 1);
if (bw_40) {
if (ptcb_desc->packet_bw) {
if (ptcb_desc->packet_bw == HT_CHANNEL_WIDTH_20_40) {
SET_TX_DESC_DATA_BW(pdesc, 1);
SET_TX_DESC_TX_SUB_CARRIER(pdesc, 3);
} else {
@@ -606,6 +782,7 @@ void rtl88ee_tx_fill_desc(struct ieee80211_hw *hw,
}
if (info->control.hw_key) {
struct ieee80211_key_conf *keyconf;
keyconf = info->control.hw_key;
switch (keyconf->cipher) {
case WLAN_CIPHER_SUITE_WEP40:
@@ -619,6 +796,7 @@ void rtl88ee_tx_fill_desc(struct ieee80211_hw *hw,
default:
SET_TX_DESC_SEC_TYPE(pdesc, 0x0);
break;
}
}
@@ -629,6 +807,7 @@ void rtl88ee_tx_fill_desc(struct ieee80211_hw *hw,
1 : 0);
SET_TX_DESC_USE_RATE(pdesc, ptcb_desc->use_driver_rate ? 1 : 0);
/*SET_TX_DESC_PWR_STATUS(pdesc, pwr_status);*/
/* Set TxRate and RTSRate in TxDesc */
/* This prevent Tx initial rate of new-coming packets */
/* from being overwritten by retried packet rate.*/
@@ -664,8 +843,9 @@ void rtl88ee_tx_fill_desc(struct ieee80211_hw *hw,
SET_TX_DESC_HWSEQ_EN(pdesc, 1);
SET_TX_DESC_MORE_FRAG(pdesc, (lastseg ? 0 : 1));
if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
is_broadcast_ether_addr(ieee80211_get_DA(hdr)))
is_broadcast_ether_addr(ieee80211_get_DA(hdr))) {
SET_TX_DESC_BMC(pdesc, 1);
}
rtl88e_dm_set_tx_ant_by_tx_info(hw, pdesc, ptcb_desc->mac_id);
RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE, "\n");
@@ -733,8 +913,8 @@ void rtl88ee_tx_fill_cmddesc(struct ieee80211_hw *hw,
pdesc, TX_DESC_SIZE);
}
void rtl88ee_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
u8 desc_name, u8 *val)
void rtl88ee_set_desc(struct ieee80211_hw *hw, u8 *pdesc,
bool istx, u8 desc_name, u8 *val)
{
if (istx == true) {
switch (desc_name) {
@@ -745,7 +925,7 @@ void rtl88ee_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
SET_TX_DESC_NEXT_DESC_ADDRESS(pdesc, *(u32 *)val);
break;
default:
RT_ASSERT(false, "ERR txdesc :%d not processed\n",
RT_ASSERT(false, "ERR txdesc :%d not process\n",
desc_name);
break;
}
@@ -764,7 +944,7 @@ void rtl88ee_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
SET_RX_DESC_EOR(pdesc, 1);
break;
default:
RT_ASSERT(false, "ERR rxdesc :%d not processed\n",
RT_ASSERT(false, "ERR rxdesc :%d not process\n",
desc_name);
break;
}
@@ -784,7 +964,7 @@ u32 rtl88ee_get_desc(u8 *pdesc, bool istx, u8 desc_name)
ret = GET_TX_DESC_TX_BUFFER_ADDRESS(pdesc);
break;
default:
RT_ASSERT(false, "ERR txdesc :%d not processed\n",
RT_ASSERT(false, "ERR txdesc :%d not process\n",
desc_name);
break;
}
@@ -796,8 +976,11 @@ u32 rtl88ee_get_desc(u8 *pdesc, bool istx, u8 desc_name)
case HW_DESC_RXPKT_LEN:
ret = GET_RX_DESC_PKT_LEN(pdesc);
break;
case HW_DESC_RXBUFF_ADDR:
ret = GET_RX_DESC_BUFF_ADDR(pdesc);
break;
default:
RT_ASSERT(false, "ERR rxdesc :%d not processed\n",
RT_ASSERT(false, "ERR rxdesc :%d not process\n",
desc_name);
break;
}
@@ -805,6 +988,22 @@ u32 rtl88ee_get_desc(u8 *pdesc, bool istx, u8 desc_name)
return ret;
}
bool rtl88ee_is_tx_desc_closed(struct ieee80211_hw *hw, u8 hw_queue, u16 index)
{
struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
u8 *entry = (u8 *)(&ring->desc[ring->idx]);
u8 own = (u8)rtl88ee_get_desc(entry, true, HW_DESC_OWN);
/*beacon packet will only use the first
*descriptor defautly,and the own may not
*be cleared by the hardware
*/
if (own)
return false;
return true;
}
void rtl88ee_tx_polling(struct ieee80211_hw *hw, u8 hw_queue)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
@@ -815,3 +1014,10 @@ void rtl88ee_tx_polling(struct ieee80211_hw *hw, u8 hw_queue)
BIT(0) << (hw_queue));
}
}
u32 rtl88ee_rx_command_packet(struct ieee80211_hw *hw,
struct rtl_stats status,
struct sk_buff *skb)
{
return 0;
}

31
drivers/net/wireless/rtlwifi/rtl8188ee/trx.h
View File

@@ -11,10 +11,6 @@
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
@@ -205,7 +201,6 @@
#define SET_TX_DESC_HWSEQ_EN(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+12, 31, 1, __val)
#define GET_TX_DESC_NEXT_HEAP_PAGE(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+12, 0, 8)
#define GET_TX_DESC_TAIL_PAGE(__pdesc) \
@@ -213,7 +208,6 @@
#define GET_TX_DESC_SEQ(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+12, 16, 12)
#define SET_TX_DESC_RTS_RATE(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+16, 0, 5, __val)
#define SET_TX_DESC_AP_DCFE(__pdesc, __val) \
@@ -386,7 +380,6 @@
#define GET_TX_DESC_TX_BUFFER_SIZE(__pdesc) \
LE_BITS_TO_4BYTE(__pdesc+28, 0, 16)
#define SET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc, __val) \
SET_BITS_TO_LE_4BYTE(__pdesc+32, 0, 32, __val)
#define SET_TX_DESC_TX_BUFFER_ADDRESS64(__pdesc, __val) \
@@ -549,8 +542,10 @@ do { \
rxmcs == DESC92C_RATE5_5M ||\
rxmcs == DESC92C_RATE11M)
#define IS_LITTLE_ENDIAN 1
struct phy_rx_agc_info_t {
#ifdef __LITTLE_ENDIAN
#if IS_LITTLE_ENDIAN
u8 gain:7, trsw:1;
#else
u8 trsw:1, gain:7;
@@ -562,7 +557,7 @@ struct phy_status_rpt {
u8 cck_sig_qual_ofdm_pwdb_all;
u8 cck_agc_rpt_ofdm_cfosho_a;
u8 cck_rpt_b_ofdm_cfosho_b;
u8 rsvd_1;
u8 rsvd_1;/* ch_corr_msb; */
u8 noise_power_db_msb;
u8 path_cfotail[2];
u8 pcts_mask[2];
@@ -574,7 +569,7 @@ struct phy_status_rpt {
u8 stream_target_csi[2];
u8 sig_evm;
u8 rsvd_3;
#ifdef __LITTLE_ENDIAN
#if IS_LITTLE_ENDIAN
u8 antsel_rx_keep_2:1; /*ex_intf_flg:1;*/
u8 sgi_en:1;
u8 rxsc:2;
@@ -777,19 +772,25 @@ struct rx_desc_88e {
void rtl88ee_tx_fill_desc(struct ieee80211_hw *hw,
struct ieee80211_hdr *hdr, u8 *pdesc_tx,
u8 *pbd_desc_tx, struct ieee80211_tx_info *info,
struct ieee80211_sta *sta, struct sk_buff *skb,
u8 *txbd, struct ieee80211_tx_info *info,
struct ieee80211_sta *sta,
struct sk_buff *skb,
u8 hw_queue, struct rtl_tcb_desc *ptcb_desc);
bool rtl88ee_rx_query_desc(struct ieee80211_hw *hw,
struct rtl_stats *status,
struct ieee80211_rx_status *rx_status,
u8 *pdesc, struct sk_buff *skb);
void rtl88ee_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
u8 desc_name, u8 *val);
void rtl88ee_set_desc(struct ieee80211_hw *hw, u8 *pdesc,
bool istx, u8 desc_name, u8 *val);
u32 rtl88ee_get_desc(u8 *pdesc, bool istx, u8 desc_name);
bool rtl88ee_is_tx_desc_closed(struct ieee80211_hw *hw,
u8 hw_queue, u16 index);
void rtl88ee_tx_polling(struct ieee80211_hw *hw, u8 hw_queue);
void rtl88ee_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc,
bool b_firstseg, bool b_lastseg,
bool firstseg, bool lastseg,
struct sk_buff *skb);
u32 rtl88ee_rx_command_packet(struct ieee80211_hw *hw,
struct rtl_stats status,
struct sk_buff *skb);
#endif

2
drivers/net/wireless/rtlwifi/rtl8723be/trx.c
View File

@@ -732,7 +732,7 @@ void rtl8723be_tx_fill_desc(struct ieee80211_hw *hw,
(ptcb_desc->rts_use_shortpreamble ? 1 : 0) :
(ptcb_desc->rts_use_shortgi ? 1 : 0)));
if (ptcb_desc->btx_enable_sw_calc_duration)
if (ptcb_desc->tx_enable_sw_calc_duration)
SET_TX_DESC_NAV_USE_HDR(pdesc, 1);
if (bw_40) {

5
drivers/net/wireless/rtlwifi/wifi.h
View File

@@ -1160,6 +1160,8 @@ struct rtl_phy {
u8 pwrgroup_cnt;
u8 cck_high_power;
/* this is for 88E & 8723A */
u32 mcs_txpwrlevel_origoffset[MAX_PG_GROUP][16];
/* MAX_PG_GROUP groups of pwr diff by rates */
u32 mcs_offset[MAX_PG_GROUP][16];
u32 tx_power_by_rate_offset[TX_PWR_BY_RATE_NUM_BAND]
@@ -1890,6 +1892,7 @@ struct rtl_stats {
bool rx_is40Mhzpacket;
u32 rx_pwdb_all;
u8 rx_mimo_signalstrength[4]; /*in 0~100 index */
s8 rx_mimo_signalquality[4];
u8 rx_mimo_evm_dbm[4];
u16 cfo_short[4]; /* per-path's Cfo_short */
u16 cfo_tail[4];
@@ -1966,7 +1969,7 @@ struct rtl_tcb_desc {
u8 empkt_num;
/* The max value by HW */
u32 empkt_len[10];
bool btx_enable_sw_calc_duration;
bool tx_enable_sw_calc_duration;
};
struct rtl92c_firmware_header;