usb: dwc2: gadget: Set TX FIFO depths to calculated defaults
Remove legacy DWC2_G_P_LEGACY_TX_FIFO_SIZE array for TX FIFOs. Update dwc2_set_param_tx_fifo_sizes function to calculate and assign default average FIFO depth to each member of g_tx_fifo_size array. Total FIFO size, EP Info block's size, FIFO operation mode and device operation mode are taken into consideration during the calculation. Cc: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Sevak Arakelyan <sevaka@synopsys.com> Signed-off-by: John Youn <johnyoun@synopsys.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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committed by
Felipe Balbi

szülő
e1f411d1b3
commit
c138ecfa61
@@ -191,6 +191,99 @@ static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg,
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local_irq_restore(flags);
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}
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/**
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* dwc2_hsotg_tx_fifo_count - return count of TX FIFOs in device mode
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*/
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int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg)
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{
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if (hsotg->hw_params.en_multiple_tx_fifo)
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/* In dedicated FIFO mode we need count of IN EPs */
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return (dwc2_readl(hsotg->regs + GHWCFG4) &
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GHWCFG4_NUM_IN_EPS_MASK) >> GHWCFG4_NUM_IN_EPS_SHIFT;
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else
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/* In shared FIFO mode we need count of Periodic IN EPs */
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return hsotg->hw_params.num_dev_perio_in_ep;
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}
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/**
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* dwc2_hsotg_ep_info_size - return Endpoint Info Control block size in DWORDs
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*/
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static int dwc2_hsotg_ep_info_size(struct dwc2_hsotg *hsotg)
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{
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int val = 0;
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int i;
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u32 ep_dirs;
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/*
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* Don't need additional space for ep info control registers in
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* slave mode.
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*/
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if (!using_dma(hsotg)) {
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dev_dbg(hsotg->dev, "Buffer DMA ep info size 0\n");
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return 0;
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}
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/*
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* Buffer DMA mode - 1 location per endpoit
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* Descriptor DMA mode - 4 locations per endpoint
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*/
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ep_dirs = hsotg->hw_params.dev_ep_dirs;
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for (i = 0; i <= hsotg->hw_params.num_dev_ep; i++) {
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val += ep_dirs & 3 ? 1 : 2;
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ep_dirs >>= 2;
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}
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if (using_desc_dma(hsotg))
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val = val * 4;
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return val;
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}
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/**
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* dwc2_hsotg_tx_fifo_total_depth - return total FIFO depth available for
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* device mode TX FIFOs
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*/
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int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg)
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{
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int ep_info_size;
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int addr;
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int tx_addr_max;
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u32 np_tx_fifo_size;
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np_tx_fifo_size = min_t(u32, hsotg->hw_params.dev_nperio_tx_fifo_size,
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hsotg->params.g_np_tx_fifo_size);
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/* Get Endpoint Info Control block size in DWORDs. */
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ep_info_size = dwc2_hsotg_ep_info_size(hsotg);
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tx_addr_max = hsotg->hw_params.total_fifo_size - ep_info_size;
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addr = hsotg->params.g_rx_fifo_size + np_tx_fifo_size;
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if (tx_addr_max <= addr)
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return 0;
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return tx_addr_max - addr;
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}
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/**
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* dwc2_hsotg_tx_fifo_average_depth - returns average depth of device mode
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* TX FIFOs
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*/
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int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg)
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{
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int tx_fifo_count;
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int tx_fifo_depth;
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tx_fifo_depth = dwc2_hsotg_tx_fifo_total_depth(hsotg);
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tx_fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
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if (!tx_fifo_count)
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return tx_fifo_depth;
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else
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return tx_fifo_depth / tx_fifo_count;
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}
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/**
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* dwc2_hsotg_init_fifo - initialise non-periodic FIFOs
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* @hsotg: The device instance.
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