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dma: shdma: fix runtime PM: clear channel buffers on reset

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On platforms, supporting power domains, if the domain, containing a DMAC
instance is powered down, the driver fails to resume correctly. On those
platforms DMAC channels have an additional CHCLR register for clearing
channel buffers. Using this register during runtime resume fixes the
problem.

Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
This commit is contained in:
Guennadi Liakhovetski
2012-01-04 15:34:17 +01:00
committed by Vinod Koul
parent f69f2e264f
commit c11b46c32c
2 changed files with 33 additions and 16 deletions
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2
include/linux/sh_dma.h
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@@ -48,6 +48,7 @@ struct sh_dmae_channel {
unsigned int offset;
unsigned int dmars;
unsigned int dmars_bit;
unsigned int chclr_offset;
};
struct sh_dmae_pdata {
@@ -68,6 +69,7 @@ struct sh_dmae_pdata {
unsigned int dmaor_is_32bit:1;
unsigned int needs_tend_set:1;
unsigned int no_dmars:1;
unsigned int chclr_present:1;
};
/* DMA register */