Merge branches 'pci/enumeration', 'pci/virtualization' and 'pci/cleanup' into next
* pci/enumeration: PCI: Generate uppercase hex for modalias interface class * pci/virtualization: PCI: Add ACS quirk for Solarflare SFC9120 & SFC9140 PCI: Remove unused pci_get_dma_source() PCI: Remove unused pci_find_upstream_pcie_bridge() * pci/cleanup: PCI: Remove assignment from complicated "if" conditions PCI: Remove assignment from "if" conditions PCI: Remove unnecessary curly braces PCI: Add space before open parenthesis
此提交包含在:
@@ -3534,57 +3534,6 @@ DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias);
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/* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */
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DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias);
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static struct pci_dev *pci_func_0_dma_source(struct pci_dev *dev)
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{
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if (!PCI_FUNC(dev->devfn))
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return pci_dev_get(dev);
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return pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
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}
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static const struct pci_dev_dma_source {
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u16 vendor;
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u16 device;
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struct pci_dev *(*dma_source)(struct pci_dev *dev);
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} pci_dev_dma_source[] = {
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/*
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* https://bugzilla.redhat.com/show_bug.cgi?id=605888
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*
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* Some Ricoh devices use the function 0 source ID for DMA on
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* other functions of a multifunction device. The DMA devices
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* is therefore function 0, which will have implications of the
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* iommu grouping of these devices.
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*/
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{ PCI_VENDOR_ID_RICOH, 0xe822, pci_func_0_dma_source },
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{ PCI_VENDOR_ID_RICOH, 0xe230, pci_func_0_dma_source },
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{ PCI_VENDOR_ID_RICOH, 0xe832, pci_func_0_dma_source },
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{ PCI_VENDOR_ID_RICOH, 0xe476, pci_func_0_dma_source },
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{ 0 }
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};
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/*
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* IOMMUs with isolation capabilities need to be programmed with the
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* correct source ID of a device. In most cases, the source ID matches
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* the device doing the DMA, but sometimes hardware is broken and will
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* tag the DMA as being sourced from a different device. This function
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* allows that translation. Note that the reference count of the
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* returned device is incremented on all paths.
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*/
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struct pci_dev *pci_get_dma_source(struct pci_dev *dev)
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{
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const struct pci_dev_dma_source *i;
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for (i = pci_dev_dma_source; i->dma_source; i++) {
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if ((i->vendor == dev->vendor ||
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i->vendor == (u16)PCI_ANY_ID) &&
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(i->device == dev->device ||
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i->device == (u16)PCI_ANY_ID))
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return i->dma_source(dev);
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}
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return pci_dev_get(dev);
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}
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/*
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* AMD has indicated that the devices below do not support peer-to-peer
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* in any system where they are found in the southbridge with an AMD
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@@ -3686,6 +3635,21 @@ static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags)
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return acs_flags & ~flags ? 0 : 1;
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}
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static int pci_quirk_solarflare_acs(struct pci_dev *dev, u16 acs_flags)
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{
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/*
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* SV, TB, and UF are not relevant to multifunction endpoints.
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*
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* Solarflare indicates that peer-to-peer between functions is not
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* possible, therefore RR, CR, and DT are not implemented. Mask
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* these out as if they were clear in the ACS capabilities register.
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*/
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acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
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PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
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return acs_flags ? 0 : 1;
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}
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static const struct pci_dev_acs_enabled {
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u16 vendor;
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u16 device;
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@@ -3697,6 +3661,8 @@ static const struct pci_dev_acs_enabled {
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{ PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
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{ PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
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{ PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
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{ PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_solarflare_acs },
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{ PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_solarflare_acs },
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{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
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{ 0 }
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};
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