[POWERPC] 85xx: Add next-level-cache property

Added next-level-cache to the L1 and a reference to the new L2 label.
This is per the ePAPR 0.94 spec.  Since we are't really dependent on this
today we aren't supporting the "legacy" l2-cache phandle that is specified
in the PPC v2.1 OF Binding spec.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

arch/powerpc/boot/dts/mpc8548cds.dts

@@ -45,6 +45,7 @@
 			timebase-frequency = <0>;	//  33 MHz, from uboot
 			bus-frequency = <0>;	// 166 MHz
 			clock-frequency = <0>;	// 825 MHz, from uboot
+			next-level-cache = <&L2>;
 		};
 	};
 
@@ -68,7 +69,7 @@
 			interrupts = <18 2>;
 		};
 
-		l2-cache-controller@20000 {
+		L2: l2-cache-controller@20000 {
 			compatible = "fsl,8548-l2-cache-controller";
 			reg = <0x20000 0x1000>;
 			cache-line-size = <32>;	// 32 bytes