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ARM: SAMSUNG: Consolidate plat/pwm-clock.h

Browse Source 
Removed
 - arch/arm/plat-s3c24xx/include/mach/pwm-clock.h
 - arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
 - arch/arm/mach-s5p64x0/include/mach/pwm-clock.h
 - arch/arm/mach-s5pc100/include/mach/pwm-clock.h
 - arch/arm/mach-s5pv210/include/mach/pwm-clock.h
 - arch/arm/mach-exynos4/include/mach/pwm-clock.h

And created
 - arch/arm/plat-samsung/include/plat/pwm-clock.h

Cc: Ben Dooks <ben-linux@fluff.org>
[kgene.kim@samsung.com: changed title]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Kukjin Kim
2011-09-20 08:44:38 +09:00
parent 4b2656fe49
commit c0468b0244
7 changed files with 36 additions and 321 deletions
Download Patch File Download Diff File Expand all files Collapse all files

56
arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
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@@ -1,56 +0,0 @@
/* linux/arch/arm/mach-s3c6400/include/mach/pwm-clock.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C64xx - pwm clock and timer support
*/
/**
* pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
* @tcfg: The timer TCFG1 register bits shifted down to 0.
*
* Return true if the given configuration from TCFG1 is a TCLK instead
* any of the TDIV clocks.
*/
static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
{
return tcfg >= S3C64XX_TCFG1_MUX_TCLK;
}
/**
* tcfg_to_divisor() - convert tcfg1 setting to a divisor
* @tcfg1: The tcfg1 setting, shifted down.
*
* Get the divisor value for the given tcfg1 setting. We assume the
* caller has already checked to see if this is not a TCLK source.
*/
static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
{
return 1 << tcfg1;
}
/**
* pwm_tdiv_has_div1() - does the tdiv setting have a /1
*
* Return true if we have a /1 in the tdiv setting.
*/
static inline unsigned int pwm_tdiv_has_div1(void)
{
return 1;
}
/**
* pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
* @div: The divisor to calculate the bit information for.
*
* Turn a divisor into the necessary bit field for TCFG1.
*/
static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
{
return ilog2(div);
}
#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK

68
arch/arm/mach-s5p64x0/include/mach/pwm-clock.h
View File

@@ -1,68 +0,0 @@
/* linux/arch/arm/mach-s5p64x0/include/mach/pwm-clock.h
*
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S5P64X0 - pwm clock and timer support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_PWMCLK_H
#define __ASM_ARCH_PWMCLK_H __FILE__
/**
* pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
* @tcfg: The timer TCFG1 register bits shifted down to 0.
*
* Return true if the given configuration from TCFG1 is a TCLK instead
* any of the TDIV clocks.
*/
static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
{
return 0;
}
/**
* tcfg_to_divisor() - convert tcfg1 setting to a divisor
* @tcfg1: The tcfg1 setting, shifted down.
*
* Get the divisor value for the given tcfg1 setting. We assume the
* caller has already checked to see if this is not a TCLK source.
*/
static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
{
return 1 << tcfg1;
}
/**
* pwm_tdiv_has_div1() - does the tdiv setting have a /1
*
* Return true if we have a /1 in the tdiv setting.
*/
static inline unsigned int pwm_tdiv_has_div1(void)
{
return 1;
}
/**
* pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
* @div: The divisor to calculate the bit information for.
*
* Turn a divisor into the necessary bit field for TCFG1.
*/
static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
{
return ilog2(div);
}
#define S3C_TCFG1_MUX_TCLK 0
#endif /* __ASM_ARCH_PWMCLK_H */

56
arch/arm/mach-s5pc100/include/mach/pwm-clock.h
View File

@@ -1,56 +0,0 @@
/* linux/arch/arm/mach-s5pc100/include/mach/pwm-clock.h
*
* Copyright 2009 Samsung Electronics Co.
* Byungho Min <bhmin@samsung.com>
*
* S5PC100 - pwm clock and timer support
*
* Based on mach-s3c6400/include/mach/pwm-clock.h
*/
/**
* pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
* @tcfg: The timer TCFG1 register bits shifted down to 0.
*
* Return true if the given configuration from TCFG1 is a TCLK instead
* any of the TDIV clocks.
*/
static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
{
return tcfg >= S3C64XX_TCFG1_MUX_TCLK;
}
/**
* tcfg_to_divisor() - convert tcfg1 setting to a divisor
* @tcfg1: The tcfg1 setting, shifted down.
*
* Get the divisor value for the given tcfg1 setting. We assume the
* caller has already checked to see if this is not a TCLK source.
*/
static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
{
return 1 << tcfg1;
}
/**
* pwm_tdiv_has_div1() - does the tdiv setting have a /1
*
* Return true if we have a /1 in the tdiv setting.
*/
static inline unsigned int pwm_tdiv_has_div1(void)
{
return 1;
}
/**
* pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
* @div: The divisor to calculate the bit information for.
*
* Turn a divisor into the necessary bit field for TCFG1.
*/
static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
{
return ilog2(div);
}
#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK

70
arch/arm/mach-s5pv210/include/mach/pwm-clock.h
View File

@@ -1,70 +0,0 @@
/* linux/arch/arm/mach-s5pv210/include/mach/pwm-clock.h
*
* Copyright (c) 2009 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
*
* S5PV210 - pwm clock and timer support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_PWMCLK_H
#define __ASM_ARCH_PWMCLK_H __FILE__
/**
* pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
* @tcfg: The timer TCFG1 register bits shifted down to 0.
*
* Return true if the given configuration from TCFG1 is a TCLK instead
* any of the TDIV clocks.
*/
static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
{
return tcfg == S3C64XX_TCFG1_MUX_TCLK;
}
/**
* tcfg_to_divisor() - convert tcfg1 setting to a divisor
* @tcfg1: The tcfg1 setting, shifted down.
*
* Get the divisor value for the given tcfg1 setting. We assume the
* caller has already checked to see if this is not a TCLK source.
*/
static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
{
return 1 << tcfg1;
}
/**
* pwm_tdiv_has_div1() - does the tdiv setting have a /1
*
* Return true if we have a /1 in the tdiv setting.
*/
static inline unsigned int pwm_tdiv_has_div1(void)
{
return 1;
}
/**
* pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
* @div: The divisor to calculate the bit information for.
*
* Turn a divisor into the necessary bit field for TCFG1.
*/
static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
{
return ilog2(div);
}
#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK
#endif /* __ASM_ARCH_PWMCLK_H */

55
arch/arm/plat-s3c24xx/include/mach/pwm-clock.h
View File

@@ -1,55 +0,0 @@
/* linux/arch/arm/plat-s3c24xx/include/mach/pwm-clock.h
*
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/
*
* S3C24xx - pwm clock and timer support
*/
/**
* pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
* @cfg: The timer TCFG1 register bits shifted down to 0.
*
* Return true if the given configuration from TCFG1 is a TCLK instead
* any of the TDIV clocks.
*/
static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
{
return tcfg == S3C2410_TCFG1_MUX_TCLK;
}
/**
* tcfg_to_divisor() - convert tcfg1 setting to a divisor
* @tcfg1: The tcfg1 setting, shifted down.
*
* Get the divisor value for the given tcfg1 setting. We assume the
* caller has already checked to see if this is not a TCLK source.
*/
static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
{
return 1 << (1 + tcfg1);
}
/**
* pwm_tdiv_has_div1() - does the tdiv setting have a /1
*
* Return true if we have a /1 in the tdiv setting.
*/
static inline unsigned int pwm_tdiv_has_div1(void)
{
return 0;
}
/**
* pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
* @div: The divisor to calculate the bit information for.
*
* Turn a divisor into the necessary bit field for TCFG1.
*/
static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
{
return ilog2(div) - 1;
}
#define S3C_TCFG1_MUX_TCLK S3C2410_TCFG1_MUX_TCLK

31
arch/arm/mach-exynos4/include/mach/pwm-clock.h → arch/arm/plat-samsung/include/plat/pwm-clock.h
View File

@@ -1,4 +1,4 @@
/* linux/arch/arm/mach-exynos4/include/mach/pwm-clock.h /* linux/arch/arm/plat-samsung/include/plat/pwm-clock.h
* *
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com * http://www.samsung.com
@@ -8,17 +8,15 @@
* Ben Dooks <ben@simtec.co.uk> * Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/ * http://armlinux.simtec.co.uk/
* *
* Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h * SAMSUNG - pwm clock and timer support
*
* EXYNOS4 - pwm clock and timer support
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as * it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation. * published by the Free Software Foundation.
*/ */
#ifndef __ASM_ARCH_PWMCLK_H #ifndef __ASM_PLAT_PWM_CLOCK_H
#define __ASM_ARCH_PWMCLK_H __FILE__ #define __ASM_PLAT_PWM_CLOCK_H __FILE__
/** /**
* pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
@@ -29,6 +27,13 @@
*/ */
static inline int pwm_cfg_src_is_tclk(unsigned long tcfg) static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
{ {
if (soc_is_s3c24xx())
return tcfg == S3C2410_TCFG1_MUX_TCLK;
else if (soc_is_s3c64xx() || soc_is_s5pc100())
return tcfg >= S3C64XX_TCFG1_MUX_TCLK;
else if (soc_is_s5p6440() || soc_is_s5p6450())
return 0;
else
return tcfg == S3C64XX_TCFG1_MUX_TCLK; return tcfg == S3C64XX_TCFG1_MUX_TCLK;
} }
@@ -41,6 +46,9 @@ static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
*/ */
static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
{ {
if (soc_is_s3c24xx())
return 1 << (tcfg1 + 1);
else
return 1 << tcfg1; return 1 << tcfg1;
} }
@@ -51,6 +59,9 @@ static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
*/ */
static inline unsigned int pwm_tdiv_has_div1(void) static inline unsigned int pwm_tdiv_has_div1(void)
{ {
if (soc_is_s3c24xx())
return 0;
else
return 1; return 1;
} }
@@ -62,9 +73,9 @@ static inline unsigned int pwm_tdiv_has_div1(void)
*/ */
static inline unsigned long pwm_tdiv_div_bits(unsigned int div) static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
{ {
if (soc_is_s3c24xx())
return ilog2(div) - 1;
else
return ilog2(div); return ilog2(div);
} }
#endif /* __ASM_PLAT_PWM_CLOCK_H */
#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK
#endif /* __ASM_ARCH_PWMCLK_H */

13
arch/arm/plat-samsung/pwm-clock.c
View File

@@ -27,7 +27,7 @@
#include <plat/cpu.h> #include <plat/cpu.h>
#include <plat/regs-timer.h> #include <plat/regs-timer.h>
#include <mach/pwm-clock.h> #include <plat/pwm-clock.h>
/* Each of the timers 0 through 5 go through the following /* Each of the timers 0 through 5 go through the following
* clock tree, with the inputs depending on the timers. * clock tree, with the inputs depending on the timers.
@@ -339,8 +339,17 @@ static int clk_pwm_tin_set_parent(struct clk *clk, struct clk *parent)
unsigned long bits; unsigned long bits;
unsigned long shift = S3C2410_TCFG1_SHIFT(id); unsigned long shift = S3C2410_TCFG1_SHIFT(id);
unsigned long mux_tclk;
if (soc_is_s3c24xx())
mux_tclk = S3C2410_TCFG1_MUX_TCLK;
else if (soc_is_s5p6440() || soc_is_s5p6450())
mux_tclk = 0;
else
mux_tclk = S3C64XX_TCFG1_MUX_TCLK;
if (parent == s3c24xx_pwmclk_tclk(id)) if (parent == s3c24xx_pwmclk_tclk(id))
bits = S3C_TCFG1_MUX_TCLK << shift; bits = mux_tclk << shift;
else if (parent == s3c24xx_pwmclk_tdiv(id)) else if (parent == s3c24xx_pwmclk_tdiv(id))
bits = clk_pwm_tdiv_bits(to_tdiv(parent)) << shift; bits = clk_pwm_tdiv_bits(to_tdiv(parent)) << shift;
else else