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scsi: ufs: add support for UFS HCI 2.1

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The UFS HCI v2.1 includes a few additional registers. This change
updates the HCI register, the UFS version register content and the
Interrupt Status register.

Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org>
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Yaniv Gardi
2016-12-05 19:25:02 -08:00
committed by Martin K. Petersen
parent 70439e9334
commit c01848c67d
2 changed files with 32 additions and 4 deletions
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29
drivers/scsi/ufs/ufshcd.c
View File

@@ -288,10 +288,24 @@ int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
*/ */
static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba) static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
{ {
if (hba->ufs_version == UFSHCI_VERSION_10) u32 intr_mask = 0;
return INTERRUPT_MASK_ALL_VER_10;
else switch (hba->ufs_version) {
return INTERRUPT_MASK_ALL_VER_11; case UFSHCI_VERSION_10:
intr_mask = INTERRUPT_MASK_ALL_VER_10;
break;
/* allow fall through */
case UFSHCI_VERSION_11:
case UFSHCI_VERSION_20:
intr_mask = INTERRUPT_MASK_ALL_VER_11;
break;
/* allow fall through */
case UFSHCI_VERSION_21:
default:
intr_mask = INTERRUPT_MASK_ALL_VER_21;
}
return intr_mask;
} }
/** /**
@@ -6667,6 +6681,13 @@ int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq)
/* Get UFS version supported by the controller */ /* Get UFS version supported by the controller */
hba->ufs_version = ufshcd_get_ufs_version(hba); hba->ufs_version = ufshcd_get_ufs_version(hba);
if ((hba->ufs_version != UFSHCI_VERSION_10) &&
(hba->ufs_version != UFSHCI_VERSION_11) &&
(hba->ufs_version != UFSHCI_VERSION_20) &&
(hba->ufs_version != UFSHCI_VERSION_21))
dev_err(hba->dev, "invalid UFS version 0x%x\n",
hba->ufs_version);
/* Get Interrupt bit mask per version */ /* Get Interrupt bit mask per version */
hba->intr_mask = ufshcd_get_intr_mask(hba); hba->intr_mask = ufshcd_get_intr_mask(hba);

7
drivers/scsi/ufs/ufshci.h
View File

@@ -72,6 +72,10 @@ enum {
REG_UIC_COMMAND_ARG_1 = 0x94, REG_UIC_COMMAND_ARG_1 = 0x94,
REG_UIC_COMMAND_ARG_2 = 0x98, REG_UIC_COMMAND_ARG_2 = 0x98,
REG_UIC_COMMAND_ARG_3 = 0x9C, REG_UIC_COMMAND_ARG_3 = 0x9C,
REG_UFS_CCAP = 0x100,
REG_UFS_CRYPTOCAP = 0x104,
UFSHCI_CRYPTO_REG_SPACE_SIZE = 0x400,
}; };
/* Controller capability masks */ /* Controller capability masks */
@@ -275,6 +279,9 @@ enum {
/* Interrupt disable mask for UFSHCI v1.1 */ /* Interrupt disable mask for UFSHCI v1.1 */
INTERRUPT_MASK_ALL_VER_11 = 0x31FFF, INTERRUPT_MASK_ALL_VER_11 = 0x31FFF,
/* Interrupt disable mask for UFSHCI v2.1 */
INTERRUPT_MASK_ALL_VER_21 = 0x71FFF,
}; };
/* /*