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clk: mediatek: correct the clocks for MT2701 HDMI PHY module

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The hdmitx_dig_cts clock signal is not a child of clk26m,
and the actual output of the PLL block is derived from
the tvdpll via a configurable PLL post-divider.

It is used as the PLL reference input to the HDMI PHY module.

Fixes: e986211827 ("clk: mediatek: Add MT2701 clock support")
Signed-off-by: Chunhui Dai <chunhui.dai@mediatek.com>
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Ryder Lee
2018-04-17 20:30:27 +08:00
committed by Stephen Boyd
parent 60cc43fc88
commit bf61099a21
2 changed files with 14 additions and 10 deletions
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16
include/dt-bindings/clock/mt2701-clk.h
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@@ -171,13 +171,12 @@
#define CLK_TOP_8BDAC 151
#define CLK_TOP_WBG_DIG_416M 152
#define CLK_TOP_DPI 153
#define CLK_TOP_HDMITX_CLKDIG_CTS 154
#define CLK_TOP_DSI0_LNTC_DSI 155
#define CLK_TOP_AUD_EXT1 156
#define CLK_TOP_AUD_EXT2 157
#define CLK_TOP_NFI1X_PAD 158
#define CLK_TOP_AXISEL_D4 159
#define CLK_TOP_NR 160
#define CLK_TOP_DSI0_LNTC_DSI 154
#define CLK_TOP_AUD_EXT1 155
#define CLK_TOP_AUD_EXT2 156
#define CLK_TOP_NFI1X_PAD 157
#define CLK_TOP_AXISEL_D4 158
#define CLK_TOP_NR 159
/* APMIXEDSYS */
@@ -194,7 +193,8 @@
#define CLK_APMIXED_HADDS2PLL 11
#define CLK_APMIXED_AUD2PLL 12
#define CLK_APMIXED_TVD2PLL 13
#define CLK_APMIXED_NR 14
#define CLK_APMIXED_HDMI_REF 14
#define CLK_APMIXED_NR 15
/* DDRPHY */