Merge tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linux
Pull clock framework changes from Michael Turquette: "The common clk framework changes for 3.12 are dominated by clock driver patches, both new drivers and fixes to existing. A high percentage of these are for Samsung platforms like Exynos. Core framework fixes and some new features like automagical clock re-parenting round out the patches" * tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linux: (102 commits) clk: only call get_parent if there is one clk: samsung: exynos5250: Simplify registration of PLL rate tables clk: samsung: exynos4: Register PLL rate tables for Exynos4x12 clk: samsung: exynos4: Register PLL rate tables for Exynos4210 clk: samsung: exynos4: Reorder registration of mout_vpllsrc clk: samsung: pll: Add support for rate configuration of PLL46xx clk: samsung: pll: Use new registration method for PLL46xx clk: samsung: pll: Add support for rate configuration of PLL45xx clk: samsung: pll: Use new registration method for PLL45xx clk: samsung: exynos4: Rename exynos4_plls to exynos4x12_plls clk: samsung: exynos4: Remove checks for DT node clk: samsung: exynos4: Remove unused static clkdev aliases clk: samsung: Modify _get_rate() helper to use __clk_lookup() clk: samsung: exynos4: Use separate aliases for cpufreq related clocks clocksource: samsung_pwm_timer: Get clock from device tree ARM: dts: exynos4: Specify PWM clocks in PWM node pwm: samsung: Update DT bindings documentation to cover clocks clk: Move symbol export to proper location clk: fix new_parent dereference before null check clk: wm831x: Initialise wm831x pointer on init ...
This commit is contained in:
Linus Torvalds
@@ -125,8 +125,9 @@ static void __init zynq_clk_register_fclk(enum zynq_clk fclk,
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div0_name = kasprintf(GFP_KERNEL, "%s_div0", clk_name);
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div1_name = kasprintf(GFP_KERNEL, "%s_div1", clk_name);
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clk = clk_register_mux(NULL, mux_name, parents, 4, 0,
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fclk_ctrl_reg, 4, 2, 0, fclk_lock);
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clk = clk_register_mux(NULL, mux_name, parents, 4,
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CLK_SET_RATE_NO_REPARENT, fclk_ctrl_reg, 4, 2, 0,
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fclk_lock);
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clk = clk_register_divider(NULL, div0_name, mux_name,
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0, fclk_ctrl_reg, 8, 6, CLK_DIVIDER_ONE_BASED |
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@@ -168,8 +169,8 @@ static void __init zynq_clk_register_periph_clk(enum zynq_clk clk0,
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mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name0);
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div_name = kasprintf(GFP_KERNEL, "%s_div", clk_name0);
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clk = clk_register_mux(NULL, mux_name, parents, 4, 0,
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clk_ctrl, 4, 2, 0, lock);
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clk = clk_register_mux(NULL, mux_name, parents, 4,
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CLK_SET_RATE_NO_REPARENT, clk_ctrl, 4, 2, 0, lock);
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clk = clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6,
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CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, lock);
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@@ -236,25 +237,26 @@ static void __init zynq_clk_setup(struct device_node *np)
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clk = clk_register_zynq_pll("armpll_int", "ps_clk", SLCR_ARMPLL_CTRL,
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SLCR_PLL_STATUS, 0, &armpll_lock);
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clks[armpll] = clk_register_mux(NULL, clk_output_name[armpll],
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armpll_parents, 2, 0, SLCR_ARMPLL_CTRL, 4, 1, 0,
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&armpll_lock);
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armpll_parents, 2, CLK_SET_RATE_NO_REPARENT,
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SLCR_ARMPLL_CTRL, 4, 1, 0, &armpll_lock);
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clk = clk_register_zynq_pll("ddrpll_int", "ps_clk", SLCR_DDRPLL_CTRL,
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SLCR_PLL_STATUS, 1, &ddrpll_lock);
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clks[ddrpll] = clk_register_mux(NULL, clk_output_name[ddrpll],
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ddrpll_parents, 2, 0, SLCR_DDRPLL_CTRL, 4, 1, 0,
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&ddrpll_lock);
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ddrpll_parents, 2, CLK_SET_RATE_NO_REPARENT,
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SLCR_DDRPLL_CTRL, 4, 1, 0, &ddrpll_lock);
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clk = clk_register_zynq_pll("iopll_int", "ps_clk", SLCR_IOPLL_CTRL,
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SLCR_PLL_STATUS, 2, &iopll_lock);
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clks[iopll] = clk_register_mux(NULL, clk_output_name[iopll],
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iopll_parents, 2, 0, SLCR_IOPLL_CTRL, 4, 1, 0,
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&iopll_lock);
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iopll_parents, 2, CLK_SET_RATE_NO_REPARENT,
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SLCR_IOPLL_CTRL, 4, 1, 0, &iopll_lock);
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/* CPU clocks */
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tmp = readl(SLCR_621_TRUE) & 1;
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clk = clk_register_mux(NULL, "cpu_mux", cpu_parents, 4, 0,
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SLCR_ARM_CLK_CTRL, 4, 2, 0, &armclk_lock);
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clk = clk_register_mux(NULL, "cpu_mux", cpu_parents, 4,
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CLK_SET_RATE_NO_REPARENT, SLCR_ARM_CLK_CTRL, 4, 2, 0,
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&armclk_lock);
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clk = clk_register_divider(NULL, "cpu_div", "cpu_mux", 0,
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SLCR_ARM_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
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CLK_DIVIDER_ALLOW_ZERO, &armclk_lock);
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@@ -293,8 +295,9 @@ static void __init zynq_clk_setup(struct device_node *np)
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swdt_ext_clk_mux_parents[i + 1] = dummy_nm;
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}
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clks[swdt] = clk_register_mux(NULL, clk_output_name[swdt],
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swdt_ext_clk_mux_parents, 2, CLK_SET_RATE_PARENT,
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SLCR_SWDT_CLK_SEL, 0, 1, 0, &swdtclk_lock);
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swdt_ext_clk_mux_parents, 2, CLK_SET_RATE_PARENT |
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CLK_SET_RATE_NO_REPARENT, SLCR_SWDT_CLK_SEL, 0, 1, 0,
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&swdtclk_lock);
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/* DDR clocks */
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clk = clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0,
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@@ -356,8 +359,9 @@ static void __init zynq_clk_setup(struct device_node *np)
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gem0_mux_parents[i + 1] = of_clk_get_parent_name(np,
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idx);
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}
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clk = clk_register_mux(NULL, "gem0_mux", periph_parents, 4, 0,
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SLCR_GEM0_CLK_CTRL, 4, 2, 0, &gem0clk_lock);
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clk = clk_register_mux(NULL, "gem0_mux", periph_parents, 4,
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CLK_SET_RATE_NO_REPARENT, SLCR_GEM0_CLK_CTRL, 4, 2, 0,
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&gem0clk_lock);
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clk = clk_register_divider(NULL, "gem0_div0", "gem0_mux", 0,
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SLCR_GEM0_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
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CLK_DIVIDER_ALLOW_ZERO, &gem0clk_lock);
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@@ -366,7 +370,8 @@ static void __init zynq_clk_setup(struct device_node *np)
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CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
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&gem0clk_lock);
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clk = clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2,
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CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 6, 1, 0,
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CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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SLCR_GEM0_CLK_CTRL, 6, 1, 0,
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&gem0clk_lock);
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clks[gem0] = clk_register_gate(NULL, clk_output_name[gem0],
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"gem0_emio_mux", CLK_SET_RATE_PARENT,
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@@ -379,8 +384,9 @@ static void __init zynq_clk_setup(struct device_node *np)
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gem1_mux_parents[i + 1] = of_clk_get_parent_name(np,
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idx);
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}
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clk = clk_register_mux(NULL, "gem1_mux", periph_parents, 4, 0,
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SLCR_GEM1_CLK_CTRL, 4, 2, 0, &gem1clk_lock);
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clk = clk_register_mux(NULL, "gem1_mux", periph_parents, 4,
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CLK_SET_RATE_NO_REPARENT, SLCR_GEM1_CLK_CTRL, 4, 2, 0,
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&gem1clk_lock);
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clk = clk_register_divider(NULL, "gem1_div0", "gem1_mux", 0,
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SLCR_GEM1_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
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CLK_DIVIDER_ALLOW_ZERO, &gem1clk_lock);
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@@ -389,7 +395,8 @@ static void __init zynq_clk_setup(struct device_node *np)
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CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
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&gem1clk_lock);
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clk = clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2,
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CLK_SET_RATE_PARENT, SLCR_GEM1_CLK_CTRL, 6, 1, 0,
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CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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SLCR_GEM1_CLK_CTRL, 6, 1, 0,
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&gem1clk_lock);
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clks[gem1] = clk_register_gate(NULL, clk_output_name[gem1],
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"gem1_emio_mux", CLK_SET_RATE_PARENT,
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@@ -409,8 +416,9 @@ static void __init zynq_clk_setup(struct device_node *np)
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can_mio_mux_parents[i] = dummy_nm;
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}
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kfree(clk_name);
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clk = clk_register_mux(NULL, "can_mux", periph_parents, 4, 0,
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SLCR_CAN_CLK_CTRL, 4, 2, 0, &canclk_lock);
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clk = clk_register_mux(NULL, "can_mux", periph_parents, 4,
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CLK_SET_RATE_NO_REPARENT, SLCR_CAN_CLK_CTRL, 4, 2, 0,
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&canclk_lock);
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clk = clk_register_divider(NULL, "can_div0", "can_mux", 0,
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SLCR_CAN_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
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CLK_DIVIDER_ALLOW_ZERO, &canclk_lock);
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@@ -425,17 +433,21 @@ static void __init zynq_clk_setup(struct device_node *np)
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CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 1, 0,
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&canclk_lock);
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clk = clk_register_mux(NULL, "can0_mio_mux",
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can_mio_mux_parents, 54, CLK_SET_RATE_PARENT,
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SLCR_CAN_MIOCLK_CTRL, 0, 6, 0, &canmioclk_lock);
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can_mio_mux_parents, 54, CLK_SET_RATE_PARENT |
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CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 0, 6, 0,
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&canmioclk_lock);
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clk = clk_register_mux(NULL, "can1_mio_mux",
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can_mio_mux_parents, 54, CLK_SET_RATE_PARENT,
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SLCR_CAN_MIOCLK_CTRL, 16, 6, 0, &canmioclk_lock);
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can_mio_mux_parents, 54, CLK_SET_RATE_PARENT |
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CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 16, 6,
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0, &canmioclk_lock);
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clks[can0] = clk_register_mux(NULL, clk_output_name[can0],
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can0_mio_mux2_parents, 2, CLK_SET_RATE_PARENT,
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SLCR_CAN_MIOCLK_CTRL, 6, 1, 0, &canmioclk_lock);
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can0_mio_mux2_parents, 2, CLK_SET_RATE_PARENT |
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CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 6, 1, 0,
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&canmioclk_lock);
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clks[can1] = clk_register_mux(NULL, clk_output_name[can1],
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can1_mio_mux2_parents, 2, CLK_SET_RATE_PARENT,
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SLCR_CAN_MIOCLK_CTRL, 22, 1, 0, &canmioclk_lock);
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can1_mio_mux2_parents, 2, CLK_SET_RATE_PARENT |
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CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 22, 1,
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0, &canmioclk_lock);
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for (i = 0; i < ARRAY_SIZE(dbgtrc_emio_input_names); i++) {
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int idx = of_property_match_string(np, "clock-names",
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@@ -444,13 +456,15 @@ static void __init zynq_clk_setup(struct device_node *np)
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dbg_emio_mux_parents[i + 1] = of_clk_get_parent_name(np,
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idx);
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}
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clk = clk_register_mux(NULL, "dbg_mux", periph_parents, 4, 0,
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SLCR_DBG_CLK_CTRL, 4, 2, 0, &dbgclk_lock);
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clk = clk_register_mux(NULL, "dbg_mux", periph_parents, 4,
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CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 4, 2, 0,
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&dbgclk_lock);
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clk = clk_register_divider(NULL, "dbg_div", "dbg_mux", 0,
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SLCR_DBG_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
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CLK_DIVIDER_ALLOW_ZERO, &dbgclk_lock);
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clk = clk_register_mux(NULL, "dbg_emio_mux", dbg_emio_mux_parents, 2, 0,
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SLCR_DBG_CLK_CTRL, 6, 1, 0, &dbgclk_lock);
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clk = clk_register_mux(NULL, "dbg_emio_mux", dbg_emio_mux_parents, 2,
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CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 6, 1, 0,
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&dbgclk_lock);
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clks[dbg_trc] = clk_register_gate(NULL, clk_output_name[dbg_trc],
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"dbg_emio_mux", CLK_SET_RATE_PARENT, SLCR_DBG_CLK_CTRL,
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0, 0, &dbgclk_lock);
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@@ -50,6 +50,9 @@ struct zynq_pll {
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#define PLLCTRL_RESET_MASK 1
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#define PLLCTRL_RESET_SHIFT 0
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#define PLL_FBDIV_MIN 13
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#define PLL_FBDIV_MAX 66
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/**
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* zynq_pll_round_rate() - Round a clock frequency
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* @hw: Handle between common and hardware-specific interfaces
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@@ -63,10 +66,10 @@ static long zynq_pll_round_rate(struct clk_hw *hw, unsigned long rate,
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u32 fbdiv;
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fbdiv = DIV_ROUND_CLOSEST(rate, *prate);
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if (fbdiv < 13)
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fbdiv = 13;
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else if (fbdiv > 66)
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fbdiv = 66;
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if (fbdiv < PLL_FBDIV_MIN)
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fbdiv = PLL_FBDIV_MIN;
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else if (fbdiv > PLL_FBDIV_MAX)
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fbdiv = PLL_FBDIV_MAX;
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return *prate * fbdiv;
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}
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@@ -182,7 +185,13 @@ static const struct clk_ops zynq_pll_ops = {
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/**
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* clk_register_zynq_pll() - Register PLL with the clock framework
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* @np Pointer to the DT device node
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* @name PLL name
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* @parent Parent clock name
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* @pll_ctrl Pointer to PLL control register
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* @pll_status Pointer to PLL status register
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* @lock_index Bit index to this PLL's lock status bit in @pll_status
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* @lock Register lock
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* Returns handle to the registered clock.
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*/
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struct clk *clk_register_zynq_pll(const char *name, const char *parent,
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void __iomem *pll_ctrl, void __iomem *pll_status, u8 lock_index,
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