Merge tag 'drm-next-2019-07-16' of git://anongit.freedesktop.org/drm/drm
Pull drm updates from Dave Airlie: "The biggest thing in this is the AMD Navi GPU support, this again contains a bunch of header files that are large. These are the new AMD RX5700 GPUs that just recently became available. New drivers: - ST-Ericsson MCDE driver - Ingenic JZ47xx SoC UAPI change: - HDR source metadata property Core: - HDR inforframes and EDID parsing - drm hdmi infoframe unpacking - remove prime sg_table caching into dma-buf - New gem vram helpers to reduce driver code - Lots of drmP.h removal - reservation fencing fix - documentation updates - drm_fb_helper_connector removed - mode name command handler rewrite fbcon: - Remove the fbcon notifiers ttm: - forward progress fixes dma-buf: - make mmap call optional - debugfs refcount fixes - dma-fence free with pending signals fix - each dma-buf gets an inode Panels: - Lots of additional panel bindings amdgpu: - initial navi10 support - avoid hw reset - HDR metadata support - new thermal sensors for vega asics - RAS fixes - use HMM rather than MMU notifier - xgmi topology via kfd - SR-IOV fixes - driver reload fixes - DC use a core bpc attribute - Aux fixes for DC - Bandwidth calc updates for DC - Clock handling refactor - kfd VEGAM support vmwgfx: - Coherent memory support changes i915: - HDR Support - HDMI i2c link - Icelake multi-segmented gamma support - GuC firmware update - Mule Creek Canyon PCH support for EHL - EHL platform updtes - move i915.alpha_support to i915.force_probe - runtime PM refactoring - VBT parsing refactoring - DSI fixes - struct mutex dependency reduction - GEM code reorg mali-dp: - Komeda driver features msm: - dsi vs EPROBE_DEFER fixes - msm8998 snapdragon 835 support - a540 gpu support - mdp5 and dpu interconnect support exynos: - drmP.h removal tegra: - misc fixes tda998x: - audio support improvements - pixel repeated mode support - quantisation range handling corrections - HDMI vendor info fix armada: - interlace support fix - overlay/video plane register handling refactor - add gamma support rockchip: - RX3328 support panfrost: - expose perf counters via hidden ioctls vkms: - enumerate CRC sources list ast: - rework BO handling mgag200: - rework BO handling dw-hdmi: - suspend/resume support rcar-du: - R8A774A1 Soc Support - LVDS dual-link mode support - Additional formats - Misc fixes omapdrm: - DSI command mode display support stm - fb modifier support - runtime PM support sun4i: - use vmap ops vc4: - binner bo binding rework v3d: - compute shader support - resync/sync fixes - job management refactoring lima: - NULL pointer in irq handler fix - scheduler default timeout virtio: - fence seqno support - trace events bochs: - misc fixes tc458767: - IRQ/HDP handling sii902x: - HDMI audio support atmel-hlcdc: - misc fixes meson: - zpos support" * tag 'drm-next-2019-07-16' of git://anongit.freedesktop.org/drm/drm: (1815 commits) Revert "Merge branch 'vmwgfx-next' of git://people.freedesktop.org/~thomash/linux into drm-next" Revert "mm: adjust apply_to_pfn_range interface for dropped token." mm: adjust apply_to_pfn_range interface for dropped token. drm/amdgpu/navi10: add uclk activity sensor drm/amdgpu: properly guard the generic discovery code drm/amdgpu: add missing documentation on new module parameters drm/amdgpu: don't invalidate caches in RELEASE_MEM, only do the writeback drm/amd/display: avoid 64-bit division drm/amdgpu/psp11: simplify the ucode register logic drm/amdgpu: properly guard DC support in navi code drm/amd/powerplay: vega20: fix uninitialized variable use drm/amd/display: dcn20: include linux/delay.h amdgpu: make pmu support optional drm/amd/powerplay: Zero initialize current_rpm in vega20_get_fan_speed_percent drm/amd/powerplay: Zero initialize freq in smu_v11_0_get_current_clk_freq drm/amd/powerplay: Use memset to initialize metrics structs drm/amdgpu/mes10.1: Fix header guard drm/amd/powerplay: add temperature sensor support for navi10 drm/amdgpu: fix scheduler timeout calc drm/amdgpu: Prepare for hmm_range_register API change (v2) ...
This commit is contained in:
Linus Torvalds
@@ -0,0 +1,100 @@
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/allwinner,sun6i-a31-mipi-dsi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Allwinner A31 MIPI-DSI Controller Device Tree Bindings
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maintainers:
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- Chen-Yu Tsai <wens@csie.org>
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- Maxime Ripard <maxime.ripard@bootlin.com>
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properties:
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"#address-cells": true
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"#size-cells": true
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compatible:
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const: allwinner,sun6i-a31-mipi-dsi
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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items:
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- description: Bus Clock
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- description: Module Clock
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clock-names:
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items:
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- const: bus
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- const: mod
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resets:
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maxItems: 1
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phys:
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maxItems: 1
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phy-names:
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const: dphy
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port:
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type: object
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description:
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A port node with endpoint definitions as defined in
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Documentation/devicetree/bindings/media/video-interfaces.txt. That
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port should be the input endpoint, usually coming from the
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associated TCON.
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patternProperties:
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"^panel@[0-9]+$": true
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required:
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- "#address-cells"
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- "#size-cells"
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- phys
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- phy-names
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- resets
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- port
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additionalProperties: false
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examples:
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- |
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dsi0: dsi@1ca0000 {
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compatible = "allwinner,sun6i-a31-mipi-dsi";
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reg = <0x01ca0000 0x1000>;
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interrupts = <0 89 4>;
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clocks = <&ccu 23>, <&ccu 96>;
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clock-names = "bus", "mod";
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resets = <&ccu 4>;
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phys = <&dphy0>;
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phy-names = "dphy";
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#address-cells = <1>;
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#size-cells = <0>;
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panel@0 {
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compatible = "bananapi,lhr050h41", "ilitek,ili9881c";
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reg = <0>;
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power-gpios = <&pio 1 7 0>; /* PB07 */
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reset-gpios = <&r_pio 0 5 1>; /* PL05 */
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backlight = <&pwm_bl>;
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};
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port {
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dsi0_in_tcon0: endpoint {
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remote-endpoint = <&tcon0_out_dsi0>;
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};
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};
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};
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...
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@@ -7,10 +7,13 @@ Required properties:
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- clocks: A list of phandle + clock-specifier pairs, one for each entry
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in 'clock-names'
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- clock-names: A list of clock names. It should contain:
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- "mclk": for the main processor clock
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- "pclk": for the APB interface clock
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- "aclk": for the main processor clock
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- #address-cells: Must be 1
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- #size-cells: Must be 0
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- iommus: configure the stream id to IOMMU, Must be configured if want to
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enable iommu in display. for how to configure this node please reference
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devicetree/bindings/iommu/arm,smmu-v3.txt,
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devicetree/bindings/iommu/iommu.txt
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Required properties for sub-node: pipeline@nq
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Each device contains one or two pipeline sub-nodes (at least one), each
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@@ -20,7 +23,6 @@ pipeline node should provide properties:
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in 'clock-names'
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- clock-names: should contain:
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- "pxclk": pixel clock
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- "aclk": AXI interface clock
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- port: each pipeline connect to an encoder input port. The connection is
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modeled using the OF graph bindings specified in
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@@ -42,12 +44,15 @@ Example:
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compatible = "arm,mali-d71";
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reg = <0xc00000 0x20000>;
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interrupts = <0 168 4>;
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clocks = <&dpu_mclk>, <&dpu_aclk>;
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clock-names = "mclk", "pclk";
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clocks = <&dpu_aclk>;
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clock-names = "aclk";
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iommus = <&smmu 0>, <&smmu 1>, <&smmu 2>, <&smmu 3>,
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<&smmu 4>, <&smmu 5>, <&smmu 6>, <&smmu 7>,
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<&smmu 8>, <&smmu 9>;
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dp0_pipe0: pipeline@0 {
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clocks = <&fpgaosc2>, <&dpu_aclk>;
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clock-names = "pxclk", "aclk";
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clocks = <&fpgaosc2>;
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clock-names = "pxclk";
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reg = <0>;
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port {
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@@ -58,8 +63,8 @@ Example:
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};
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dp0_pipe1: pipeline@1 {
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clocks = <&fpgaosc2>, <&dpu_aclk>;
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clock-names = "pxclk", "aclk";
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clocks = <&fpgaosc2>;
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clock-names = "pxclk";
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reg = <1>;
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port {
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@@ -9,6 +9,7 @@ Required properties:
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- compatible : Shall contain one of
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- "renesas,r8a7743-lvds" for R8A7743 (RZ/G1M) compatible LVDS encoders
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- "renesas,r8a7744-lvds" for R8A7744 (RZ/G1N) compatible LVDS encoders
|
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- "renesas,r8a774a1-lvds" for R8A774A1 (RZ/G2M) compatible LVDS encoders
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- "renesas,r8a774c0-lvds" for R8A774C0 (RZ/G2E) compatible LVDS encoders
|
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- "renesas,r8a7790-lvds" for R8A7790 (R-Car H2) compatible LVDS encoders
|
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- "renesas,r8a7791-lvds" for R8A7791 (R-Car M2-W) compatible LVDS encoders
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@@ -45,14 +46,24 @@ OF graph bindings specified in Documentation/devicetree/bindings/graph.txt.
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Each port shall have a single endpoint.
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Optional properties:
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- renesas,companion : phandle to the companion LVDS encoder. This property is
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mandatory for the first LVDS encoder on D3 and E3 SoCs, and shall point to
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the second encoder to be used as a companion in dual-link mode. It shall not
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be set for any other LVDS encoder.
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Example:
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lvds0: lvds@feb90000 {
|
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compatible = "renesas,r8a7790-lvds";
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reg = <0 0xfeb90000 0 0x1c>;
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clocks = <&cpg CPG_MOD 726>;
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resets = <&cpg 726>;
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compatible = "renesas,r8a77990-lvds";
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reg = <0 0xfeb90000 0 0x20>;
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clocks = <&cpg CPG_MOD 727>;
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power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
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resets = <&cpg 727>;
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renesas,companion = <&lvds1>;
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ports {
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#address-cells = <1>;
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|
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@@ -5,10 +5,44 @@ Required properties:
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- reg: i2c address of the bridge
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|
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Optional properties:
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- interrupts: describe the interrupt line used to inform the host
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- interrupts: describe the interrupt line used to inform the host
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about hotplug events.
|
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- reset-gpios: OF device-tree gpio specification for RST_N pin.
|
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|
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HDMI audio properties:
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- #sound-dai-cells: <0> or <1>. <0> if only i2s or spdif pin
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is wired, <1> if the both are wired. HDMI audio is
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configured only if this property is found.
|
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- sil,i2s-data-lanes: Array of up to 4 integers with values of 0-3
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Each integer indicates which i2s pin is connected to which
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audio fifo. The first integer selects i2s audio pin for the
|
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first audio fifo#0 (HDMI channels 1&2), second for fifo#1
|
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(HDMI channels 3&4), and so on. There is 4 fifos and 4 i2s
|
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pins (SD0 - SD3). Any i2s pin can be connected to any fifo,
|
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but there can be no gaps. E.g. an i2s pin must be mapped to
|
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fifo#0 and fifo#1 before mapping a channel to fifo#2. Default
|
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value is <0>, describing SD0 pin beiging routed to hdmi audio
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fifo #0.
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- clocks: phandle and clock specifier for each clock listed in
|
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the clock-names property
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- clock-names: "mclk"
|
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Describes SII902x MCLK input. MCLK is used to produce
|
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HDMI audio CTS values. This property is required if
|
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"#sound-dai-cells"-property is present. This property follows
|
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Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
consumer binding.
|
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|
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If HDMI audio is configured the sii902x device becomes an I2S
|
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and/or spdif audio codec component (e.g a digital audio sink),
|
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that can be used in configuring a full audio devices with
|
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simple-card or audio-graph-card binding. See their binding
|
||||
documents on how to describe the way the sii902x device is
|
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connected to the rest of the audio system:
|
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Documentation/devicetree/bindings/sound/simple-card.txt
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Documentation/devicetree/bindings/sound/audio-graph-card.txt
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Note: In case of the audio-graph-card binding the used port
|
||||
index should be 3.
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|
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Optional subnodes:
|
||||
- video input: this subnode can contain a video input port node
|
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to connect the bridge to a display controller output (See this
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@@ -21,6 +55,12 @@ Example:
|
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compatible = "sil,sii9022";
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reg = <0x39>;
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reset-gpios = <&pioA 1 0>;
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#sound-dai-cells = <0>;
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sil,i2s-data-lanes = < 0 1 2 >;
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clocks = <&mclk>;
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clock-names = "mclk";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
|
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|
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@@ -28,6 +28,12 @@ Optional video port nodes:
|
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- port@1: Second LVDS input port
|
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- port@3: Second digital CMOS/TTL parallel output
|
||||
|
||||
The device can operate in single-link mode or dual-link mode. In single-link
|
||||
mode, all pixels are received on port@0, and port@1 shall not contain any
|
||||
endpoint. In dual-link mode, even-numbered pixels are received on port@0 and
|
||||
odd-numbered pixels on port@1, and both port@0 and port@1 shall contain
|
||||
endpoints.
|
||||
|
||||
Example:
|
||||
--------
|
||||
|
||||
|
||||
@@ -12,6 +12,7 @@ Optional properties:
|
||||
(active high shutdown input)
|
||||
- reset-gpios: OF device-tree gpio specification for RSTX pin
|
||||
(active low system reset)
|
||||
- toshiba,hpd-pin: TC358767 GPIO pin number to which HPD is connected to (0 or 1)
|
||||
- ports: the ports node can contain video interface port nodes to connect
|
||||
to a DPI/DSI source and to an eDP/DP sink according to [1][2]:
|
||||
- port@0: DSI input port
|
||||
|
||||
44
Documentation/devicetree/bindings/display/ingenic,lcd.txt
Normal file
44
Documentation/devicetree/bindings/display/ingenic,lcd.txt
Normal file
@@ -0,0 +1,44 @@
|
||||
Ingenic JZ47xx LCD driver
|
||||
|
||||
Required properties:
|
||||
- compatible: one of:
|
||||
* ingenic,jz4740-lcd
|
||||
* ingenic,jz4725b-lcd
|
||||
- reg: LCD registers location and length
|
||||
- clocks: LCD pixclock and device clock specifiers.
|
||||
The device clock is only required on the JZ4740.
|
||||
- clock-names: "lcd_pclk" and "lcd"
|
||||
- interrupts: Specifies the interrupt line the LCD controller is connected to.
|
||||
|
||||
Example:
|
||||
|
||||
panel {
|
||||
compatible = "sharp,ls020b1dd01d";
|
||||
|
||||
backlight = <&backlight>;
|
||||
power-supply = <&vcc>;
|
||||
|
||||
port {
|
||||
panel_input: endpoint {
|
||||
remote-endpoint = <&panel_output>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
lcd: lcd-controller@13050000 {
|
||||
compatible = "ingenic,jz4725b-lcd";
|
||||
reg = <0x13050000 0x1000>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <31>;
|
||||
|
||||
clocks = <&cgu JZ4725B_CLK_LCD>;
|
||||
clock-names = "lcd";
|
||||
|
||||
port {
|
||||
panel_output: endpoint {
|
||||
remote-endpoint = <&panel_input>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -28,6 +28,11 @@ Required properties:
|
||||
- #address-cells: number of address cells for the MDSS children. Should be 1.
|
||||
- #size-cells: Should be 1.
|
||||
- ranges: parent bus address space is the same as the child bus address space.
|
||||
- interconnects : interconnect path specifier for MDSS according to
|
||||
Documentation/devicetree/bindings/interconnect/interconnect.txt. Should be
|
||||
2 paths corresponding to 2 AXI ports.
|
||||
- interconnect-names : MDSS will have 2 port names to differentiate between the
|
||||
2 interconnect paths defined with interconnect specifier.
|
||||
|
||||
Optional properties:
|
||||
- assigned-clocks: list of clock specifiers for clocks needing rate assignment
|
||||
@@ -86,6 +91,11 @@ Example:
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interconnects = <&rsc_hlos MASTER_MDP0 &rsc_hlos SLAVE_EBI1>,
|
||||
<&rsc_hlos MASTER_MDP1 &rsc_hlos SLAVE_EBI1>;
|
||||
|
||||
interconnect-names = "mdp0-mem", "mdp1-mem";
|
||||
|
||||
iommus = <&apps_iommu 0>;
|
||||
|
||||
#address-cells = <2>;
|
||||
|
||||
@@ -88,6 +88,7 @@ Required properties:
|
||||
* "qcom,dsi-phy-28nm-8960"
|
||||
* "qcom,dsi-phy-14nm"
|
||||
* "qcom,dsi-phy-10nm"
|
||||
* "qcom,dsi-phy-10nm-8998"
|
||||
- reg: Physical base address and length of the registers of PLL, PHY. Some
|
||||
revisions require the PHY regulator base address, whereas others require the
|
||||
PHY lane base address. See below for each PHY revision.
|
||||
|
||||
@@ -0,0 +1,9 @@
|
||||
Armadeus ST0700 Adapt. A Santek ST0700I5Y-RBSLW 7.0" WVGA (800x480) TFT with
|
||||
an adapter board.
|
||||
|
||||
Required properties:
|
||||
- compatible: "armadeus,st0700-adapt"
|
||||
- power-supply: see panel-common.txt
|
||||
|
||||
Optional properties:
|
||||
- backlight: see panel-common.txt
|
||||
@@ -6,6 +6,22 @@ Display bindings for EDT Display Technology Corp. Displays which are
|
||||
compatible with the simple-panel binding, which is specified in
|
||||
simple-panel.txt
|
||||
|
||||
3,5" QVGA TFT Panels
|
||||
--------------------
|
||||
+-----------------+---------------------+-------------------------------------+
|
||||
| Identifier | compatbile | description |
|
||||
+=================+=====================+=====================================+
|
||||
| ET035012DM6 | edt,et035012dm6 | 3.5" QVGA TFT LCD panel |
|
||||
+-----------------+---------------------+-------------------------------------+
|
||||
|
||||
4,3" WVGA TFT Panels
|
||||
--------------------
|
||||
|
||||
+-----------------+---------------------+-------------------------------------+
|
||||
| Identifier | compatbile | description |
|
||||
+=================+=====================+=====================================+
|
||||
| ETM0430G0DH6 | edt,etm0430g0dh6 | 480x272 TFT Display |
|
||||
+-----------------+---------------------+-------------------------------------+
|
||||
|
||||
5,7" WVGA TFT Panels
|
||||
--------------------
|
||||
|
||||
@@ -0,0 +1,12 @@
|
||||
Evervision Electronics Co. Ltd. VGG804821 5.0" WVGA TFT LCD Panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "evervision,vgg804821"
|
||||
- power-supply: See simple-panel.txt
|
||||
|
||||
Optional properties:
|
||||
- backlight: See simple-panel.txt
|
||||
- enable-gpios: See simple-panel.txt
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
||||
@@ -0,0 +1,32 @@
|
||||
FriendlyELEC HD702E 800x1280 LCD panel
|
||||
|
||||
HD702E lcd is FriendlyELEC developed eDP LCD panel with 800x1280
|
||||
resolution. It has built in Goodix, GT9271 captive touchscreen
|
||||
with backlight adjustable via PWM.
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "friendlyarm,hd702e"
|
||||
- power-supply: regulator to provide the supply voltage
|
||||
|
||||
Optional properties:
|
||||
- backlight: phandle of the backlight device attached to the panel
|
||||
|
||||
Optional nodes:
|
||||
- Video port for LCD panel input.
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
||||
|
||||
Example:
|
||||
|
||||
panel {
|
||||
compatible ="friendlyarm,hd702e", "simple-panel";
|
||||
backlight = <&backlight>;
|
||||
power-supply = <&vcc3v3_sys>;
|
||||
|
||||
port {
|
||||
panel_in_edp: endpoint {
|
||||
remote-endpoint = <&edp_out_panel>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,42 @@
|
||||
Kaohsiung Opto-Electronics Inc. 5.7" QVGA (320 x 240) TFT LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "koe,tx14d24vm1bpa"
|
||||
- backlight: phandle of the backlight device attached to the panel
|
||||
- power-supply: single regulator to provide the supply voltage
|
||||
|
||||
Required nodes:
|
||||
- port: Parallel port mapping to connect this display
|
||||
|
||||
This panel needs single power supply voltage. Its backlight is conntrolled
|
||||
via PWM signal.
|
||||
|
||||
Example:
|
||||
--------
|
||||
|
||||
Example device-tree definition when connected to iMX53 based board
|
||||
|
||||
lcd_panel: lcd-panel {
|
||||
compatible = "koe,tx14d24vm1bpa";
|
||||
backlight = <&backlight_lcd>;
|
||||
power-supply = <®_3v3>;
|
||||
|
||||
port {
|
||||
lcd_panel_in: endpoint {
|
||||
remote-endpoint = <&lcd_display_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
Then one needs to extend the dispX node:
|
||||
|
||||
lcd_display: disp1 {
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
lcd_display_out: endpoint {
|
||||
remote-endpoint = <&lcd_panel_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,11 @@
|
||||
One Stop Displays OSD101T2045-53TS 10.1" 1920x1200 panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "osddisplays,osd101t2045-53ts"
|
||||
- power-supply: as specified in the base binding
|
||||
|
||||
Optional properties:
|
||||
- backlight: as specified in the base binding
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
||||
@@ -0,0 +1,14 @@
|
||||
One Stop Displays OSD101T2587-53TS 10.1" 1920x1200 panel
|
||||
|
||||
The panel is similar to OSD101T2045-53TS, but it needs additional
|
||||
MIPI_DSI_TURN_ON_PERIPHERAL message from the host.
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "osddisplays,osd101t2587-53ts"
|
||||
- power-supply: as specified in the base binding
|
||||
|
||||
Optional properties:
|
||||
- backlight: as specified in the base binding
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
||||
@@ -0,0 +1,33 @@
|
||||
Samsung s6e63m0 AMOLED LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: "samsung,s6e63m0"
|
||||
- reset-gpios: GPIO spec for reset pin
|
||||
- vdd3-supply: VDD regulator
|
||||
- vci-supply: VCI regulator
|
||||
|
||||
The panel must obey rules for SPI slave device specified in document [1].
|
||||
|
||||
The device node can contain one 'port' child node with one child
|
||||
'endpoint' node, according to the bindings defined in [2]. This
|
||||
node should describe panel's video bus.
|
||||
|
||||
[1]: Documentation/devicetree/bindings/spi/spi-bus.txt
|
||||
[2]: Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||
|
||||
Example:
|
||||
|
||||
s6e63m0: display@0 {
|
||||
compatible = "samsung,s6e63m0";
|
||||
reg = <0>;
|
||||
reset-gpio = <&mp05 5 1>;
|
||||
vdd3-supply = <&ldo12_reg>;
|
||||
vci-supply = <&ldo11_reg>;
|
||||
spi-max-frequency = <1200000>;
|
||||
|
||||
port {
|
||||
lcd_ep: endpoint {
|
||||
remote-endpoint = <&fimd_ep>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,15 @@
|
||||
TFC S9700RTWV43TR-01B 7" Three Five Corp 800x480 LCD panel with
|
||||
resistive touch
|
||||
|
||||
The panel is found on TI AM335x-evm.
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "tfc,s9700rtwv43tr-01b"
|
||||
- power-supply: See panel-common.txt
|
||||
|
||||
Optional properties:
|
||||
- enable-gpios: GPIO pin to enable or disable the panel, if there is one
|
||||
- backlight: phandle of the backlight device attached to the panel
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
||||
@@ -0,0 +1,12 @@
|
||||
VXT 800x480 color TFT LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "vxt,vl050-8048nt-c01"
|
||||
- power-supply: as specified in the base binding
|
||||
|
||||
Optional properties:
|
||||
- backlight: as specified in the base binding
|
||||
- enable-gpios: as specified in the base binding
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
||||
@@ -7,6 +7,7 @@ Required Properties:
|
||||
- "renesas,du-r8a7744" for R8A7744 (RZ/G1N) compatible DU
|
||||
- "renesas,du-r8a7745" for R8A7745 (RZ/G1E) compatible DU
|
||||
- "renesas,du-r8a77470" for R8A77470 (RZ/G1C) compatible DU
|
||||
- "renesas,du-r8a774a1" for R8A774A1 (RZ/G2M) compatible DU
|
||||
- "renesas,du-r8a774c0" for R8A774C0 (RZ/G2E) compatible DU
|
||||
- "renesas,du-r8a7779" for R8A7779 (R-Car H1) compatible DU
|
||||
- "renesas,du-r8a7790" for R8A7790 (R-Car H2) compatible DU
|
||||
@@ -58,6 +59,7 @@ corresponding to each DU output.
|
||||
R8A7744 (RZ/G1N) DPAD 0 LVDS 0 - -
|
||||
R8A7745 (RZ/G1E) DPAD 0 DPAD 1 - -
|
||||
R8A77470 (RZ/G1C) DPAD 0 DPAD 1 LVDS 0 -
|
||||
R8A774A1 (RZ/G2M) DPAD 0 HDMI 0 LVDS 0 -
|
||||
R8A774C0 (RZ/G2E) DPAD 0 LVDS 0 LVDS 1 -
|
||||
R8A7779 (R-Car H1) DPAD 0 DPAD 1 - -
|
||||
R8A7790 (R-Car H2) DPAD 0 LVDS 0 LVDS 1 -
|
||||
|
||||
@@ -12,6 +12,7 @@ following device-specific properties.
|
||||
Required properties:
|
||||
|
||||
- compatible: should be one of the following:
|
||||
"rockchip,rk3228-dw-hdmi"
|
||||
"rockchip,rk3288-dw-hdmi"
|
||||
"rockchip,rk3328-dw-hdmi"
|
||||
"rockchip,rk3399-dw-hdmi"
|
||||
@@ -38,6 +39,13 @@ Optional properties
|
||||
- phys: from general PHY binding: the phandle for the PHY device.
|
||||
- phy-names: Should be "hdmi" if phys references an external phy.
|
||||
|
||||
Optional pinctrl entry:
|
||||
- If you have both a "unwedge" and "default" pinctrl entry, dw_hdmi
|
||||
will switch to the unwedge pinctrl state for 10ms if it ever gets an
|
||||
i2c timeout. It's intended that this unwedge pinctrl entry will
|
||||
cause the SDA line to be driven low to work around a hardware
|
||||
errata.
|
||||
|
||||
Example:
|
||||
|
||||
hdmi: hdmi@ff980000 {
|
||||
|
||||
@@ -40,6 +40,8 @@ Mandatory nodes specific to STM32 DSI:
|
||||
- panel or bridge node: A node containing the panel or bridge description as
|
||||
documented in [6].
|
||||
- port: panel or bridge port node, connected to the DSI output port (port@1).
|
||||
Optional properties:
|
||||
- phy-dsi-supply: phandle of the regulator that provides the supply voltage.
|
||||
|
||||
Note: You can find more documentation in the following references
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
@@ -101,6 +103,7 @@ Example 2: DSI panel
|
||||
clock-names = "pclk", "ref";
|
||||
resets = <&rcc STM32F4_APB2_RESET(DSI)>;
|
||||
reset-names = "apb";
|
||||
phy-dsi-supply = <®18>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
|
||||
@@ -1,93 +0,0 @@
|
||||
Allwinner A31 DSI Encoder
|
||||
=========================
|
||||
|
||||
The DSI pipeline consists of two separate blocks: the DSI controller
|
||||
itself, and its associated D-PHY.
|
||||
|
||||
DSI Encoder
|
||||
-----------
|
||||
|
||||
The DSI Encoder generates the DSI signal from the TCON's.
|
||||
|
||||
Required properties:
|
||||
- compatible: value must be one of:
|
||||
* allwinner,sun6i-a31-mipi-dsi
|
||||
- reg: base address and size of memory-mapped region
|
||||
- interrupts: interrupt associated to this IP
|
||||
- clocks: phandles to the clocks feeding the DSI encoder
|
||||
* bus: the DSI interface clock
|
||||
* mod: the DSI module clock
|
||||
- clock-names: the clock names mentioned above
|
||||
- phys: phandle to the D-PHY
|
||||
- phy-names: must be "dphy"
|
||||
- resets: phandle to the reset controller driving the encoder
|
||||
|
||||
- ports: A ports node with endpoint definitions as defined in
|
||||
Documentation/devicetree/bindings/media/video-interfaces.txt. The
|
||||
first port should be the input endpoint, usually coming from the
|
||||
associated TCON.
|
||||
|
||||
Any MIPI-DSI device attached to this should be described according to
|
||||
the bindings defined in ../mipi-dsi-bus.txt
|
||||
|
||||
D-PHY
|
||||
-----
|
||||
|
||||
Required properties:
|
||||
- compatible: value must be one of:
|
||||
* allwinner,sun6i-a31-mipi-dphy
|
||||
- reg: base address and size of memory-mapped region
|
||||
- clocks: phandles to the clocks feeding the DSI encoder
|
||||
* bus: the DSI interface clock
|
||||
* mod: the DSI module clock
|
||||
- clock-names: the clock names mentioned above
|
||||
- resets: phandle to the reset controller driving the encoder
|
||||
|
||||
Example:
|
||||
|
||||
dsi0: dsi@1ca0000 {
|
||||
compatible = "allwinner,sun6i-a31-mipi-dsi";
|
||||
reg = <0x01ca0000 0x1000>;
|
||||
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu CLK_BUS_MIPI_DSI>,
|
||||
<&ccu CLK_DSI_SCLK>;
|
||||
clock-names = "bus", "mod";
|
||||
resets = <&ccu RST_BUS_MIPI_DSI>;
|
||||
phys = <&dphy0>;
|
||||
phy-names = "dphy";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
panel@0 {
|
||||
compatible = "bananapi,lhr050h41", "ilitek,ili9881c";
|
||||
reg = <0>;
|
||||
power-gpios = <&pio 1 7 GPIO_ACTIVE_HIGH>; /* PB07 */
|
||||
reset-gpios = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL05 */
|
||||
backlight = <&pwm_bl>;
|
||||
};
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
|
||||
dsi0_in_tcon0: endpoint {
|
||||
remote-endpoint = <&tcon0_out_dsi0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dphy0: d-phy@1ca1000 {
|
||||
compatible = "allwinner,sun6i-a31-mipi-dphy";
|
||||
reg = <0x01ca1000 0x1000>;
|
||||
clocks = <&ccu CLK_BUS_MIPI_DSI>,
|
||||
<&ccu CLK_DSI_DPHY>;
|
||||
clock-names = "bus", "mod";
|
||||
resets = <&ccu RST_BUS_MIPI_DSI>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
Reference in New Issue
Block a user