drm/i915: add VLV DSI PLL Calculations

v2:
 - Grab dpio_lock mutex in vlv_enable_dsi_pll().
 - Add and call vlv_disable_dsi_pll().

v3: Mostly based on Ville's review comments.
 - Only pipe A has DSI PLL lock bit.
 - Add more of CCK REG bit definitions for DSI PLL.
 - Make tables static.
 - Move clock gating out of the clock calculation functions.
 - DSI PLL LDO power gating.
 - Put alternative MNP from table calc behind #ifdef.

v4: s/CKK/CLK/ in the CCK REG bit definitions (Ville).

Signed-off-by: ymohanma <yogesh.mohan.marimuthu@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

drivers/gpu/drm/i915/intel_dsi.c

@@ -83,6 +83,8 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
 static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder)
 {
 	DRM_DEBUG_KMS("\n");
+
+	vlv_enable_dsi_pll(encoder);
 }
 
 static void intel_dsi_pre_enable(struct intel_encoder *encoder)
@@ -167,6 +169,8 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
 static void intel_dsi_post_disable(struct intel_encoder *encoder)
 {
 	DRM_DEBUG_KMS("\n");
+
+	vlv_disable_dsi_pll(encoder);
 }
 
 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
@@ -303,6 +307,9 @@ static void intel_dsi_mode_set(struct intel_encoder *intel_encoder)
 
 	DRM_DEBUG_KMS("pipe %d\n", pipe);
 
+	/* Update the DSI PLL */
+	vlv_enable_dsi_pll(intel_encoder);
+
 	/* escape clock divider, 20MHz, shared for A and C. device ready must be
 	 * off when doing this! txclkesc? */
 	tmp = I915_READ(MIPI_CTRL(0));