cpufreq: exynos: Fix the compile error
Commit 7da83a80 ("ARM: EXYNOS: Migrate Exynos specific macros from plat to mach") which lands in samsung tree causes build breakage for cpufreq-exynos like following: drivers/cpufreq/exynos-cpufreq.c: In function 'exynos_cpufreq_probe': drivers/cpufreq/exynos-cpufreq.c:166:2: error: implicit declaration of function 'soc_is_exynos4210' [-Werror=implicit-function-declaration] drivers/cpufreq/exynos-cpufreq.c:168:2: error: implicit declaration of function 'soc_is_exynos4212' [-Werror=implicit-function-declaration] drivers/cpufreq/exynos-cpufreq.c:168:2: error: implicit declaration of function 'soc_is_exynos4412' [-Werror=implicit-function-declaration] drivers/cpufreq/exynos-cpufreq.c:170:2: error: implicit declaration of function 'soc_is_exynos5250' [-Werror=implicit-function-declaration] cc1: some warnings being treated as errors make[2]: *** [drivers/cpufreq/exynos-cpufreq.o] Error 1 make[2]: *** Waiting for unfinished jobs.... drivers/cpufreq/exynos4x12-cpufreq.c: In function 'exynos4x12_set_clkdiv': drivers/cpufreq/exynos4x12-cpufreq.c:118:2: error: implicit declaration of function 'soc_is_exynos4212' [-Werror=implicit-function-declaration] cc1: some warnings being treated as errors make[2]: *** [drivers/cpufreq/exynos4x12-cpufreq.o] Error 1 make[1]: *** [drivers/cpufreq] Error 2 This fixes above error with getting SoC information via of_machine_is_compatible() instead of soc_is_exynosXXXX(). Suggested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Jonghwan Choi <jhbird.choi@samsung.com> [kgene.kim@samsung.com: fixed typo and modified as per Viresh's suggestion] [kgene.kim@samsung.com: Rafael agreed] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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committed by
Kukjin Kim

parent
2cd62bd4e5
commit
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@@ -17,6 +17,13 @@ enum cpufreq_level_index {
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L20,
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};
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enum exynos_soc_type {
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EXYNOS_SOC_4210,
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EXYNOS_SOC_4212,
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EXYNOS_SOC_4412,
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EXYNOS_SOC_5250,
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};
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#define APLL_FREQ(f, a0, a1, a2, a3, a4, a5, a6, a7, b0, b1, b2, m, p, s) \
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{ \
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.freq = (f) * 1000, \
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@@ -34,6 +41,7 @@ struct apll_freq {
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};
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struct exynos_dvfs_info {
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enum exynos_soc_type type;
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unsigned long mpll_freq_khz;
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unsigned int pll_safe_idx;
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struct clk *cpu_clk;
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