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qed*: Utilize Firmware 8.15.3.0

Browse Source 
This patch advances the qed* drivers into using the newer firmware -
This solves several firmware bugs, mostly related [but not limited to]
various init/deinit issues in various offloaded protocols.

It also introduces a major 4-Cached SGE change in firmware, which can be
seen in the storage drivers' changes.

In addition, this firmware is required for supporting the new QL41xxx
series of adapters; While this patch doesn't add the actual support,
the firmware contains the necessary initialization & firmware logic to
operate such adapters [actual support would be added later on].

Changes from Previous versions:
-------------------------------
 - V2 - fix kbuild-test robot warnings

Signed-off-by: Tomer Tayar <Tomer.Tayar@cavium.com>
Signed-off-by: Ram Amrani <Ram.Amrani@cavium.com>
Signed-off-by: Manish Rangankar <Manish.Rangankar@cavium.com>
Signed-off-by: Chad Dupuis <Chad.Dupuis@cavium.com>
Signed-off-by: Yuval Mintz <Yuval.Mintz@cavium.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Mintz, Yuval
2017-03-11 18:39:18 +02:00
committed by David S. Miller
parent 6a019c5c50
commit be086e7c53
40 changed files with 4208 additions and 2202 deletions
Download Patch File Download Diff File Expand all files Collapse all files

30
include/linux/qed/common_hsi.h
View File

@@ -100,8 +100,8 @@
#define MAX_NUM_LL2_TX_STATS_COUNTERS 32
#define FW_MAJOR_VERSION 8
#define FW_MINOR_VERSION 10
#define FW_REVISION_VERSION 10
#define FW_MINOR_VERSION 15
#define FW_REVISION_VERSION 3
#define FW_ENGINEERING_VERSION 0
/***********************/
@@ -187,6 +187,9 @@
/* DEMS */
#define DQ_DEMS_LEGACY 0
#define DQ_DEMS_TOE_MORE_TO_SEND 3
#define DQ_DEMS_TOE_LOCAL_ADV_WND 4
#define DQ_DEMS_ROCE_CQ_CONS 7
/* XCM agg val selection */
#define DQ_XCM_AGG_VAL_SEL_WORD2 0
@@ -214,6 +217,9 @@
#define DQ_XCM_ISCSI_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3
#define DQ_XCM_ISCSI_EXP_STAT_SN_CMD DQ_XCM_AGG_VAL_SEL_REG6
#define DQ_XCM_ROCE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
#define DQ_XCM_TOE_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
#define DQ_XCM_TOE_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3
#define DQ_XCM_TOE_LOCAL_ADV_WND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG4
/* UCM agg val selection (HW) */
#define DQ_UCM_AGG_VAL_SEL_WORD0 0
@@ -269,6 +275,8 @@
#define DQ_XCM_ISCSI_DQ_FLUSH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19)
#define DQ_XCM_ISCSI_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
#define DQ_XCM_ISCSI_PROC_ONLY_CLEANUP_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF23)
#define DQ_XCM_TOE_DQ_FLUSH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19)
#define DQ_XCM_TOE_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
/* UCM agg counter flag selection (HW) */
#define DQ_UCM_AGG_FLG_SHIFT_CF0 0
@@ -285,6 +293,9 @@
#define DQ_UCM_ETH_PMD_RX_ARM_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF5)
#define DQ_UCM_ROCE_CQ_ARM_SE_CF_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF4)
#define DQ_UCM_ROCE_CQ_ARM_CF_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF5)
#define DQ_UCM_TOE_TIMER_STOP_ALL_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF3)
#define DQ_UCM_TOE_SLOW_PATH_CF_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF4)
#define DQ_UCM_TOE_DQ_CF_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF5)
/* TCM agg counter flag selection (HW) */
#define DQ_TCM_AGG_FLG_SHIFT_CF0 0
@@ -301,6 +312,9 @@
#define DQ_TCM_FCOE_TIMER_STOP_ALL_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF3)
#define DQ_TCM_ISCSI_FLUSH_Q0_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1)
#define DQ_TCM_ISCSI_TIMER_STOP_ALL_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF3)
#define DQ_TCM_TOE_FLUSH_Q0_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1)
#define DQ_TCM_TOE_TIMER_STOP_ALL_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF3)
#define DQ_TCM_IWARP_POST_RQ_CF_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1)
/* PWM address mapping */
#define DQ_PWM_OFFSET_DPM_BASE 0x0
@@ -689,6 +703,16 @@ struct iscsi_eqe_data {
#define ISCSI_EQE_DATA_RESERVED0_SHIFT 7
};
struct rdma_eqe_destroy_qp {
__le32 cid;
u8 reserved[4];
};
union rdma_eqe_data {
struct regpair async_handle;
struct rdma_eqe_destroy_qp rdma_destroy_qp_data;
};
struct malicious_vf_eqe_data {
u8 vf_id;
u8 err_id;
@@ -705,9 +729,9 @@ union event_ring_data {
u8 bytes[8];
struct vf_pf_channel_eqe_data vf_pf_channel;
struct iscsi_eqe_data iscsi_info;
union rdma_eqe_data rdma_data;
struct malicious_vf_eqe_data malicious_vf;
struct initial_cleanup_eqe_data vf_init_cleanup;
struct regpair roce_handle;
};
/* Event Ring Entry */

3
include/linux/qed/eth_common.h
View File

@@ -49,6 +49,9 @@
#define ETH_RX_CQE_PAGE_SIZE_BYTES 4096
#define ETH_RX_NUM_NEXT_PAGE_BDS 2
#define ETH_MAX_TUNN_LSO_INNER_IPV4_OFFSET 253
#define ETH_MAX_TUNN_LSO_INNER_IPV6_OFFSET 251
#define ETH_TX_MIN_BDS_PER_NON_LSO_PKT 1
#define ETH_TX_MAX_BDS_PER_NON_LSO_PACKET 18
#define ETH_TX_MAX_BDS_PER_LSO_PACKET 255

180
include/linux/qed/fcoe_common.h
View File

@@ -109,13 +109,6 @@ struct fcoe_conn_terminate_ramrod_data {
struct regpair terminate_params_addr;
};
struct fcoe_fast_sgl_ctx {
struct regpair sgl_start_addr;
__le32 sgl_byte_offset;
__le16 task_reuse_cnt;
__le16 init_offset_in_first_sge;
};
struct fcoe_slow_sgl_ctx {
struct regpair base_sgl_addr;
__le16 curr_sge_off;
@@ -124,23 +117,16 @@ struct fcoe_slow_sgl_ctx {
__le16 reserved;
};
struct fcoe_sge {
struct regpair sge_addr;
__le16 size;
__le16 reserved0;
u8 reserved1[3];
u8 is_valid_sge;
};
union fcoe_data_desc_ctx {
struct fcoe_fast_sgl_ctx fast;
struct fcoe_slow_sgl_ctx slow;
struct fcoe_sge single_sge;
};
union fcoe_dix_desc_ctx {
struct fcoe_slow_sgl_ctx dix_sgl;
struct fcoe_sge cached_dix_sge;
struct scsi_sge cached_dix_sge;
};
struct fcoe_fast_sgl_ctx {
struct regpair sgl_start_addr;
__le32 sgl_byte_offset;
__le16 task_reuse_cnt;
__le16 init_offset_in_first_sge;
};
struct fcoe_fcp_cmd_payload {
@@ -172,57 +158,6 @@ enum fcoe_mode_type {
MAX_FCOE_MODE_TYPE
};
struct fcoe_mstorm_fcoe_task_st_ctx_fp {
__le16 flags;
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_FP_RSRV0_MASK 0x7FFF
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_FP_RSRV0_SHIFT 0
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_FP_MP_INCLUDE_FC_HEADER_MASK 0x1
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_FP_MP_INCLUDE_FC_HEADER_SHIFT 15
__le16 difDataResidue;
__le16 parent_id;
__le16 single_sge_saved_offset;
__le32 data_2_trns_rem;
__le32 offset_in_io;
union fcoe_dix_desc_ctx dix_desc;
union fcoe_data_desc_ctx data_desc;
};
struct fcoe_mstorm_fcoe_task_st_ctx_non_fp {
__le16 flags;
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_HOST_INTERFACE_MASK 0x3
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_HOST_INTERFACE_SHIFT 0
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_DIF_TO_PEER_MASK 0x1
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_DIF_TO_PEER_SHIFT 2
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_VALIDATE_DIX_APP_TAG_MASK 0x1
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_VALIDATE_DIX_APP_TAG_SHIFT 3
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_INTERVAL_SIZE_LOG_MASK 0xF
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_INTERVAL_SIZE_LOG_SHIFT 4
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_DIX_BLOCK_SIZE_MASK 0x3
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_DIX_BLOCK_SIZE_SHIFT 8
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_RESERVED_MASK 0x1
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_RESERVED_SHIFT 10
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_HAS_FIRST_PACKET_ARRIVED_MASK 0x1
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_HAS_FIRST_PACKET_ARRIVED_SHIFT 11
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_VALIDATE_DIX_REF_TAG_MASK 0x1
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_VALIDATE_DIX_REF_TAG_SHIFT 12
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_DIX_CACHED_SGE_FLG_MASK 0x1
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_DIX_CACHED_SGE_FLG_SHIFT 13
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_OFFSET_IN_IO_VALID_MASK 0x1
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_OFFSET_IN_IO_VALID_SHIFT 14
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_DIF_SUPPORTED_MASK 0x1
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_DIF_SUPPORTED_SHIFT 15
u8 tx_rx_sgl_mode;
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_TX_SGL_MODE_MASK 0x7
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_TX_SGL_MODE_SHIFT 0
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_RX_SGL_MODE_MASK 0x7
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_RX_SGL_MODE_SHIFT 3
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_RSRV1_MASK 0x3
#define FCOE_MSTORM_FCOE_TASK_ST_CTX_NON_FP_RSRV1_SHIFT 6
u8 rsrv2;
__le32 num_prm_zero_read;
struct regpair rsp_buf_addr;
};
struct fcoe_rx_stat {
struct regpair fcoe_rx_byte_cnt;
struct regpair fcoe_rx_data_pkt_cnt;
@@ -236,16 +171,6 @@ struct fcoe_rx_stat {
__le32 rsrv;
};
enum fcoe_sgl_mode {
FCOE_SLOW_SGL,
FCOE_SINGLE_FAST_SGE,
FCOE_2_FAST_SGE,
FCOE_3_FAST_SGE,
FCOE_4_FAST_SGE,
FCOE_MUL_FAST_SGES,
MAX_FCOE_SGL_MODE
};
struct fcoe_stat_ramrod_data {
struct regpair stat_params_addr;
};
@@ -328,22 +253,24 @@ union fcoe_tx_info_union_ctx {
struct ystorm_fcoe_task_st_ctx {
u8 task_type;
u8 sgl_mode;
#define YSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_MASK 0x7
#define YSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_MASK 0x1
#define YSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_SHIFT 0
#define YSTORM_FCOE_TASK_ST_CTX_RSRV_MASK 0x1F
#define YSTORM_FCOE_TASK_ST_CTX_RSRV_SHIFT 3
#define YSTORM_FCOE_TASK_ST_CTX_RSRV_MASK 0x7F
#define YSTORM_FCOE_TASK_ST_CTX_RSRV_SHIFT 1
u8 cached_dix_sge;
u8 expect_first_xfer;
__le32 num_pbf_zero_write;
union protection_info_union_ctx protection_info_union;
__le32 data_2_trns_rem;
struct scsi_sgl_params sgl_params;
u8 reserved1[12];
union fcoe_tx_info_union_ctx tx_info_union;
union fcoe_dix_desc_ctx dix_desc;
union fcoe_data_desc_ctx data_desc;
struct scsi_cached_sges data_desc;
__le16 ox_id;
__le16 rx_id;
__le32 task_rety_identifier;
__le32 reserved1[2];
u8 reserved2[8];
};
struct ystorm_fcoe_task_ag_ctx {
@@ -484,22 +411,22 @@ struct tstorm_fcoe_task_ag_ctx {
struct fcoe_tstorm_fcoe_task_st_ctx_read_write {
union fcoe_cleanup_addr_exp_ro_union cleanup_addr_exp_ro_union;
__le16 flags;
#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RX_SGL_MODE_MASK 0x7
#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RX_SGL_MODE_MASK 0x1
#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RX_SGL_MODE_SHIFT 0
#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_EXP_FIRST_FRAME_MASK 0x1
#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_EXP_FIRST_FRAME_SHIFT 3
#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_EXP_FIRST_FRAME_SHIFT 1
#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_ACTIVE_MASK 0x1
#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_ACTIVE_SHIFT 4
#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_ACTIVE_SHIFT 2
#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_TIMEOUT_MASK 0x1
#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_TIMEOUT_SHIFT 5
#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_TIMEOUT_SHIFT 3
#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SINGLE_PKT_IN_EX_MASK 0x1
#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SINGLE_PKT_IN_EX_SHIFT 6
#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SINGLE_PKT_IN_EX_SHIFT 4
#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_OOO_RX_SEQ_STAT_MASK 0x1
#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_OOO_RX_SEQ_STAT_SHIFT 7
#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_OOO_RX_SEQ_STAT_SHIFT 5
#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_CQ_ADD_ADV_MASK 0x3
#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_CQ_ADD_ADV_SHIFT 8
#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RSRV1_MASK 0x3F
#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RSRV1_SHIFT 10
#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_CQ_ADD_ADV_SHIFT 6
#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RSRV1_MASK 0xFF
#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RSRV1_SHIFT 8
__le16 seq_cnt;
u8 seq_id;
u8 ooo_rx_seq_id;
@@ -582,8 +509,34 @@ struct mstorm_fcoe_task_ag_ctx {
};
struct mstorm_fcoe_task_st_ctx {
struct fcoe_mstorm_fcoe_task_st_ctx_non_fp non_fp;
struct fcoe_mstorm_fcoe_task_st_ctx_fp fp;
struct regpair rsp_buf_addr;
__le32 rsrv[2];
struct scsi_sgl_params sgl_params;
__le32 data_2_trns_rem;
__le32 data_buffer_offset;
__le16 parent_id;
__le16 flags;
#define MSTORM_FCOE_TASK_ST_CTX_INTERVAL_SIZE_LOG_MASK 0xF
#define MSTORM_FCOE_TASK_ST_CTX_INTERVAL_SIZE_LOG_SHIFT 0
#define MSTORM_FCOE_TASK_ST_CTX_HOST_INTERFACE_MASK 0x3
#define MSTORM_FCOE_TASK_ST_CTX_HOST_INTERFACE_SHIFT 4
#define MSTORM_FCOE_TASK_ST_CTX_DIF_TO_PEER_MASK 0x1
#define MSTORM_FCOE_TASK_ST_CTX_DIF_TO_PEER_SHIFT 6
#define MSTORM_FCOE_TASK_ST_CTX_MP_INCLUDE_FC_HEADER_MASK 0x1
#define MSTORM_FCOE_TASK_ST_CTX_MP_INCLUDE_FC_HEADER_SHIFT 7
#define MSTORM_FCOE_TASK_ST_CTX_DIX_BLOCK_SIZE_MASK 0x3
#define MSTORM_FCOE_TASK_ST_CTX_DIX_BLOCK_SIZE_SHIFT 8
#define MSTORM_FCOE_TASK_ST_CTX_VALIDATE_DIX_REF_TAG_MASK 0x1
#define MSTORM_FCOE_TASK_ST_CTX_VALIDATE_DIX_REF_TAG_SHIFT 10
#define MSTORM_FCOE_TASK_ST_CTX_DIX_CACHED_SGE_FLG_MASK 0x1
#define MSTORM_FCOE_TASK_ST_CTX_DIX_CACHED_SGE_FLG_SHIFT 11
#define MSTORM_FCOE_TASK_ST_CTX_DIF_SUPPORTED_MASK 0x1
#define MSTORM_FCOE_TASK_ST_CTX_DIF_SUPPORTED_SHIFT 12
#define MSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_MASK 0x1
#define MSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_SHIFT 13
#define MSTORM_FCOE_TASK_ST_CTX_RESERVED_MASK 0x3
#define MSTORM_FCOE_TASK_ST_CTX_RESERVED_SHIFT 14
struct scsi_cached_sges data_desc;
};
struct ustorm_fcoe_task_ag_ctx {
@@ -646,6 +599,7 @@ struct ustorm_fcoe_task_ag_ctx {
struct fcoe_task_context {
struct ystorm_fcoe_task_st_ctx ystorm_st_context;
struct regpair ystorm_st_padding[2];
struct tdif_task_context tdif_context;
struct ystorm_fcoe_task_ag_ctx ystorm_ag_context;
struct tstorm_fcoe_task_ag_ctx tstorm_ag_context;
@@ -668,20 +622,20 @@ struct fcoe_tx_stat {
struct fcoe_wqe {
__le16 task_id;
__le16 flags;
#define FCOE_WQE_REQ_TYPE_MASK 0xF
#define FCOE_WQE_REQ_TYPE_SHIFT 0
#define FCOE_WQE_SGL_MODE_MASK 0x7
#define FCOE_WQE_SGL_MODE_SHIFT 4
#define FCOE_WQE_CONTINUATION_MASK 0x1
#define FCOE_WQE_CONTINUATION_SHIFT 7
#define FCOE_WQE_INVALIDATE_PTU_MASK 0x1
#define FCOE_WQE_INVALIDATE_PTU_SHIFT 8
#define FCOE_WQE_SUPER_IO_MASK 0x1
#define FCOE_WQE_SUPER_IO_SHIFT 9
#define FCOE_WQE_SEND_AUTO_RSP_MASK 0x1
#define FCOE_WQE_SEND_AUTO_RSP_SHIFT 10
#define FCOE_WQE_RESERVED0_MASK 0x1F
#define FCOE_WQE_RESERVED0_SHIFT 11
#define FCOE_WQE_REQ_TYPE_MASK 0xF
#define FCOE_WQE_REQ_TYPE_SHIFT 0
#define FCOE_WQE_SGL_MODE_MASK 0x1
#define FCOE_WQE_SGL_MODE_SHIFT 4
#define FCOE_WQE_CONTINUATION_MASK 0x1
#define FCOE_WQE_CONTINUATION_SHIFT 5
#define FCOE_WQE_SEND_AUTO_RSP_MASK 0x1
#define FCOE_WQE_SEND_AUTO_RSP_SHIFT 6
#define FCOE_WQE_RESERVED_MASK 0x1
#define FCOE_WQE_RESERVED_SHIFT 7
#define FCOE_WQE_NUM_SGES_MASK 0xF
#define FCOE_WQE_NUM_SGES_SHIFT 8
#define FCOE_WQE_RESERVED1_MASK 0xF
#define FCOE_WQE_RESERVED1_SHIFT 12
union fcoe_additional_info_union additional_info_union;
};

243
include/linux/qed/iscsi_common.h
View File

@@ -39,17 +39,9 @@
/* iSCSI HSI constants */
#define ISCSI_DEFAULT_MTU (1500)
/* Current iSCSI HSI version number composed of two fields (16 bit) */
#define ISCSI_HSI_MAJOR_VERSION (0)
#define ISCSI_HSI_MINOR_VERSION (0)
/* KWQ (kernel work queue) layer codes */
#define ISCSI_SLOW_PATH_LAYER_CODE (6)
/* CQE completion status */
#define ISCSI_EQE_COMPLETION_SUCCESS (0x0)
#define ISCSI_EQE_RST_CONN_RCVD (0x1)
/* iSCSI parameter defaults */
#define ISCSI_DEFAULT_HEADER_DIGEST (0)
#define ISCSI_DEFAULT_DATA_DIGEST (0)
@@ -68,6 +60,10 @@
#define ISCSI_MIN_VAL_MAX_OUTSTANDING_R2T (1)
#define ISCSI_MAX_VAL_MAX_OUTSTANDING_R2T (0xff)
#define ISCSI_AHS_CNTL_SIZE 4
#define ISCSI_WQE_NUM_SGES_SLOWIO (0xf)
/* iSCSI reserved params */
#define ISCSI_ITT_ALL_ONES (0xffffffff)
#define ISCSI_TTT_ALL_ONES (0xffffffff)
@@ -173,19 +169,6 @@ struct iscsi_async_msg_hdr {
__le32 reserved7;
};
struct iscsi_sge {
struct regpair sge_addr;
__le16 sge_len;
__le16 reserved0;
__le32 reserved1;
};
struct iscsi_cached_sge_ctx {
struct iscsi_sge sge;
struct regpair reserved;
__le32 dsgl_curr_offset[2];
};
struct iscsi_cmd_hdr {
__le16 reserved1;
u8 flags_attr;
@@ -229,8 +212,13 @@ struct iscsi_common_hdr {
#define ISCSI_COMMON_HDR_DATA_SEG_LEN_SHIFT 0
#define ISCSI_COMMON_HDR_TOTAL_AHS_LEN_MASK 0xFF
#define ISCSI_COMMON_HDR_TOTAL_AHS_LEN_SHIFT 24
__le32 lun_reserved[4];
__le32 data[6];
struct regpair lun_reserved;
__le32 itt;
__le32 ttt;
__le32 cmdstat_sn;
__le32 exp_statcmd_sn;
__le32 max_cmd_sn;
__le32 data[3];
};
struct iscsi_conn_offload_params {
@@ -246,8 +234,10 @@ struct iscsi_conn_offload_params {
#define ISCSI_CONN_OFFLOAD_PARAMS_TCP_ON_CHIP_1B_SHIFT 0
#define ISCSI_CONN_OFFLOAD_PARAMS_TARGET_MODE_MASK 0x1
#define ISCSI_CONN_OFFLOAD_PARAMS_TARGET_MODE_SHIFT 1
#define ISCSI_CONN_OFFLOAD_PARAMS_RESERVED1_MASK 0x3F
#define ISCSI_CONN_OFFLOAD_PARAMS_RESERVED1_SHIFT 2
#define ISCSI_CONN_OFFLOAD_PARAMS_RESTRICTED_MODE_MASK 0x1
#define ISCSI_CONN_OFFLOAD_PARAMS_RESTRICTED_MODE_SHIFT 2
#define ISCSI_CONN_OFFLOAD_PARAMS_RESERVED1_MASK 0x1F
#define ISCSI_CONN_OFFLOAD_PARAMS_RESERVED1_SHIFT 3
u8 pbl_page_size_log;
u8 pbe_page_size_log;
u8 default_cq;
@@ -278,8 +268,12 @@ struct iscsi_conn_update_ramrod_params {
#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_INITIAL_R2T_SHIFT 2
#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_IMMEDIATE_DATA_MASK 0x1
#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_IMMEDIATE_DATA_SHIFT 3
#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_RESERVED1_MASK 0xF
#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_RESERVED1_SHIFT 4
#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_DIF_BLOCK_SIZE_MASK 0x1
#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_DIF_BLOCK_SIZE_SHIFT 4
#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_DIF_ON_HOST_EN_MASK 0x1
#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_DIF_ON_HOST_EN_SHIFT 5
#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_RESERVED1_MASK 0x3
#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_RESERVED1_SHIFT 6
u8 reserved0[3];
__le32 max_seq_size;
__le32 max_send_pdu_length;
@@ -312,7 +306,7 @@ struct iscsi_ext_cdb_cmd_hdr {
__le32 expected_transfer_length;
__le32 cmd_sn;
__le32 exp_stat_sn;
struct iscsi_sge cdb_sge;
struct scsi_sge cdb_sge;
};
struct iscsi_login_req_hdr {
@@ -519,8 +513,8 @@ struct iscsi_logout_response_hdr {
__le32 exp_cmd_sn;
__le32 max_cmd_sn;
__le32 reserved4;
__le16 time2retain;
__le16 time2wait;
__le16 time_2_retain;
__le16 time_2_wait;
__le32 reserved5[1];
};
@@ -602,7 +596,7 @@ struct iscsi_tmf_response_hdr {
#define ISCSI_TMF_RESPONSE_HDR_TOTAL_AHS_LEN_SHIFT 24
struct regpair reserved0;
__le32 itt;
__le32 rtt;
__le32 reserved1;
__le32 stat_sn;
__le32 exp_cmd_sn;
__le32 max_cmd_sn;
@@ -641,7 +635,7 @@ struct iscsi_reject_hdr {
#define ISCSI_REJECT_HDR_TOTAL_AHS_LEN_MASK 0xFF
#define ISCSI_REJECT_HDR_TOTAL_AHS_LEN_SHIFT 24
struct regpair reserved0;
__le32 reserved1;
__le32 all_ones;
__le32 reserved2;
__le32 stat_sn;
__le32 exp_cmd_sn;
@@ -688,7 +682,9 @@ struct iscsi_cqe_solicited {
__le16 itid;
u8 task_type;
u8 fw_dbg_field;
__le32 reserved1[2];
u8 caused_conn_err;
u8 reserved0[3];
__le32 reserved1[1];
union iscsi_task_hdr iscsi_hdr;
};
@@ -727,35 +723,6 @@ enum iscsi_cqe_unsolicited_type {
MAX_ISCSI_CQE_UNSOLICITED_TYPE
};
struct iscsi_virt_sgl_ctx {
struct regpair sgl_base;
struct regpair dsgl_base;
__le32 sgl_initial_offset;
__le32 dsgl_initial_offset;
__le32 dsgl_curr_offset[2];
};
struct iscsi_sgl_var_params {
u8 sgl_ptr;
u8 dsgl_ptr;
__le16 sge_offset;
__le16 dsge_offset;
};
struct iscsi_phys_sgl_ctx {
struct regpair sgl_base;
struct regpair dsgl_base;
u8 sgl_size;
u8 dsgl_size;
__le16 reserved;
struct iscsi_sgl_var_params var_params[2];
};
union iscsi_data_desc_ctx {
struct iscsi_virt_sgl_ctx virt_sgl;
struct iscsi_phys_sgl_ctx phys_sgl;
struct iscsi_cached_sge_ctx cached_sge;
};
struct iscsi_debug_modes {
u8 flags;
@@ -771,8 +738,10 @@ struct iscsi_debug_modes {
#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_REJECT_OR_ASYNC_SHIFT 4
#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_NOP_MASK 0x1
#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_NOP_SHIFT 5
#define ISCSI_DEBUG_MODES_RESERVED0_MASK 0x3
#define ISCSI_DEBUG_MODES_RESERVED0_SHIFT 6
#define ISCSI_DEBUG_MODES_ASSERT_IF_DATA_DIGEST_ERROR_MASK 0x1
#define ISCSI_DEBUG_MODES_ASSERT_IF_DATA_DIGEST_ERROR_SHIFT 6
#define ISCSI_DEBUG_MODES_ASSERT_IF_DIF_ERROR_MASK 0x1
#define ISCSI_DEBUG_MODES_ASSERT_IF_DIF_ERROR_SHIFT 7
};
struct iscsi_dif_flags {
@@ -806,7 +775,6 @@ enum iscsi_eqe_opcode {
ISCSI_EVENT_TYPE_ASYN_FIN_WAIT2,
ISCSI_EVENT_TYPE_ISCSI_CONN_ERROR,
ISCSI_EVENT_TYPE_TCP_CONN_ERROR,
ISCSI_EVENT_TYPE_ASYN_DELETE_OOO_ISLES,
MAX_ISCSI_EQE_OPCODE
};
@@ -856,31 +824,11 @@ enum iscsi_error_types {
ISCSI_CONN_ERROR_PROTOCOL_ERR_DIF_TX,
ISCSI_CONN_ERROR_SENSE_DATA_LENGTH,
ISCSI_CONN_ERROR_DATA_PLACEMENT_ERROR,
ISCSI_CONN_ERROR_INVALID_ITT,
ISCSI_ERROR_UNKNOWN,
MAX_ISCSI_ERROR_TYPES
};
struct iscsi_mflags {
u8 mflags;
#define ISCSI_MFLAGS_SLOW_IO_MASK 0x1
#define ISCSI_MFLAGS_SLOW_IO_SHIFT 0
#define ISCSI_MFLAGS_SINGLE_SGE_MASK 0x1
#define ISCSI_MFLAGS_SINGLE_SGE_SHIFT 1
#define ISCSI_MFLAGS_RESERVED_MASK 0x3F
#define ISCSI_MFLAGS_RESERVED_SHIFT 2
};
struct iscsi_sgl {
struct regpair sgl_addr;
__le16 updated_sge_size;
__le16 updated_sge_offset;
__le32 byte_offset;
};
union iscsi_mstorm_sgl {
struct iscsi_sgl sgl_struct;
struct iscsi_sge single_sge;
};
enum iscsi_ramrod_cmd_id {
ISCSI_RAMROD_CMD_ID_UNUSED = 0,
@@ -896,10 +844,10 @@ enum iscsi_ramrod_cmd_id {
struct iscsi_reg1 {
__le32 reg1_map;
#define ISCSI_REG1_NUM_FAST_SGES_MASK 0x7
#define ISCSI_REG1_NUM_FAST_SGES_SHIFT 0
#define ISCSI_REG1_RESERVED1_MASK 0x1FFFFFFF
#define ISCSI_REG1_RESERVED1_SHIFT 3
#define ISCSI_REG1_NUM_SGES_MASK 0xF
#define ISCSI_REG1_NUM_SGES_SHIFT 0
#define ISCSI_REG1_RESERVED1_MASK 0xFFFFFFF
#define ISCSI_REG1_RESERVED1_SHIFT 4
};
union iscsi_seq_num {
@@ -967,22 +915,33 @@ struct iscsi_spe_func_init {
};
struct ystorm_iscsi_task_state {
union iscsi_data_desc_ctx sgl_ctx_union;
__le32 buffer_offset[2];
__le16 bytes_nxt_dif;
__le16 rxmit_bytes_nxt_dif;
union iscsi_seq_num seq_num_union;
u8 dif_bytes_leftover;
u8 rxmit_dif_bytes_leftover;
__le16 reuse_count;
struct iscsi_dif_flags dif_flags;
u8 local_comp;
struct scsi_cached_sges data_desc;
struct scsi_sgl_params sgl_params;
__le32 exp_r2t_sn;
__le32 sgl_offset[2];
__le32 buffer_offset;
union iscsi_seq_num seq_num;
struct iscsi_dif_flags dif_flags;
u8 flags;
#define YSTORM_ISCSI_TASK_STATE_LOCAL_COMP_MASK 0x1
#define YSTORM_ISCSI_TASK_STATE_LOCAL_COMP_SHIFT 0
#define YSTORM_ISCSI_TASK_STATE_SLOW_IO_MASK 0x1
#define YSTORM_ISCSI_TASK_STATE_SLOW_IO_SHIFT 1
#define YSTORM_ISCSI_TASK_STATE_RESERVED0_MASK 0x3F
#define YSTORM_ISCSI_TASK_STATE_RESERVED0_SHIFT 2
};
struct ystorm_iscsi_task_rxmit_opt {
__le32 fast_rxmit_sge_offset;
__le32 scan_start_buffer_offset;
__le32 fast_rxmit_buffer_offset;
u8 scan_start_sgl_index;
u8 fast_rxmit_sgl_index;
__le16 reserved;
};
struct ystorm_iscsi_task_st_ctx {
struct ystorm_iscsi_task_state state;
struct ystorm_iscsi_task_rxmit_opt rxmit_opt;
union iscsi_task_hdr pdu_hdr;
};
@@ -1152,25 +1111,16 @@ struct ustorm_iscsi_task_ag_ctx {
};
struct mstorm_iscsi_task_st_ctx {
union iscsi_mstorm_sgl sgl_union;
struct iscsi_dif_flags dif_flags;
struct iscsi_mflags flags;
u8 sgl_size;
u8 host_sge_index;
__le16 dix_cur_sge_offset;
__le16 dix_cur_sge_size;
__le32 data_offset_rtid;
u8 dif_offset;
u8 dix_sgl_size;
u8 dix_sge_index;
u8 task_type;
struct regpair sense_db;
struct regpair dix_sgl_cur_sge;
struct scsi_cached_sges data_desc;
struct scsi_sgl_params sgl_params;
__le32 rem_task_size;
__le16 reuse_count;
__le16 dif_data_residue;
u8 reserved0[4];
__le32 reserved1[1];
__le32 data_buffer_offset;
u8 task_type;
struct iscsi_dif_flags dif_flags;
u8 reserved0[2];
struct regpair sense_db;
__le32 expected_itt;
__le32 reserved1;
};
struct ustorm_iscsi_task_st_ctx {
@@ -1184,7 +1134,7 @@ struct ustorm_iscsi_task_st_ctx {
#define USTORM_ISCSI_TASK_ST_CTX_AHS_EXIST_SHIFT 0
#define USTORM_ISCSI_TASK_ST_CTX_RESERVED1_MASK 0x7F
#define USTORM_ISCSI_TASK_ST_CTX_RESERVED1_SHIFT 1
u8 reserved2;
struct iscsi_dif_flags dif_flags;
__le16 reserved3;
__le32 reserved4;
__le32 reserved5;
@@ -1207,10 +1157,10 @@ struct ustorm_iscsi_task_st_ctx {
#define USTORM_ISCSI_TASK_ST_CTX_LOCAL_COMP_SHIFT 2
#define USTORM_ISCSI_TASK_ST_CTX_Q0_R2TQE_WRITE_MASK 0x1
#define USTORM_ISCSI_TASK_ST_CTX_Q0_R2TQE_WRITE_SHIFT 3
#define USTORM_ISCSI_TASK_ST_CTX_TOTALDATAACKED_DONE_MASK 0x1
#define USTORM_ISCSI_TASK_ST_CTX_TOTALDATAACKED_DONE_SHIFT 4
#define USTORM_ISCSI_TASK_ST_CTX_HQSCANNED_DONE_MASK 0x1
#define USTORM_ISCSI_TASK_ST_CTX_HQSCANNED_DONE_SHIFT 5
#define USTORM_ISCSI_TASK_ST_CTX_TOTAL_DATA_ACKED_DONE_MASK 0x1
#define USTORM_ISCSI_TASK_ST_CTX_TOTAL_DATA_ACKED_DONE_SHIFT 4
#define USTORM_ISCSI_TASK_ST_CTX_HQ_SCANNED_DONE_MASK 0x1
#define USTORM_ISCSI_TASK_ST_CTX_HQ_SCANNED_DONE_SHIFT 5
#define USTORM_ISCSI_TASK_ST_CTX_R2T2RECV_DONE_MASK 0x1
#define USTORM_ISCSI_TASK_ST_CTX_R2T2RECV_DONE_SHIFT 6
#define USTORM_ISCSI_TASK_ST_CTX_RESERVED0_MASK 0x1
@@ -1220,7 +1170,6 @@ struct ustorm_iscsi_task_st_ctx {
struct iscsi_task_context {
struct ystorm_iscsi_task_st_ctx ystorm_st_context;
struct regpair ystorm_st_padding[2];
struct ystorm_iscsi_task_ag_ctx ystorm_ag_context;
struct regpair ystorm_ag_padding[2];
struct tdif_task_context tdif_context;
@@ -1272,32 +1221,22 @@ struct iscsi_uhqe {
#define ISCSI_UHQE_TASK_ID_LO_SHIFT 24
};
struct iscsi_wqe_field {
__le32 contlen_cdbsize_field;
#define ISCSI_WQE_FIELD_CONT_LEN_MASK 0xFFFFFF
#define ISCSI_WQE_FIELD_CONT_LEN_SHIFT 0
#define ISCSI_WQE_FIELD_CDB_SIZE_MASK 0xFF
#define ISCSI_WQE_FIELD_CDB_SIZE_SHIFT 24
};
union iscsi_wqe_field_union {
struct iscsi_wqe_field cont_field;
__le32 prev_tid;
};
struct iscsi_wqe {
__le16 task_id;
u8 flags;
#define ISCSI_WQE_WQE_TYPE_MASK 0x7
#define ISCSI_WQE_WQE_TYPE_SHIFT 0
#define ISCSI_WQE_NUM_FAST_SGES_MASK 0x7
#define ISCSI_WQE_NUM_FAST_SGES_SHIFT 3
#define ISCSI_WQE_PTU_INVALIDATE_MASK 0x1
#define ISCSI_WQE_PTU_INVALIDATE_SHIFT 6
#define ISCSI_WQE_NUM_SGES_MASK 0xF
#define ISCSI_WQE_NUM_SGES_SHIFT 3
#define ISCSI_WQE_RESPONSE_MASK 0x1
#define ISCSI_WQE_RESPONSE_SHIFT 7
struct iscsi_dif_flags prot_flags;
union iscsi_wqe_field_union cont_prevtid_union;
__le32 contlen_cdbsize;
#define ISCSI_WQE_CONT_LEN_MASK 0xFFFFFF
#define ISCSI_WQE_CONT_LEN_SHIFT 0
#define ISCSI_WQE_CDB_SIZE_MASK 0xFF
#define ISCSI_WQE_CDB_SIZE_SHIFT 24
};
enum iscsi_wqe_type {
@@ -1318,17 +1257,15 @@ struct iscsi_xhqe {
u8 total_ahs_length;
u8 opcode;
u8 flags;
#define ISCSI_XHQE_NUM_FAST_SGES_MASK 0x7
#define ISCSI_XHQE_NUM_FAST_SGES_SHIFT 0
#define ISCSI_XHQE_FINAL_MASK 0x1
#define ISCSI_XHQE_FINAL_SHIFT 3
#define ISCSI_XHQE_SUPER_IO_MASK 0x1
#define ISCSI_XHQE_SUPER_IO_SHIFT 4
#define ISCSI_XHQE_STATUS_BIT_MASK 0x1
#define ISCSI_XHQE_STATUS_BIT_SHIFT 5
#define ISCSI_XHQE_RESERVED_MASK 0x3
#define ISCSI_XHQE_RESERVED_SHIFT 6
union iscsi_seq_num seq_num_union;
#define ISCSI_XHQE_FINAL_MASK 0x1
#define ISCSI_XHQE_FINAL_SHIFT 0
#define ISCSI_XHQE_STATUS_BIT_MASK 0x1
#define ISCSI_XHQE_STATUS_BIT_SHIFT 1
#define ISCSI_XHQE_NUM_SGES_MASK 0xF
#define ISCSI_XHQE_NUM_SGES_SHIFT 2
#define ISCSI_XHQE_RESERVED0_MASK 0x3
#define ISCSI_XHQE_RESERVED0_SHIFT 6
union iscsi_seq_num seq_num;
__le16 reserved1;
};

17
include/linux/qed/roce_common.h
View File

@@ -38,4 +38,21 @@
#define ROCE_MAX_QPS (32 * 1024)
enum roce_async_events_type {
ROCE_ASYNC_EVENT_NONE = 0,
ROCE_ASYNC_EVENT_COMM_EST = 1,
ROCE_ASYNC_EVENT_SQ_DRAINED,
ROCE_ASYNC_EVENT_SRQ_LIMIT,
ROCE_ASYNC_EVENT_LAST_WQE_REACHED,
ROCE_ASYNC_EVENT_CQ_ERR,
ROCE_ASYNC_EVENT_LOCAL_INVALID_REQUEST_ERR,
ROCE_ASYNC_EVENT_LOCAL_CATASTROPHIC_ERR,
ROCE_ASYNC_EVENT_LOCAL_ACCESS_ERR,
ROCE_ASYNC_EVENT_QP_CATASTROPHIC_ERR,
ROCE_ASYNC_EVENT_CQ_OVERFLOW_ERR,
ROCE_ASYNC_EVENT_SRQ_EMPTY,
ROCE_ASYNC_EVENT_DESTROY_QP_DONE,
MAX_ROCE_ASYNC_EVENTS_TYPE
};
#endif /* __ROCE_COMMON__ */

30
include/linux/qed/storage_common.h
View File

@@ -40,6 +40,8 @@
#define BDQ_ID_IMM_DATA (1)
#define BDQ_NUM_IDS (2)
#define SCSI_NUM_SGES_SLOW_SGL_THR 8
#define BDQ_MAX_EXTERNAL_RING_SIZE (1 << 15)
struct scsi_bd {
@@ -52,6 +54,16 @@ struct scsi_bdq_ram_drv_data {
__le16 reserved0[3];
};
struct scsi_sge {
struct regpair sge_addr;
__le32 sge_len;
__le32 reserved;
};
struct scsi_cached_sges {
struct scsi_sge sge[4];
};
struct scsi_drv_cmdq {
__le16 cmdq_cons;
__le16 reserved0;
@@ -99,11 +111,19 @@ struct scsi_ram_per_bdq_resource_drv_data {
struct scsi_bdq_ram_drv_data drv_data_per_bdq_id[BDQ_NUM_IDS];
};
struct scsi_sge {
struct regpair sge_addr;
__le16 sge_len;
__le16 reserved0;
__le32 reserved1;
enum scsi_sgl_mode {
SCSI_TX_SLOW_SGL,
SCSI_FAST_SGL,
MAX_SCSI_SGL_MODE
};
struct scsi_sgl_params {
struct regpair sgl_addr;
__le32 sgl_total_length;
__le32 sge_offset;
__le16 sgl_num_sges;
u8 sgl_index;
u8 reserved;
};
struct scsi_terminate_extra_params {

1
include/linux/qed/tcp_common.h
View File

@@ -173,6 +173,7 @@ enum tcp_seg_placement_event {
TCP_EVENT_ADD_ISLE_RIGHT,
TCP_EVENT_ADD_ISLE_LEFT,
TCP_EVENT_JOIN,
TCP_EVENT_DELETE_ISLES,
TCP_EVENT_NOP,
MAX_TCP_SEG_PLACEMENT_EVENT
};