Merge tag 'media/v4.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media
Pull media updates from Mauro Carvalho Chehab: - new Mediatek drivers: mtk-mdp and mtk-vcodec - some additions at the media documentation - the CEC core and drivers were promoted from staging to mainstream - some cleanups at the DVB core - the LIRC serial driver got promoted from staging to mainstream - added a driver for Renesas R-Car FDP1 driver - add DVBv5 statistics support to mn88473 driver - several fixes related to printk continuation lines - add support for HSV encoding formats - lots of other cleanups, fixups and driver improvements. * tag 'media/v4.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media: (496 commits) [media] v4l: tvp5150: Add missing break in set control handler [media] v4l: tvp5150: Don't inline the tvp5150_selmux() function [media] v4l: tvp5150: Compile tvp5150_link_setup out if !CONFIG_MEDIA_CONTROLLER [media] em28xx: don't store usb_device at struct em28xx [media] em28xx: use usb_interface for dev_foo() calls [media] em28xx: don't change the device's name [media] mn88472: fix chip id check on probe [media] mn88473: fix chip id check on probe [media] lirc: fix error paths in lirc_cdev_add() [media] s5p-mfc: Add support for MFC v8 available in Exynos 5433 SoCs [media] s5p-mfc: Rework clock handling [media] s5p-mfc: Don't keep clock prepared all the time [media] s5p-mfc: Kill all IS_ERR_OR_NULL in clocks management code [media] s5p-mfc: Remove dead conditional code [media] s5p-mfc: Ensure that clock is disabled before turning power off [media] s5p-mfc: Remove special clock rate management [media] s5p-mfc: Use printk_ratelimited for reporting ioctl errors [media] s5p-mfc: Set DMA_ATTR_ALLOC_SINGLE_PAGES [media] vivid: Set color_enc on HSV formats [media] v4l2-tpg: Init hv_enc field with a valid value ...
This commit is contained in:
Linus Torvalds
@@ -41,6 +41,14 @@
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dpi0 = &dpi0;
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dsi0 = &dsi0;
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dsi1 = &dsi1;
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mdp_rdma0 = &mdp_rdma0;
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mdp_rdma1 = &mdp_rdma1;
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mdp_rsz0 = &mdp_rsz0;
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mdp_rsz1 = &mdp_rsz1;
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mdp_rsz2 = &mdp_rsz2;
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mdp_wdma0 = &mdp_wdma0;
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mdp_wrot0 = &mdp_wrot0;
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mdp_wrot1 = &mdp_wrot1;
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};
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cpus {
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@@ -773,6 +781,82 @@
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#clock-cells = <1>;
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};
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mdp {
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compatible = "mediatek,mt8173-mdp";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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mediatek,vpu = <&vpu>;
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mdp_rdma0: rdma@14001000 {
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compatible = "mediatek,mt8173-mdp-rdma";
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reg = <0 0x14001000 0 0x1000>;
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clocks = <&mmsys CLK_MM_MDP_RDMA0>,
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<&mmsys CLK_MM_MUTEX_32K>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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iommus = <&iommu M4U_PORT_MDP_RDMA0>;
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mediatek,larb = <&larb0>;
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};
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mdp_rdma1: rdma@14002000 {
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compatible = "mediatek,mt8173-mdp-rdma";
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reg = <0 0x14002000 0 0x1000>;
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clocks = <&mmsys CLK_MM_MDP_RDMA1>,
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<&mmsys CLK_MM_MUTEX_32K>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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iommus = <&iommu M4U_PORT_MDP_RDMA1>;
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mediatek,larb = <&larb4>;
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};
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mdp_rsz0: rsz@14003000 {
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compatible = "mediatek,mt8173-mdp-rsz";
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reg = <0 0x14003000 0 0x1000>;
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clocks = <&mmsys CLK_MM_MDP_RSZ0>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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};
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mdp_rsz1: rsz@14004000 {
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compatible = "mediatek,mt8173-mdp-rsz";
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reg = <0 0x14004000 0 0x1000>;
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clocks = <&mmsys CLK_MM_MDP_RSZ1>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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};
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mdp_rsz2: rsz@14005000 {
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compatible = "mediatek,mt8173-mdp-rsz";
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reg = <0 0x14005000 0 0x1000>;
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clocks = <&mmsys CLK_MM_MDP_RSZ2>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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};
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mdp_wdma0: wdma@14006000 {
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compatible = "mediatek,mt8173-mdp-wdma";
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reg = <0 0x14006000 0 0x1000>;
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clocks = <&mmsys CLK_MM_MDP_WDMA>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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iommus = <&iommu M4U_PORT_MDP_WDMA>;
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mediatek,larb = <&larb0>;
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};
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mdp_wrot0: wrot@14007000 {
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compatible = "mediatek,mt8173-mdp-wrot";
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reg = <0 0x14007000 0 0x1000>;
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clocks = <&mmsys CLK_MM_MDP_WROT0>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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iommus = <&iommu M4U_PORT_MDP_WROT0>;
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mediatek,larb = <&larb0>;
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};
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mdp_wrot1: wrot@14008000 {
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compatible = "mediatek,mt8173-mdp-wrot";
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reg = <0 0x14008000 0 0x1000>;
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clocks = <&mmsys CLK_MM_MDP_WROT1>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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iommus = <&iommu M4U_PORT_MDP_WROT1>;
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mediatek,larb = <&larb4>;
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};
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};
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ovl0: ovl@1400c000 {
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compatible = "mediatek,mt8173-disp-ovl";
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reg = <0 0x1400c000 0 0x1000>;
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@@ -1069,6 +1153,50 @@
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#clock-cells = <1>;
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};
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vcodec_dec: vcodec@16000000 {
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compatible = "mediatek,mt8173-vcodec-dec";
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reg = <0 0x16000000 0 0x100>, /* VDEC_SYS */
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<0 0x16020000 0 0x1000>, /* VDEC_MISC */
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<0 0x16021000 0 0x800>, /* VDEC_LD */
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<0 0x16021800 0 0x800>, /* VDEC_TOP */
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<0 0x16022000 0 0x1000>, /* VDEC_CM */
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<0 0x16023000 0 0x1000>, /* VDEC_AD */
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<0 0x16024000 0 0x1000>, /* VDEC_AV */
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<0 0x16025000 0 0x1000>, /* VDEC_PP */
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<0 0x16026800 0 0x800>, /* VDEC_HWD */
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<0 0x16027000 0 0x800>, /* VDEC_HWQ */
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<0 0x16027800 0 0x800>, /* VDEC_HWB */
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<0 0x16028400 0 0x400>; /* VDEC_HWG */
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interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
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mediatek,larb = <&larb1>;
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iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
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<&iommu M4U_PORT_HW_VDEC_PP_EXT>,
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<&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
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<&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
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<&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
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<&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
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<&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
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<&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
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mediatek,vpu = <&vpu>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
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clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
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<&topckgen CLK_TOP_UNIVPLL_D2>,
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<&topckgen CLK_TOP_CCI400_SEL>,
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<&topckgen CLK_TOP_VDEC_SEL>,
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<&topckgen CLK_TOP_VCODECPLL>,
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<&apmixedsys CLK_APMIXED_VENCPLL>,
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<&topckgen CLK_TOP_VENC_LT_SEL>,
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<&topckgen CLK_TOP_VCODECPLL_370P5>;
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clock-names = "vcodecpll",
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"univpll_d2",
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"clk_cci400_sel",
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"vdec_sel",
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"vdecpll",
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"vencpll",
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"venc_lt_sel",
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"vdec_bus_clk_src";
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};
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larb1: larb@16010000 {
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compatible = "mediatek,mt8173-smi-larb";
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reg = <0 0x16010000 0 0x1000>;
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