xiaomi-sm8450/android_kernel_xiaomi_sm8450
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

powerpc: Load Monitor Register Support

Browse Source 
This enables new registers, LMRR and LMSER, that can trigger an EBB in
userspace code when a monitored load (via the new ldmx instruction)
loads memory from a monitored space. This facility is controlled by a
new FSCR bit, LM.

This patch disables the FSCR LM control bit on task init and enables
that bit when a load monitor facility unavailable exception is taken
for using it. On context switch, this bit is then used to determine
whether the two relevant registers are saved and restored. This is
done lazily for performance reasons.

Signed-off-by: Jack Miller <jack@codezen.org>
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Jack Miller
2016-06-09 12:31:09 +10:00
committed by Michael Ellerman
parent b57bd2de8c
commit bd3ea317fd
4 changed files with 34 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
arch/powerpc/kernel/traps.c
View File

@@ -1377,6 +1377,7 @@ void facility_unavailable_exception(struct pt_regs *regs)
[FSCR_TM_LG] = "TM",
[FSCR_EBB_LG] = "EBB",
[FSCR_TAR_LG] = "TAR",
[FSCR_LM_LG] = "LM",
};
char *facility = "unknown";
u64 value;
@@ -1434,6 +1435,14 @@ void facility_unavailable_exception(struct pt_regs *regs)
emulate_single_step(regs);
}
return;
} else if ((status == FSCR_LM_LG) && cpu_has_feature(CPU_FTR_ARCH_300)) {
/*
* This process has touched LM, so turn it on forever
* for this process
*/
current->thread.fscr |= FSCR_LM;
mtspr(SPRN_FSCR, current->thread.fscr);
return;
}
if ((status < ARRAY_SIZE(facility_strings)) &&