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powerpc/64: Fix naming of cache block vs. cache line

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In a number of places we called "cache line size" what is actually
the cache block size, which in the powerpc architecture, means the
effective size to use with cache management instructions (it can
be different from the actual cache line size).

We fix the naming across the board and properly retrieve both
pieces of information when available in the device-tree.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Benjamin Herrenschmidt
2017-01-08 17:31:45 -06:00
committed by Michael Ellerman
parent f9e473f1aa
commit bd067f83b0
9 changed files with 75 additions and 68 deletions
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4
arch/powerpc/include/asm/page_64.h
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@@ -47,14 +47,14 @@ static inline void clear_page(void *addr)
unsigned long iterations;
unsigned long onex, twox, fourx, eightx;
iterations = ppc64_caches.dlines_per_page / 8;
iterations = ppc64_caches.dblocks_per_page / 8;
/*
* Some verisions of gcc use multiply instructions to
* calculate the offsets so lets give it a hand to
* do better.
*/
onex = ppc64_caches.dline_size;
onex = ppc64_caches.dblock_size;
twox = onex << 1;
fourx = onex << 2;
eightx = onex << 3;