xiaomi-sm8450/android_kernel_xiaomi_sm8450
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

ARCv2: MMUv4: support aliasing icache config

Browse Source 
This is also default for AXS103 release

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
This commit is contained in:
Vineet Gupta
2015-06-04 14:39:15 +05:30
parent d1f317d825
commit bcc4d65abe
2 changed files with 14 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arc/include/asm/cache.h
View File

@@ -60,7 +60,7 @@ extern void read_decode_cache_bcr(void);
#define ARC_REG_IC_IVIC 0x10
#define ARC_REG_IC_CTRL 0x11
#define ARC_REG_IC_IVIL 0x19
#if defined(CONFIG_ARC_MMU_V3)
#if defined(CONFIG_ARC_MMU_V3) || defined(CONFIG_ARC_MMU_V4)
#define ARC_REG_IC_PTAG 0x1E
#endif
@@ -74,9 +74,7 @@ extern void read_decode_cache_bcr(void);
#define ARC_REG_DC_IVDL 0x4A
#define ARC_REG_DC_FLSH 0x4B
#define ARC_REG_DC_FLDL 0x4C
#if defined(CONFIG_ARC_MMU_V3)
#define ARC_REG_DC_PTAG 0x5C
#endif
/* Bit val in DC_CTRL */
#define DC_CTRL_INV_MODE_FLUSH 0x40