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scsi: lpfc: Adjust default value of lpfc_nvmet_mrq

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The current default for async hw receive queues is 1, which presents
issues under heavy load as number of queues influence the available
async receive buffer limits.

Raise the default to the either the current hw limit (16) or the number
of hw qs configured (io channel value).

Revise the attribute definition for mrq to better reflect what we do for
hw queues. E.g. 0 means default to optimal (# of cpus), non-zero
specifies a specific limit. Before this change, mrq=0 meant target mode
was disabled. As 0 now has a different meaning, rework the if tests to
use the better nvmet_support check.

Signed-off-by: Dick Kennedy <dick.kennedy@broadcom.com>
Signed-off-by: James Smart <james.smart@broadcom.com>
Reviewed-by: Hannes Reinecke <hare@suse.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
James Smart
2017-11-20 16:00:36 -08:00
committed by Martin K. Petersen
parent 07d494f753
commit bcb24f6577
4 changed files with 42 additions and 22 deletions
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47
drivers/scsi/lpfc/lpfc_init.c
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@@ -7933,8 +7933,12 @@ lpfc_sli4_queue_verify(struct lpfc_hba *phba)
phba->cfg_fcp_io_channel = io_channel;
if (phba->cfg_nvme_io_channel > io_channel)
phba->cfg_nvme_io_channel = io_channel;
if (phba->cfg_nvme_io_channel < phba->cfg_nvmet_mrq)
phba->cfg_nvmet_mrq = phba->cfg_nvme_io_channel;
if (phba->nvmet_support) {
if (phba->cfg_nvme_io_channel < phba->cfg_nvmet_mrq)
phba->cfg_nvmet_mrq = phba->cfg_nvme_io_channel;
}
if (phba->cfg_nvmet_mrq > LPFC_NVMET_MRQ_MAX)
phba->cfg_nvmet_mrq = LPFC_NVMET_MRQ_MAX;
lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
"2574 IO channels: irqs %d fcp %d nvme %d MRQ: %d\n",
@@ -8448,13 +8452,15 @@ lpfc_sli4_queue_destroy(struct lpfc_hba *phba)
/* Release NVME CQ mapping array */
lpfc_sli4_release_queue_map(&phba->sli4_hba.nvme_cq_map);
lpfc_sli4_release_queues(&phba->sli4_hba.nvmet_cqset,
phba->cfg_nvmet_mrq);
if (phba->nvmet_support) {
lpfc_sli4_release_queues(&phba->sli4_hba.nvmet_cqset,
phba->cfg_nvmet_mrq);
lpfc_sli4_release_queues(&phba->sli4_hba.nvmet_mrq_hdr,
phba->cfg_nvmet_mrq);
lpfc_sli4_release_queues(&phba->sli4_hba.nvmet_mrq_data,
phba->cfg_nvmet_mrq);
lpfc_sli4_release_queues(&phba->sli4_hba.nvmet_mrq_hdr,
phba->cfg_nvmet_mrq);
lpfc_sli4_release_queues(&phba->sli4_hba.nvmet_mrq_data,
phba->cfg_nvmet_mrq);
}
/* Release mailbox command work queue */
__lpfc_sli4_release_queue(&phba->sli4_hba.mbx_wq);
@@ -9009,19 +9015,22 @@ lpfc_sli4_queue_unset(struct lpfc_hba *phba)
for (qidx = 0; qidx < phba->cfg_nvme_io_channel; qidx++)
lpfc_cq_destroy(phba, phba->sli4_hba.nvme_cq[qidx]);
/* Unset NVMET MRQ queue */
if (phba->sli4_hba.nvmet_mrq_hdr) {
for (qidx = 0; qidx < phba->cfg_nvmet_mrq; qidx++)
lpfc_rq_destroy(phba,
if (phba->nvmet_support) {
/* Unset NVMET MRQ queue */
if (phba->sli4_hba.nvmet_mrq_hdr) {
for (qidx = 0; qidx < phba->cfg_nvmet_mrq; qidx++)
lpfc_rq_destroy(
phba,
phba->sli4_hba.nvmet_mrq_hdr[qidx],
phba->sli4_hba.nvmet_mrq_data[qidx]);
}
}
/* Unset NVMET CQ Set complete queue */
if (phba->sli4_hba.nvmet_cqset) {
for (qidx = 0; qidx < phba->cfg_nvmet_mrq; qidx++)
lpfc_cq_destroy(phba,
phba->sli4_hba.nvmet_cqset[qidx]);
/* Unset NVMET CQ Set complete queue */
if (phba->sli4_hba.nvmet_cqset) {
for (qidx = 0; qidx < phba->cfg_nvmet_mrq; qidx++)
lpfc_cq_destroy(
phba, phba->sli4_hba.nvmet_cqset[qidx]);
}
}
/* Unset FCP response complete queue */
@@ -10397,7 +10406,7 @@ lpfc_get_sli4_parameters(struct lpfc_hba *phba, LPFC_MBOXQ_t *mboxq)
!phba->nvme_support) {
phba->nvme_support = 0;
phba->nvmet_support = 0;
phba->cfg_nvmet_mrq = 0;
phba->cfg_nvmet_mrq = LPFC_NVMET_MRQ_OFF;
phba->cfg_nvme_io_channel = 0;
phba->io_channel_irqs = phba->cfg_fcp_io_channel;
lpfc_printf_log(phba, KERN_ERR, LOG_INIT | LOG_NVME,