Merge branch 'perf-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull perf updates from Ingo Molnar: "The biggest changes are Intel Nehalem-EX PMU uncore support, uprobes updates/cleanups/fixes from Oleg and diverse tooling updates (mostly fixes) now that Arnaldo is back from vacation." * 'perf-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (40 commits) uprobes: __replace_page() needs munlock_vma_page() uprobes: Rename vma_address() and make it return "unsigned long" uprobes: Fix register_for_each_vma()->vma_address() check uprobes: Introduce vaddr_to_offset(vma, vaddr) uprobes: Teach build_probe_list() to consider the range uprobes: Remove insert_vm_struct()->uprobe_mmap() uprobes: Remove copy_vma()->uprobe_mmap() uprobes: Fix overflow in vma_address()/find_active_uprobe() uprobes: Suppress uprobe_munmap() from mmput() uprobes: Uprobe_mmap/munmap needs list_for_each_entry_safe() uprobes: Clean up and document write_opcode()->lock_page(old_page) uprobes: Kill write_opcode()->lock_page(new_page) uprobes: __replace_page() should not use page_address_in_vma() uprobes: Don't recheck vma/f_mapping in write_opcode() perf/x86: Fix missing struct before structure name perf/x86: Fix format definition of SNB-EP uncore QPI box perf/x86: Make bitfield unsigned perf/x86: Fix LLC-* and node-* events on Intel SandyBridge perf/x86: Add Intel Nehalem-EX uncore support perf/x86: Fix typo in format definition of uncore PCU filter ...
This commit is contained in:
Linus Torvalds
@@ -374,7 +374,7 @@ struct x86_pmu {
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/*
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* Intel DebugStore bits
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*/
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int bts :1,
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unsigned int bts :1,
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bts_active :1,
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pebs :1,
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pebs_active :1,
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@@ -138,6 +138,84 @@ static u64 intel_pmu_event_map(int hw_event)
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return intel_perfmon_event_map[hw_event];
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}
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#define SNB_DMND_DATA_RD (1ULL << 0)
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#define SNB_DMND_RFO (1ULL << 1)
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#define SNB_DMND_IFETCH (1ULL << 2)
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#define SNB_DMND_WB (1ULL << 3)
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#define SNB_PF_DATA_RD (1ULL << 4)
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#define SNB_PF_RFO (1ULL << 5)
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#define SNB_PF_IFETCH (1ULL << 6)
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#define SNB_LLC_DATA_RD (1ULL << 7)
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#define SNB_LLC_RFO (1ULL << 8)
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#define SNB_LLC_IFETCH (1ULL << 9)
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#define SNB_BUS_LOCKS (1ULL << 10)
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#define SNB_STRM_ST (1ULL << 11)
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#define SNB_OTHER (1ULL << 15)
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#define SNB_RESP_ANY (1ULL << 16)
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#define SNB_NO_SUPP (1ULL << 17)
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#define SNB_LLC_HITM (1ULL << 18)
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#define SNB_LLC_HITE (1ULL << 19)
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#define SNB_LLC_HITS (1ULL << 20)
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#define SNB_LLC_HITF (1ULL << 21)
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#define SNB_LOCAL (1ULL << 22)
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#define SNB_REMOTE (0xffULL << 23)
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#define SNB_SNP_NONE (1ULL << 31)
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#define SNB_SNP_NOT_NEEDED (1ULL << 32)
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#define SNB_SNP_MISS (1ULL << 33)
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#define SNB_NO_FWD (1ULL << 34)
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#define SNB_SNP_FWD (1ULL << 35)
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#define SNB_HITM (1ULL << 36)
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#define SNB_NON_DRAM (1ULL << 37)
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#define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
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#define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO)
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#define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
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#define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
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SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
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SNB_HITM)
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#define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
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#define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY)
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#define SNB_L3_ACCESS SNB_RESP_ANY
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#define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM)
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static __initconst const u64 snb_hw_cache_extra_regs
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[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_RESULT_MAX] =
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{
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[ C(LL ) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
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[ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS,
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
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[ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
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[ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
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},
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},
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[ C(NODE) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
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[ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
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[ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
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[ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
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},
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},
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};
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static __initconst const u64 snb_hw_cache_event_ids
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[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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@@ -235,16 +313,16 @@ static __initconst const u64 snb_hw_cache_event_ids
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},
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[ C(NODE) ] = {
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[ C(OP_READ) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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[ C(RESULT_ACCESS) ] = 0x01b7,
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[ C(RESULT_MISS) ] = 0x01b7,
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},
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[ C(OP_WRITE) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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[ C(RESULT_ACCESS) ] = 0x01b7,
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[ C(RESULT_MISS) ] = 0x01b7,
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},
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[ C(OP_PREFETCH) ] = {
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[ C(RESULT_ACCESS) ] = -1,
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[ C(RESULT_MISS) ] = -1,
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[ C(RESULT_ACCESS) ] = 0x01b7,
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[ C(RESULT_MISS) ] = 0x01b7,
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},
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},
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@@ -1964,6 +2042,8 @@ __init int intel_pmu_init(void)
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case 58: /* IvyBridge */
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memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
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sizeof(hw_cache_event_ids));
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memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
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sizeof(hw_cache_extra_regs));
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intel_pmu_lbr_init_snb();
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File diff suppressed because it is too large
Load Diff
@@ -5,8 +5,6 @@
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#include "perf_event.h"
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#define UNCORE_PMU_NAME_LEN 32
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#define UNCORE_BOX_HASH_SIZE 8
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#define UNCORE_PMU_HRTIMER_INTERVAL (60 * NSEC_PER_SEC)
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#define UNCORE_FIXED_EVENT 0xff
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@@ -115,6 +113,10 @@
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SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT | \
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SNBEP_PCU_MSR_PMON_CTL_OCC_EDGE_DET)
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#define SNBEP_QPI_PCI_PMON_RAW_EVENT_MASK \
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(SNBEP_PMON_RAW_EVENT_MASK | \
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SNBEP_PMON_CTL_EV_SEL_EXT)
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/* SNB-EP pci control register */
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#define SNBEP_PCI_PMON_BOX_CTL 0xf4
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#define SNBEP_PCI_PMON_CTL0 0xd8
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@@ -158,6 +160,193 @@
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#define SNBEP_PCU_MSR_CORE_C3_CTR 0x3fc
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#define SNBEP_PCU_MSR_CORE_C6_CTR 0x3fd
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/* NHM-EX event control */
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#define NHMEX_PMON_CTL_EV_SEL_MASK 0x000000ff
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#define NHMEX_PMON_CTL_UMASK_MASK 0x0000ff00
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#define NHMEX_PMON_CTL_EN_BIT0 (1 << 0)
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#define NHMEX_PMON_CTL_EDGE_DET (1 << 18)
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#define NHMEX_PMON_CTL_PMI_EN (1 << 20)
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#define NHMEX_PMON_CTL_EN_BIT22 (1 << 22)
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#define NHMEX_PMON_CTL_INVERT (1 << 23)
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#define NHMEX_PMON_CTL_TRESH_MASK 0xff000000
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#define NHMEX_PMON_RAW_EVENT_MASK (NHMEX_PMON_CTL_EV_SEL_MASK | \
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NHMEX_PMON_CTL_UMASK_MASK | \
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NHMEX_PMON_CTL_EDGE_DET | \
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NHMEX_PMON_CTL_INVERT | \
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NHMEX_PMON_CTL_TRESH_MASK)
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/* NHM-EX Ubox */
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#define NHMEX_U_MSR_PMON_GLOBAL_CTL 0xc00
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#define NHMEX_U_MSR_PMON_CTR 0xc11
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#define NHMEX_U_MSR_PMON_EV_SEL 0xc10
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#define NHMEX_U_PMON_GLOBAL_EN (1 << 0)
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#define NHMEX_U_PMON_GLOBAL_PMI_CORE_SEL 0x0000001e
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#define NHMEX_U_PMON_GLOBAL_EN_ALL (1 << 28)
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#define NHMEX_U_PMON_GLOBAL_RST_ALL (1 << 29)
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#define NHMEX_U_PMON_GLOBAL_FRZ_ALL (1 << 31)
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#define NHMEX_U_PMON_RAW_EVENT_MASK \
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(NHMEX_PMON_CTL_EV_SEL_MASK | \
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NHMEX_PMON_CTL_EDGE_DET)
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/* NHM-EX Cbox */
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#define NHMEX_C0_MSR_PMON_GLOBAL_CTL 0xd00
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#define NHMEX_C0_MSR_PMON_CTR0 0xd11
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#define NHMEX_C0_MSR_PMON_EV_SEL0 0xd10
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#define NHMEX_C_MSR_OFFSET 0x20
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/* NHM-EX Bbox */
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#define NHMEX_B0_MSR_PMON_GLOBAL_CTL 0xc20
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#define NHMEX_B0_MSR_PMON_CTR0 0xc31
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#define NHMEX_B0_MSR_PMON_CTL0 0xc30
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#define NHMEX_B_MSR_OFFSET 0x40
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#define NHMEX_B0_MSR_MATCH 0xe45
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#define NHMEX_B0_MSR_MASK 0xe46
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#define NHMEX_B1_MSR_MATCH 0xe4d
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#define NHMEX_B1_MSR_MASK 0xe4e
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#define NHMEX_B_PMON_CTL_EN (1 << 0)
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#define NHMEX_B_PMON_CTL_EV_SEL_SHIFT 1
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#define NHMEX_B_PMON_CTL_EV_SEL_MASK \
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(0x1f << NHMEX_B_PMON_CTL_EV_SEL_SHIFT)
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#define NHMEX_B_PMON_CTR_SHIFT 6
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#define NHMEX_B_PMON_CTR_MASK \
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(0x3 << NHMEX_B_PMON_CTR_SHIFT)
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#define NHMEX_B_PMON_RAW_EVENT_MASK \
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(NHMEX_B_PMON_CTL_EV_SEL_MASK | \
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NHMEX_B_PMON_CTR_MASK)
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/* NHM-EX Sbox */
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#define NHMEX_S0_MSR_PMON_GLOBAL_CTL 0xc40
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#define NHMEX_S0_MSR_PMON_CTR0 0xc51
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#define NHMEX_S0_MSR_PMON_CTL0 0xc50
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#define NHMEX_S_MSR_OFFSET 0x80
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#define NHMEX_S0_MSR_MM_CFG 0xe48
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#define NHMEX_S0_MSR_MATCH 0xe49
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#define NHMEX_S0_MSR_MASK 0xe4a
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#define NHMEX_S1_MSR_MM_CFG 0xe58
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#define NHMEX_S1_MSR_MATCH 0xe59
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#define NHMEX_S1_MSR_MASK 0xe5a
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#define NHMEX_S_PMON_MM_CFG_EN (0x1ULL << 63)
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/* NHM-EX Mbox */
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#define NHMEX_M0_MSR_GLOBAL_CTL 0xca0
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#define NHMEX_M0_MSR_PMU_DSP 0xca5
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#define NHMEX_M0_MSR_PMU_ISS 0xca6
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#define NHMEX_M0_MSR_PMU_MAP 0xca7
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#define NHMEX_M0_MSR_PMU_MSC_THR 0xca8
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#define NHMEX_M0_MSR_PMU_PGT 0xca9
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#define NHMEX_M0_MSR_PMU_PLD 0xcaa
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#define NHMEX_M0_MSR_PMU_ZDP_CTL_FVC 0xcab
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#define NHMEX_M0_MSR_PMU_CTL0 0xcb0
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#define NHMEX_M0_MSR_PMU_CNT0 0xcb1
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#define NHMEX_M_MSR_OFFSET 0x40
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#define NHMEX_M0_MSR_PMU_MM_CFG 0xe54
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#define NHMEX_M1_MSR_PMU_MM_CFG 0xe5c
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#define NHMEX_M_PMON_MM_CFG_EN (1ULL << 63)
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#define NHMEX_M_PMON_ADDR_MATCH_MASK 0x3ffffffffULL
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#define NHMEX_M_PMON_ADDR_MASK_MASK 0x7ffffffULL
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#define NHMEX_M_PMON_ADDR_MASK_SHIFT 34
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#define NHMEX_M_PMON_CTL_EN (1 << 0)
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#define NHMEX_M_PMON_CTL_PMI_EN (1 << 1)
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#define NHMEX_M_PMON_CTL_COUNT_MODE_SHIFT 2
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#define NHMEX_M_PMON_CTL_COUNT_MODE_MASK \
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(0x3 << NHMEX_M_PMON_CTL_COUNT_MODE_SHIFT)
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#define NHMEX_M_PMON_CTL_STORAGE_MODE_SHIFT 4
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#define NHMEX_M_PMON_CTL_STORAGE_MODE_MASK \
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(0x3 << NHMEX_M_PMON_CTL_STORAGE_MODE_SHIFT)
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#define NHMEX_M_PMON_CTL_WRAP_MODE (1 << 6)
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#define NHMEX_M_PMON_CTL_FLAG_MODE (1 << 7)
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#define NHMEX_M_PMON_CTL_INC_SEL_SHIFT 9
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#define NHMEX_M_PMON_CTL_INC_SEL_MASK \
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(0x1f << NHMEX_M_PMON_CTL_INC_SEL_SHIFT)
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#define NHMEX_M_PMON_CTL_SET_FLAG_SEL_SHIFT 19
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#define NHMEX_M_PMON_CTL_SET_FLAG_SEL_MASK \
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(0x7 << NHMEX_M_PMON_CTL_SET_FLAG_SEL_SHIFT)
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#define NHMEX_M_PMON_RAW_EVENT_MASK \
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(NHMEX_M_PMON_CTL_COUNT_MODE_MASK | \
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NHMEX_M_PMON_CTL_STORAGE_MODE_MASK | \
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NHMEX_M_PMON_CTL_WRAP_MODE | \
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NHMEX_M_PMON_CTL_FLAG_MODE | \
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NHMEX_M_PMON_CTL_INC_SEL_MASK | \
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NHMEX_M_PMON_CTL_SET_FLAG_SEL_MASK)
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#define NHMEX_M_PMON_ZDP_CTL_FVC_FVID_MASK 0x1f
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#define NHMEX_M_PMON_ZDP_CTL_FVC_BCMD_MASK (0x7 << 5)
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#define NHMEX_M_PMON_ZDP_CTL_FVC_RSP_MASK (0x7 << 8)
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#define NHMEX_M_PMON_ZDP_CTL_FVC_PBOX_INIT_ERR (1 << 23)
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#define NHMEX_M_PMON_ZDP_CTL_FVC_MASK \
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(NHMEX_M_PMON_ZDP_CTL_FVC_FVID_MASK | \
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NHMEX_M_PMON_ZDP_CTL_FVC_BCMD_MASK | \
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NHMEX_M_PMON_ZDP_CTL_FVC_RSP_MASK | \
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NHMEX_M_PMON_ZDP_CTL_FVC_PBOX_INIT_ERR)
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#define NHMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(n) (0x7 << (11 + 3 * (n)))
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/*
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* use the 9~13 bits to select event If the 7th bit is not set,
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* otherwise use the 19~21 bits to select event.
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*/
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#define MBOX_INC_SEL(x) ((x) << NHMEX_M_PMON_CTL_INC_SEL_SHIFT)
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#define MBOX_SET_FLAG_SEL(x) (((x) << NHMEX_M_PMON_CTL_SET_FLAG_SEL_SHIFT) | \
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NHMEX_M_PMON_CTL_FLAG_MODE)
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#define MBOX_INC_SEL_MASK (NHMEX_M_PMON_CTL_INC_SEL_MASK | \
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NHMEX_M_PMON_CTL_FLAG_MODE)
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#define MBOX_SET_FLAG_SEL_MASK (NHMEX_M_PMON_CTL_SET_FLAG_SEL_MASK | \
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NHMEX_M_PMON_CTL_FLAG_MODE)
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#define MBOX_INC_SEL_EXTAR_REG(c, r) \
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EVENT_EXTRA_REG(MBOX_INC_SEL(c), NHMEX_M0_MSR_PMU_##r, \
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MBOX_INC_SEL_MASK, (u64)-1, NHMEX_M_##r)
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#define MBOX_SET_FLAG_SEL_EXTRA_REG(c, r) \
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EVENT_EXTRA_REG(MBOX_SET_FLAG_SEL(c), NHMEX_M0_MSR_PMU_##r, \
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MBOX_SET_FLAG_SEL_MASK, \
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(u64)-1, NHMEX_M_##r)
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/* NHM-EX Rbox */
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#define NHMEX_R_MSR_GLOBAL_CTL 0xe00
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#define NHMEX_R_MSR_PMON_CTL0 0xe10
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#define NHMEX_R_MSR_PMON_CNT0 0xe11
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#define NHMEX_R_MSR_OFFSET 0x20
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#define NHMEX_R_MSR_PORTN_QLX_CFG(n) \
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((n) < 4 ? (0xe0c + (n)) : (0xe2c + (n) - 4))
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#define NHMEX_R_MSR_PORTN_IPERF_CFG0(n) (0xe04 + (n))
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#define NHMEX_R_MSR_PORTN_IPERF_CFG1(n) (0xe24 + (n))
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#define NHMEX_R_MSR_PORTN_XBR_OFFSET(n) \
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(((n) < 4 ? 0 : 0x10) + (n) * 4)
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#define NHMEX_R_MSR_PORTN_XBR_SET1_MM_CFG(n) \
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(0xe60 + NHMEX_R_MSR_PORTN_XBR_OFFSET(n))
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#define NHMEX_R_MSR_PORTN_XBR_SET1_MATCH(n) \
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(NHMEX_R_MSR_PORTN_XBR_SET1_MM_CFG(n) + 1)
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#define NHMEX_R_MSR_PORTN_XBR_SET1_MASK(n) \
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(NHMEX_R_MSR_PORTN_XBR_SET1_MM_CFG(n) + 2)
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#define NHMEX_R_MSR_PORTN_XBR_SET2_MM_CFG(n) \
|
||||
(0xe70 + NHMEX_R_MSR_PORTN_XBR_OFFSET(n))
|
||||
#define NHMEX_R_MSR_PORTN_XBR_SET2_MATCH(n) \
|
||||
(NHMEX_R_MSR_PORTN_XBR_SET2_MM_CFG(n) + 1)
|
||||
#define NHMEX_R_MSR_PORTN_XBR_SET2_MASK(n) \
|
||||
(NHMEX_R_MSR_PORTN_XBR_SET2_MM_CFG(n) + 2)
|
||||
|
||||
#define NHMEX_R_PMON_CTL_EN (1 << 0)
|
||||
#define NHMEX_R_PMON_CTL_EV_SEL_SHIFT 1
|
||||
#define NHMEX_R_PMON_CTL_EV_SEL_MASK \
|
||||
(0x1f << NHMEX_R_PMON_CTL_EV_SEL_SHIFT)
|
||||
#define NHMEX_R_PMON_CTL_PMI_EN (1 << 6)
|
||||
#define NHMEX_R_PMON_RAW_EVENT_MASK NHMEX_R_PMON_CTL_EV_SEL_MASK
|
||||
|
||||
/* NHM-EX Wbox */
|
||||
#define NHMEX_W_MSR_GLOBAL_CTL 0xc80
|
||||
#define NHMEX_W_MSR_PMON_CNT0 0xc90
|
||||
#define NHMEX_W_MSR_PMON_EVT_SEL0 0xc91
|
||||
#define NHMEX_W_MSR_PMON_FIXED_CTR 0x394
|
||||
#define NHMEX_W_MSR_PMON_FIXED_CTL 0x395
|
||||
|
||||
#define NHMEX_W_PMON_GLOBAL_FIXED_EN (1ULL << 31)
|
||||
|
||||
struct intel_uncore_ops;
|
||||
struct intel_uncore_pmu;
|
||||
struct intel_uncore_box;
|
||||
@@ -178,6 +367,7 @@ struct intel_uncore_type {
|
||||
unsigned msr_offset;
|
||||
unsigned num_shared_regs:8;
|
||||
unsigned single_fixed:1;
|
||||
unsigned pair_ctr_ctl:1;
|
||||
struct event_constraint unconstrainted;
|
||||
struct event_constraint *constraints;
|
||||
struct intel_uncore_pmu *pmus;
|
||||
@@ -213,7 +403,7 @@ struct intel_uncore_pmu {
|
||||
|
||||
struct intel_uncore_extra_reg {
|
||||
raw_spinlock_t lock;
|
||||
u64 config1;
|
||||
u64 config, config1, config2;
|
||||
atomic_t ref;
|
||||
};
|
||||
|
||||
@@ -323,14 +513,16 @@ unsigned uncore_msr_fixed_ctr(struct intel_uncore_box *box)
|
||||
static inline
|
||||
unsigned uncore_msr_event_ctl(struct intel_uncore_box *box, int idx)
|
||||
{
|
||||
return idx + box->pmu->type->event_ctl +
|
||||
return box->pmu->type->event_ctl +
|
||||
(box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +
|
||||
box->pmu->type->msr_offset * box->pmu->pmu_idx;
|
||||
}
|
||||
|
||||
static inline
|
||||
unsigned uncore_msr_perf_ctr(struct intel_uncore_box *box, int idx)
|
||||
{
|
||||
return idx + box->pmu->type->perf_ctr +
|
||||
return box->pmu->type->perf_ctr +
|
||||
(box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +
|
||||
box->pmu->type->msr_offset * box->pmu->pmu_idx;
|
||||
}
|
||||
|
||||
@@ -422,3 +614,8 @@ static inline void uncore_box_init(struct intel_uncore_box *box)
|
||||
box->pmu->type->ops->init_box(box);
|
||||
}
|
||||
}
|
||||
|
||||
static inline bool uncore_box_is_fake(struct intel_uncore_box *box)
|
||||
{
|
||||
return (box->phys_id < 0);
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user