xiaomi-sm8450/android_kernel_xiaomi_sm8450
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Merge branch 'origin' into for-linus

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Conflicts:
	MAINTAINERS
This commit is contained in:
Russell King
2009-09-24 21:22:33 +01:00
parent ae19ffbadc 94e0fb086f
commit baea7b946f
3418 changed files with 295792 additions and 97045 deletions
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52
drivers/video/Kconfig
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@@ -1275,26 +1275,6 @@ config FB_MATROX_MAVEN
painting procedures (the secondary head does not use acceleration
engine).
config FB_MATROX_MULTIHEAD
bool "Multihead support"
depends on FB_MATROX
---help---
Say Y here if you have more than one (supported) Matrox device in
your computer and you want to use all of them for different monitors
("multihead"). If you have only one device, you should say N because
the driver compiled with Y is larger and a bit slower, especially on
ia32 (ix86).
If you said M to "Matrox unified accelerated driver" and N here, you
will still be able to use several Matrox devices simultaneously:
insert several instances of the module matroxfb into the kernel
with insmod, supplying the parameter "dev=N" where N is 0, 1, etc.
for the different Matrox devices. This method is slightly faster but
uses 40 KB of kernel memory per Matrox card.
There is no need for enabling 'Matrox multihead support' if you have
only one Matrox card in the box.
config FB_RADEON
tristate "ATI Radeon display support"
depends on FB && PCI
@@ -1869,7 +1849,7 @@ config FB_W100
config FB_SH_MOBILE_LCDC
tristate "SuperH Mobile LCDC framebuffer support"
depends on FB && SUPERH
depends on FB && SUPERH && HAVE_CLK
select FB_SYS_FILLRECT
select FB_SYS_COPYAREA
select FB_SYS_IMAGEBLIT
@@ -2041,6 +2021,17 @@ config FB_SH7760
and 8, 15 or 16 bpp color; 90 degrees clockwise display rotation for
panels <= 320 pixel horizontal resolution.
config FB_DA8XX
tristate "DA8xx/OMAP-L1xx Framebuffer support"
depends on FB && ARCH_DAVINCI_DA8XX
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT
---help---
This is the frame buffer device driver for the TI LCD controller
found on DA8xx/OMAP-L1xx SoCs.
If unsure, say N.
config FB_VIRTUAL
tristate "Virtual Frame Buffer support (ONLY FOR TESTING!)"
depends on FB
@@ -2117,6 +2108,17 @@ config FB_MB862XX_LIME
---help---
Framebuffer support for Fujitsu Lime GDC on host CPU bus.
config FB_EP93XX
tristate "EP93XX frame buffer support"
depends on FB && ARCH_EP93XX
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT
---help---
Framebuffer driver for the Cirrus Logic EP93XX series of processors.
This driver is also available as a module. The module will be called
ep93xx-fb.
config FB_PRE_INIT_FB
bool "Don't reinitialize, use bootloader's GDC/Display configuration"
depends on FB_MB862XX_LIME
@@ -2124,6 +2126,14 @@ config FB_PRE_INIT_FB
Select this option if display contents should be inherited as set by
the bootloader.
config FB_MSM
tristate
depends on FB && ARCH_MSM
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT
default y
config FB_MX3
tristate "MX3 Framebuffer support"
depends on FB && MX3_IPU

3
drivers/video/Makefile
View File

@@ -85,6 +85,7 @@ obj-$(CONFIG_FB_Q40) += q40fb.o
obj-$(CONFIG_FB_TGA) += tgafb.o
obj-$(CONFIG_FB_HP300) += hpfb.o
obj-$(CONFIG_FB_G364) += g364fb.o
obj-$(CONFIG_FB_EP93XX) += ep93xx-fb.o
obj-$(CONFIG_FB_SA1100) += sa1100fb.o
obj-$(CONFIG_FB_HIT) += hitfb.o
obj-$(CONFIG_FB_EPSON1355) += epson1355fb.o
@@ -126,6 +127,7 @@ obj-$(CONFIG_FB_OMAP) += omap/
obj-$(CONFIG_XEN_FBDEV_FRONTEND) += xen-fbfront.o
obj-$(CONFIG_FB_CARMINE) += carminefb.o
obj-$(CONFIG_FB_MB862XX) += mb862xx/
obj-$(CONFIG_FB_MSM) += msm/
# Platform or fallback drivers go here
obj-$(CONFIG_FB_UVESA) += uvesafb.o
@@ -136,6 +138,7 @@ obj-$(CONFIG_FB_OF) += offb.o
obj-$(CONFIG_FB_BF54X_LQ043) += bf54x-lq043fb.o
obj-$(CONFIG_FB_BFIN_T350MCQB) += bfin-t350mcqb-fb.o
obj-$(CONFIG_FB_MX3) += mx3fb.o
obj-$(CONFIG_FB_DA8XX) += da8xx-fb.o
# the test framebuffer is last
obj-$(CONFIG_FB_VIRTUAL) += vfb.o

829
drivers/video/aty/atyfb_base.c
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File diff suppressed because it is too large Load Diff

7
drivers/video/au1100fb.c
View File

@@ -715,8 +715,11 @@ int au1100fb_setup(char *options)
}
/* Mode option (only option that start with digit) */
else if (isdigit(this_opt[0])) {
mode = kmalloc(strlen(this_opt) + 1, GFP_KERNEL);
strncpy(mode, this_opt, strlen(this_opt) + 1);
mode = kstrdup(this_opt, GFP_KERNEL);
if (!mode) {
print_err("memory allocation failed");
return -ENOMEM;
}
}
/* Unsupported option */
else {

1
drivers/video/backlight/corgi_lcd.c
View File

@@ -639,3 +639,4 @@ module_exit(corgi_lcd_exit);
MODULE_DESCRIPTION("LCD and backlight driver for SHARP C7x0/Cxx00");
MODULE_AUTHOR("Eric Miao <eric.miao@marvell.com>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("spi:corgi-lcd");

1
drivers/video/backlight/ltv350qv.c
View File

@@ -328,3 +328,4 @@ module_exit(ltv350qv_exit);
MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
MODULE_DESCRIPTION("Samsung LTV350QV LCD Driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("spi:ltv350qv");

1
drivers/video/backlight/tdo24m.c
View File

@@ -472,3 +472,4 @@ module_exit(tdo24m_exit);
MODULE_AUTHOR("Eric Miao <eric.miao@marvell.com>");
MODULE_DESCRIPTION("Driver for Toppoly TDO24M LCD Panel");
MODULE_LICENSE("GPL");
MODULE_ALIAS("spi:tdo24m");

2
drivers/video/backlight/tosa_lcd.c
View File

@@ -300,4 +300,4 @@ module_exit(tosa_lcd_exit);
MODULE_AUTHOR("Dmitry Baryshkov");
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("LCD/Backlight control for Sharp SL-6000 PDA");
MODULE_ALIAS("spi:tosa-lcd");

3
drivers/video/backlight/vgg2432a4.c
View File

@@ -280,5 +280,4 @@ module_exit(vgg2432a4_exit);
MODULE_AUTHOR("Ben Dooks <ben-linux@fluff.org>");
MODULE_DESCRIPTION("VGG2432A4 LCD Driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("spi:VGG2432A4");

2
drivers/video/cfbcopyarea.c
View File

@@ -114,7 +114,7 @@ bitcpy(struct fb_info *p, unsigned long __iomem *dst, int dst_idx,
d0 >>= right;
} else if (src_idx+n <= bits) {
// Single source word
d0 <<= left;;
d0 <<= left;
} else {
// 2 source words
d1 = FB_READL(src + 1);

8
drivers/video/console/bitblit.c
View File

@@ -25,7 +25,7 @@ static inline void update_attr(u8 *dst, u8 *src, int attribute,
struct vc_data *vc)
{
int i, offset = (vc->vc_font.height < 10) ? 1 : 2;
int width = (vc->vc_font.width + 7) >> 3;
int width = DIV_ROUND_UP(vc->vc_font.width, 8);
unsigned int cellsize = vc->vc_font.height * width;
u8 c;
@@ -144,7 +144,7 @@ static void bit_putcs(struct vc_data *vc, struct fb_info *info,
int fg, int bg)
{
struct fb_image image;
u32 width = (vc->vc_font.width + 7)/8;
u32 width = DIV_ROUND_UP(vc->vc_font.width, 8);
u32 cellsize = width * vc->vc_font.height;
u32 maxcnt = info->pixmap.size/cellsize;
u32 scan_align = info->pixmap.scan_align - 1;
@@ -173,7 +173,7 @@ static void bit_putcs(struct vc_data *vc, struct fb_info *info,
cnt = count;
image.width = vc->vc_font.width * cnt;
pitch = ((image.width + 7) >> 3) + scan_align;
pitch = DIV_ROUND_UP(image.width, 8) + scan_align;
pitch &= ~scan_align;
size = pitch * image.height + buf_align;
size &= ~buf_align;
@@ -239,7 +239,7 @@ static void bit_cursor(struct vc_data *vc, struct fb_info *info, int mode,
struct fb_cursor cursor;
struct fbcon_ops *ops = info->fbcon_par;
unsigned short charmask = vc->vc_hi_font_mask ? 0x1ff : 0xff;
int w = (vc->vc_font.width + 7) >> 3, c;
int w = DIV_ROUND_UP(vc->vc_font.width, 8), c;
int y = real_y(ops->p, vc->vc_y);
int attribute, use_sw = (vc->vc_cursor_type & 0x10);
int err = 1;

58
drivers/video/console/fbcon.c
View File

@@ -114,6 +114,7 @@ static int last_fb_vc = MAX_NR_CONSOLES - 1;
static int fbcon_is_default = 1;
static int fbcon_has_exited;
static int primary_device = -1;
static int fbcon_has_console_bind;
#ifdef CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY
static int map_override;
@@ -544,6 +545,8 @@ static int fbcon_takeover(int show_logo)
con2fb_map[i] = -1;
}
info_idx = -1;
} else {
fbcon_has_console_bind = 1;
}
return err;
@@ -725,7 +728,7 @@ static int con2fb_release_oldinfo(struct vc_data *vc, struct fb_info *oldinfo,
int oldidx, int found)
{
struct fbcon_ops *ops = oldinfo->fbcon_par;
int err = 0;
int err = 0, ret;
if (oldinfo->fbops->fb_release &&
oldinfo->fbops->fb_release(oldinfo, 0)) {
@@ -752,8 +755,14 @@ static int con2fb_release_oldinfo(struct vc_data *vc, struct fb_info *oldinfo,
newinfo in an undefined state. Thus, a call to
fb_set_par() may be needed for the newinfo.
*/
if (newinfo->fbops->fb_set_par)
newinfo->fbops->fb_set_par(newinfo);
if (newinfo->fbops->fb_set_par) {
ret = newinfo->fbops->fb_set_par(newinfo);
if (ret)
printk(KERN_ERR "con2fb_release_oldinfo: "
"detected unhandled fb_set_par error, "
"error code %d\n", ret);
}
}
return err;
@@ -763,11 +772,18 @@ static void con2fb_init_display(struct vc_data *vc, struct fb_info *info,
int unit, int show_logo)
{
struct fbcon_ops *ops = info->fbcon_par;
int ret;
ops->currcon = fg_console;
if (info->fbops->fb_set_par && !(ops->flags & FBCON_FLAGS_INIT))
info->fbops->fb_set_par(info);
if (info->fbops->fb_set_par && !(ops->flags & FBCON_FLAGS_INIT)) {
ret = info->fbops->fb_set_par(info);
if (ret)
printk(KERN_ERR "con2fb_init_display: detected "
"unhandled fb_set_par error, "
"error code %d\n", ret);
}
ops->flags |= FBCON_FLAGS_INIT;
ops->graphics = 0;
@@ -1006,7 +1022,7 @@ static void fbcon_init(struct vc_data *vc, int init)
struct vc_data *svc = *default_mode;
struct display *t, *p = &fb_display[vc->vc_num];
int logo = 1, new_rows, new_cols, rows, cols, charcnt = 256;
int cap;
int cap, ret;
if (info_idx == -1 || info == NULL)
return;
@@ -1092,8 +1108,15 @@ static void fbcon_init(struct vc_data *vc, int init)
*/
if (CON_IS_VISIBLE(vc) && vc->vc_mode == KD_TEXT) {
if (info->fbops->fb_set_par &&
!(ops->flags & FBCON_FLAGS_INIT))
info->fbops->fb_set_par(info);
!(ops->flags & FBCON_FLAGS_INIT)) {
ret = info->fbops->fb_set_par(info);
if (ret)
printk(KERN_ERR "fbcon_init: detected "
"unhandled fb_set_par error, "
"error code %d\n", ret);
}
ops->flags |= FBCON_FLAGS_INIT;
}
@@ -2119,7 +2142,7 @@ static int fbcon_switch(struct vc_data *vc)
struct fbcon_ops *ops;
struct display *p = &fb_display[vc->vc_num];
struct fb_var_screeninfo var;
int i, prev_console, charcnt = 256;
int i, ret, prev_console, charcnt = 256;
info = registered_fb[con2fb_map[vc->vc_num]];
ops = info->fbcon_par;
@@ -2174,8 +2197,14 @@ static int fbcon_switch(struct vc_data *vc)
if (old_info != NULL && (old_info != info ||
info->flags & FBINFO_MISC_ALWAYS_SETPAR)) {
if (info->fbops->fb_set_par)
info->fbops->fb_set_par(info);
if (info->fbops->fb_set_par) {
ret = info->fbops->fb_set_par(info);
if (ret)
printk(KERN_ERR "fbcon_switch: detected "
"unhandled fb_set_par error, "
"error code %d\n", ret);
}
if (old_info != info)
fbcon_del_cursor_timer(old_info);
@@ -2923,6 +2952,10 @@ static int fbcon_unbind(void)
ret = unbind_con_driver(&fb_con, first_fb_vc, last_fb_vc,
fbcon_is_default);
if (!ret)
fbcon_has_console_bind = 0;
return ret;
}
#else
@@ -2936,6 +2969,9 @@ static int fbcon_fb_unbind(int idx)
{
int i, new_idx = -1, ret = 0;
if (!fbcon_has_console_bind)
return 0;
for (i = first_fb_vc; i <= last_fb_vc; i++) {
if (con2fb_map[i] != idx &&
con2fb_map[i] != -1) {

2
drivers/video/console/newport_con.c
View File

@@ -216,7 +216,7 @@ static void newport_get_screensize(void)
}
newport_xsize = newport_ysize = 0;
for (i = 0; linetable[i + 1] && (i < sizeof(linetable)); i += 2) {
for (i = 0; i < ARRAY_SIZE(linetable) - 1 && linetable[i + 1]; i += 2) {
cols = 0;
newport_vc2_set(npregs, VC2_IREG_RADDR, linetable[i]);
npregs->set.dcbmode = (NPORT_DMODE_AVC2 | VC2_REGADDR_RAM |

9
drivers/video/console/vgacon.c
View File

@@ -180,7 +180,6 @@ static inline void vga_set_mem_top(struct vc_data *c)
}
#ifdef CONFIG_VGACON_SOFT_SCROLLBACK
#include <linux/slab.h>
/* software scrollback */
static void *vgacon_scrollback;
static int vgacon_scrollback_tail;
@@ -590,12 +589,14 @@ static void vgacon_init(struct vc_data *c, int init)
static void vgacon_deinit(struct vc_data *c)
{
/* When closing the last console, reset video origin */
if (!--vgacon_uni_pagedir[1]) {
/* When closing the active console, reset video origin */
if (CON_IS_VISIBLE(c)) {
c->vc_visible_origin = vga_vram_base;
vga_set_mem_top(c);
con_free_unimap(c);
}
if (!--vgacon_uni_pagedir[1])
con_free_unimap(c);
c->vc_uni_pagedir_loc = &c->vc_uni_pagedir;
con_set_default_unimap(c);
}

890
drivers/video/da8xx-fb.c Normal file
View File

@@ -0,0 +1,890 @@
/*
* Copyright (C) 2008-2009 MontaVista Software Inc.
* Copyright (C) 2008-2009 Texas Instruments Inc
*
* Based on the LCD driver for TI Avalanche processors written by
* Ajay Singh and Shalom Hai.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option)any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/fb.h>
#include <linux/dma-mapping.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/uaccess.h>
#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/clk.h>
#include <video/da8xx-fb.h>
#define DRIVER_NAME "da8xx_lcdc"
/* LCD Status Register */
#define LCD_END_OF_FRAME0 BIT(8)
#define LCD_FIFO_UNDERFLOW BIT(5)
#define LCD_SYNC_LOST BIT(2)
/* LCD DMA Control Register */
#define LCD_DMA_BURST_SIZE(x) ((x) << 4)
#define LCD_DMA_BURST_1 0x0
#define LCD_DMA_BURST_2 0x1
#define LCD_DMA_BURST_4 0x2
#define LCD_DMA_BURST_8 0x3
#define LCD_DMA_BURST_16 0x4
#define LCD_END_OF_FRAME_INT_ENA BIT(2)
#define LCD_DUAL_FRAME_BUFFER_ENABLE BIT(0)
/* LCD Control Register */
#define LCD_CLK_DIVISOR(x) ((x) << 8)
#define LCD_RASTER_MODE 0x01
/* LCD Raster Control Register */
#define LCD_PALETTE_LOAD_MODE(x) ((x) << 20)
#define PALETTE_AND_DATA 0x00
#define PALETTE_ONLY 0x01
#define LCD_MONO_8BIT_MODE BIT(9)
#define LCD_RASTER_ORDER BIT(8)
#define LCD_TFT_MODE BIT(7)
#define LCD_UNDERFLOW_INT_ENA BIT(6)
#define LCD_MONOCHROME_MODE BIT(1)
#define LCD_RASTER_ENABLE BIT(0)
#define LCD_TFT_ALT_ENABLE BIT(23)
#define LCD_STN_565_ENABLE BIT(24)
/* LCD Raster Timing 2 Register */
#define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16)
#define LCD_AC_BIAS_FREQUENCY(x) ((x) << 8)
#define LCD_SYNC_CTRL BIT(25)
#define LCD_SYNC_EDGE BIT(24)
#define LCD_INVERT_PIXEL_CLOCK BIT(22)
#define LCD_INVERT_LINE_CLOCK BIT(21)
#define LCD_INVERT_FRAME_CLOCK BIT(20)
/* LCD Block */
#define LCD_CTRL_REG 0x4
#define LCD_STAT_REG 0x8
#define LCD_RASTER_CTRL_REG 0x28
#define LCD_RASTER_TIMING_0_REG 0x2C
#define LCD_RASTER_TIMING_1_REG 0x30
#define LCD_RASTER_TIMING_2_REG 0x34
#define LCD_DMA_CTRL_REG 0x40
#define LCD_DMA_FRM_BUF_BASE_ADDR_0_REG 0x44
#define LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG 0x48
#define WSI_TIMEOUT 50
#define PALETTE_SIZE 256
#define LEFT_MARGIN 64
#define RIGHT_MARGIN 64
#define UPPER_MARGIN 32
#define LOWER_MARGIN 32
static resource_size_t da8xx_fb_reg_base;
static struct resource *lcdc_regs;
static inline unsigned int lcdc_read(unsigned int addr)
{
return (unsigned int)__raw_readl(da8xx_fb_reg_base + (addr));
}
static inline void lcdc_write(unsigned int val, unsigned int addr)
{
__raw_writel(val, da8xx_fb_reg_base + (addr));
}
struct da8xx_fb_par {
resource_size_t p_palette_base;
unsigned char *v_palette_base;
struct clk *lcdc_clk;
int irq;
unsigned short pseudo_palette[16];
unsigned int databuf_sz;
unsigned int palette_sz;
};
/* Variable Screen Information */
static struct fb_var_screeninfo da8xx_fb_var __devinitdata = {
.xoffset = 0,
.yoffset = 0,
.transp = {0, 0, 0},
.nonstd = 0,
.activate = 0,
.height = -1,
.width = -1,
.pixclock = 46666, /* 46us - AUO display */
.accel_flags = 0,
.left_margin = LEFT_MARGIN,
.right_margin = RIGHT_MARGIN,
.upper_margin = UPPER_MARGIN,
.lower_margin = LOWER_MARGIN,
.sync = 0,
.vmode = FB_VMODE_NONINTERLACED
};
static struct fb_fix_screeninfo da8xx_fb_fix __devinitdata = {
.id = "DA8xx FB Drv",
.type = FB_TYPE_PACKED_PIXELS,
.type_aux = 0,
.visual = FB_VISUAL_PSEUDOCOLOR,
.xpanstep = 1,
.ypanstep = 1,
.ywrapstep = 1,
.accel = FB_ACCEL_NONE
};
struct da8xx_panel {
const char name[25]; /* Full name <vendor>_<model> */
unsigned short width;
unsigned short height;
int hfp; /* Horizontal front porch */
int hbp; /* Horizontal back porch */
int hsw; /* Horizontal Sync Pulse Width */
int vfp; /* Vertical front porch */
int vbp; /* Vertical back porch */
int vsw; /* Vertical Sync Pulse Width */
int pxl_clk; /* Pixel clock */
unsigned char invert_pxl_clk; /* Invert Pixel clock */
};
static struct da8xx_panel known_lcd_panels[] = {
/* Sharp LCD035Q3DG01 */
[0] = {
.name = "Sharp_LCD035Q3DG01",
.width = 320,
.height = 240,
.hfp = 8,
.hbp = 6,
.hsw = 0,
.vfp = 2,
.vbp = 2,
.vsw = 0,
.pxl_clk = 0x10,
.invert_pxl_clk = 1,
},
/* Sharp LK043T1DG01 */
[1] = {
.name = "Sharp_LK043T1DG01",
.width = 480,
.height = 272,
.hfp = 2,
.hbp = 2,
.hsw = 41,
.vfp = 2,
.vbp = 2,
.vsw = 10,
.pxl_clk = 0x12,
.invert_pxl_clk = 0,
},
};
/* Disable the Raster Engine of the LCD Controller */
static void lcd_disable_raster(struct da8xx_fb_par *par)
{
u32 reg;
reg = lcdc_read(LCD_RASTER_CTRL_REG);
if (reg & LCD_RASTER_ENABLE)
lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
}
static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
{
u32 tmp = par->p_palette_base + par->databuf_sz - 4;
u32 reg;
/* Update the databuf in the hw. */
lcdc_write(par->p_palette_base, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
lcdc_write(tmp, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
/* Start the DMA. */
reg = lcdc_read(LCD_RASTER_CTRL_REG);
reg &= ~(3 << 20);
if (load_mode == LOAD_DATA)
reg |= LCD_PALETTE_LOAD_MODE(PALETTE_AND_DATA);
else if (load_mode == LOAD_PALETTE)
reg |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);
lcdc_write(reg, LCD_RASTER_CTRL_REG);
}
/* Configure the Burst Size of DMA */
static int lcd_cfg_dma(int burst_size)
{
u32 reg;
reg = lcdc_read(LCD_DMA_CTRL_REG) & 0x00000001;
switch (burst_size) {
case 1:
reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);
break;
case 2:
reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2);
break;
case 4:
reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4);
break;
case 8:
reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);
break;
case 16:
reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
break;
default:
return -EINVAL;
}
lcdc_write(reg, LCD_DMA_CTRL_REG);
return 0;
}
static void lcd_cfg_ac_bias(int period, int transitions_per_int)
{
u32 reg;
/* Set the AC Bias Period and Number of Transisitons per Interrupt */
reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & 0xFFF00000;
reg |= LCD_AC_BIAS_FREQUENCY(period) |
LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);
lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
}
static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,
int front_porch)
{
u32 reg;
reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0xf;
reg |= ((back_porch & 0xff) << 24)
| ((front_porch & 0xff) << 16)
| ((pulse_width & 0x3f) << 10);
lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
}
static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
int front_porch)
{
u32 reg;
reg = lcdc_read(LCD_RASTER_TIMING_1_REG) & 0x3ff;
reg |= ((back_porch & 0xff) << 24)
| ((front_porch & 0xff) << 16)
| ((pulse_width & 0x3f) << 10);
lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
}
static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
{
u32 reg;
reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(LCD_TFT_MODE |
LCD_MONO_8BIT_MODE |
LCD_MONOCHROME_MODE);
switch (cfg->p_disp_panel->panel_shade) {
case MONOCHROME:
reg |= LCD_MONOCHROME_MODE;
if (cfg->mono_8bit_mode)
reg |= LCD_MONO_8BIT_MODE;
break;
case COLOR_ACTIVE:
reg |= LCD_TFT_MODE;
if (cfg->tft_alt_mode)
reg |= LCD_TFT_ALT_ENABLE;
break;
case COLOR_PASSIVE:
if (cfg->stn_565_mode)
reg |= LCD_STN_565_ENABLE;
break;
default:
return -EINVAL;
}
/* enable additional interrupts here */
reg |= LCD_UNDERFLOW_INT_ENA;
lcdc_write(reg, LCD_RASTER_CTRL_REG);
reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
if (cfg->sync_ctrl)
reg |= LCD_SYNC_CTRL;
else
reg &= ~LCD_SYNC_CTRL;
if (cfg->sync_edge)
reg |= LCD_SYNC_EDGE;
else
reg &= ~LCD_SYNC_EDGE;
if (cfg->invert_line_clock)
reg |= LCD_INVERT_LINE_CLOCK;
else
reg &= ~LCD_INVERT_LINE_CLOCK;
if (cfg->invert_frm_clock)
reg |= LCD_INVERT_FRAME_CLOCK;
else
reg &= ~LCD_INVERT_FRAME_CLOCK;
lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
return 0;
}
static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
u32 bpp, u32 raster_order)
{
u32 bpl, reg;
/* Disable Dual Frame Buffer. */
reg = lcdc_read(LCD_DMA_CTRL_REG);
lcdc_write(reg & ~LCD_DUAL_FRAME_BUFFER_ENABLE,
LCD_DMA_CTRL_REG);
/* Set the Panel Width */
/* Pixels per line = (PPL + 1)*16 */
/*0x3F in bits 4..9 gives max horisontal resolution = 1024 pixels*/
width &= 0x3f0;
reg = lcdc_read(LCD_RASTER_TIMING_0_REG);
reg &= 0xfffffc00;
reg |= ((width >> 4) - 1) << 4;
lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
/* Set the Panel Height */
reg = lcdc_read(LCD_RASTER_TIMING_1_REG);
reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
/* Set the Raster Order of the Frame Buffer */
reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(1 << 8);
if (raster_order)
reg |= LCD_RASTER_ORDER;
lcdc_write(reg, LCD_RASTER_CTRL_REG);
switch (bpp) {
case 1:
case 2:
case 4:
case 16:
par->palette_sz = 16 * 2;
break;
case 8:
par->palette_sz = 256 * 2;
break;
default:
return -EINVAL;
}
bpl = width * bpp / 8;
par->databuf_sz = height * bpl + par->palette_sz;
return 0;
}
static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
unsigned blue, unsigned transp,
struct fb_info *info)
{
struct da8xx_fb_par *par = info->par;
unsigned short *palette = (unsigned short *)par->v_palette_base;
u_short pal;
if (regno > 255)
return 1;
if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
return 1;
if (info->var.bits_per_pixel == 8) {
red >>= 4;
green >>= 8;
blue >>= 12;
pal = (red & 0x0f00);
pal |= (green & 0x00f0);
pal |= (blue & 0x000f);
palette[regno] = pal;
} else if ((info->var.bits_per_pixel == 16) && regno < 16) {
red >>= (16 - info->var.red.length);
red <<= info->var.red.offset;
green >>= (16 - info->var.green.length);
green <<= info->var.green.offset;
blue >>= (16 - info->var.blue.length);
blue <<= info->var.blue.offset;
par->pseudo_palette[regno] = red | green | blue;
palette[0] = 0x4000;
}
return 0;
}
static void lcd_reset(struct da8xx_fb_par *par)
{
/* Disable the Raster if previously Enabled */
if (lcdc_read(LCD_RASTER_CTRL_REG) & LCD_RASTER_ENABLE)
lcd_disable_raster(par);
/* DMA has to be disabled */
lcdc_write(0, LCD_DMA_CTRL_REG);
lcdc_write(0, LCD_RASTER_CTRL_REG);
}
static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
struct da8xx_panel *panel)
{
u32 bpp;
int ret = 0;
lcd_reset(par);
/* Configure the LCD clock divisor. */
lcdc_write(LCD_CLK_DIVISOR(panel->pxl_clk) |
(LCD_RASTER_MODE & 0x1), LCD_CTRL_REG);
if (panel->invert_pxl_clk)
lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) |
LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
else
lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) &
~LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
/* Configure the DMA burst size. */
ret = lcd_cfg_dma(cfg->dma_burst_sz);
if (ret < 0)
return ret;
/* Configure the AC bias properties. */
lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);
/* Configure the vertical and horizontal sync properties. */
lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp);
lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp);
/* Configure for disply */
ret = lcd_cfg_display(cfg);
if (ret < 0)
return ret;
if (QVGA != cfg->p_disp_panel->panel_type)
return -EINVAL;
if (cfg->bpp <= cfg->p_disp_panel->max_bpp &&
cfg->bpp >= cfg->p_disp_panel->min_bpp)
bpp = cfg->bpp;
else
bpp = cfg->p_disp_panel->max_bpp;
if (bpp == 12)
bpp = 16;
ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->width,
(unsigned int)panel->height, bpp,
cfg->raster_order);
if (ret < 0)
return ret;
/* Configure FDD */
lcdc_write((lcdc_read(LCD_RASTER_CTRL_REG) & 0xfff00fff) |
(cfg->fdd << 12), LCD_RASTER_CTRL_REG);
return 0;
}
static irqreturn_t lcdc_irq_handler(int irq, void *arg)
{
u32 stat = lcdc_read(LCD_STAT_REG);
u32 reg;
if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
reg = lcdc_read(LCD_RASTER_CTRL_REG);
lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
lcdc_write(stat, LCD_STAT_REG);
lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
} else
lcdc_write(stat, LCD_STAT_REG);
return IRQ_HANDLED;
}
static int fb_check_var(struct fb_var_screeninfo *var,
struct fb_info *info)
{
int err = 0;
switch (var->bits_per_pixel) {
case 1:
case 8:
var->red.offset = 0;
var->red.length = 8;
var->green.offset = 0;
var->green.length = 8;
var->blue.offset = 0;
var->blue.length = 8;
var->transp.offset = 0;
var->transp.length = 0;
break;
case 4:
var->red.offset = 0;
var->red.length = 4;
var->green.offset = 0;
var->green.length = 4;
var->blue.offset = 0;
var->blue.length = 4;
var->transp.offset = 0;
var->transp.length = 0;
break;
case 16: /* RGB 565 */
var->red.offset = 0;
var->red.length = 5;
var->green.offset = 5;
var->green.length = 6;
var->blue.offset = 11;
var->blue.length = 5;
var->transp.offset = 0;
var->transp.length = 0;
break;
default:
err = -EINVAL;
}
var->red.msb_right = 0;
var->green.msb_right = 0;
var->blue.msb_right = 0;
var->transp.msb_right = 0;
return err;
}
static int __devexit fb_remove(struct platform_device *dev)
{
struct fb_info *info = dev_get_drvdata(&dev->dev);
if (info) {
struct da8xx_fb_par *par = info->par;
if (lcdc_read(LCD_RASTER_CTRL_REG) & LCD_RASTER_ENABLE)
lcd_disable_raster(par);
lcdc_write(0, LCD_RASTER_CTRL_REG);
/* disable DMA */
lcdc_write(0, LCD_DMA_CTRL_REG);
unregister_framebuffer(info);
fb_dealloc_cmap(&info->cmap);
dma_free_coherent(NULL, par->databuf_sz + PAGE_SIZE,
info->screen_base,
info->fix.smem_start);
free_irq(par->irq, par);
clk_disable(par->lcdc_clk);
clk_put(par->lcdc_clk);
framebuffer_release(info);
iounmap((void __iomem *)da8xx_fb_reg_base);
release_mem_region(lcdc_regs->start, resource_size(lcdc_regs));
}
return 0;
}
static int fb_ioctl(struct fb_info *info, unsigned int cmd,
unsigned long arg)
{
struct lcd_sync_arg sync_arg;
switch (cmd) {
case FBIOGET_CONTRAST:
case FBIOPUT_CONTRAST:
case FBIGET_BRIGHTNESS:
case FBIPUT_BRIGHTNESS:
case FBIGET_COLOR:
case FBIPUT_COLOR:
return -ENOTTY;
case FBIPUT_HSYNC:
if (copy_from_user(&sync_arg, (char *)arg,
sizeof(struct lcd_sync_arg)))
return -EFAULT;
lcd_cfg_horizontal_sync(sync_arg.back_porch,
sync_arg.pulse_width,
sync_arg.front_porch);
break;
case FBIPUT_VSYNC:
if (copy_from_user(&sync_arg, (char *)arg,
sizeof(struct lcd_sync_arg)))
return -EFAULT;
lcd_cfg_vertical_sync(sync_arg.back_porch,
sync_arg.pulse_width,
sync_arg.front_porch);
break;
default:
return -EINVAL;
}
return 0;
}
static struct fb_ops da8xx_fb_ops = {
.owner = THIS_MODULE,
.fb_check_var = fb_check_var,
.fb_setcolreg = fb_setcolreg,
.fb_ioctl = fb_ioctl,
.fb_fillrect = cfb_fillrect,
.fb_copyarea = cfb_copyarea,
.fb_imageblit = cfb_imageblit,
};
static int __init fb_probe(struct platform_device *device)
{
struct da8xx_lcdc_platform_data *fb_pdata =
device->dev.platform_data;
struct lcd_ctrl_config *lcd_cfg;
struct da8xx_panel *lcdc_info;
struct fb_info *da8xx_fb_info;
struct clk *fb_clk = NULL;
struct da8xx_fb_par *par;
resource_size_t len;
int ret, i;
if (fb_pdata == NULL) {
dev_err(&device->dev, "Can not get platform data\n");
return -ENOENT;
}
lcdc_regs = platform_get_resource(device, IORESOURCE_MEM, 0);
if (!lcdc_regs) {
dev_err(&device->dev,
"Can not get memory resource for LCD controller\n");
return -ENOENT;
}
len = resource_size(lcdc_regs);
lcdc_regs = request_mem_region(lcdc_regs->start, len, lcdc_regs->name);
if (!lcdc_regs)
return -EBUSY;
da8xx_fb_reg_base = (resource_size_t)ioremap(lcdc_regs->start, len);
if (!da8xx_fb_reg_base) {
ret = -EBUSY;
goto err_request_mem;
}
fb_clk = clk_get(&device->dev, NULL);
if (IS_ERR(fb_clk)) {
dev_err(&device->dev, "Can not get device clock\n");
ret = -ENODEV;
goto err_ioremap;
}
ret = clk_enable(fb_clk);
if (ret)
goto err_clk_put;
for (i = 0, lcdc_info = known_lcd_panels;
i < ARRAY_SIZE(known_lcd_panels);
i++, lcdc_info++) {
if (strcmp(fb_pdata->type, lcdc_info->name) == 0)
break;
}
if (i == ARRAY_SIZE(known_lcd_panels)) {
dev_err(&device->dev, "GLCD: No valid panel found\n");
ret = ENODEV;
goto err_clk_disable;
} else
dev_info(&device->dev, "GLCD: Found %s panel\n",
fb_pdata->type);
lcd_cfg = (struct lcd_ctrl_config *)fb_pdata->controller_data;
da8xx_fb_info = framebuffer_alloc(sizeof(struct da8xx_fb_par),
&device->dev);
if (!da8xx_fb_info) {
dev_dbg(&device->dev, "Memory allocation failed for fb_info\n");
ret = -ENOMEM;
goto err_clk_disable;
}
par = da8xx_fb_info->par;
if (lcd_init(par, lcd_cfg, lcdc_info) < 0) {
dev_err(&device->dev, "lcd_init failed\n");
ret = -EFAULT;
goto err_release_fb;
}
/* allocate frame buffer */
da8xx_fb_info->screen_base = dma_alloc_coherent(NULL,
par->databuf_sz + PAGE_SIZE,
(resource_size_t *)
&da8xx_fb_info->fix.smem_start,
GFP_KERNEL | GFP_DMA);
if (!da8xx_fb_info->screen_base) {
dev_err(&device->dev,
"GLCD: kmalloc for frame buffer failed\n");
ret = -EINVAL;
goto err_release_fb;
}
/* move palette base pointer by (PAGE_SIZE - palette_sz) bytes */
par->v_palette_base = da8xx_fb_info->screen_base +
(PAGE_SIZE - par->palette_sz);
par->p_palette_base = da8xx_fb_info->fix.smem_start +
(PAGE_SIZE - par->palette_sz);
/* the rest of the frame buffer is pixel data */
da8xx_fb_fix.smem_start = par->p_palette_base + par->palette_sz;
da8xx_fb_fix.smem_len = par->databuf_sz - par->palette_sz;
da8xx_fb_fix.line_length = (lcdc_info->width * lcd_cfg->bpp) / 8;
par->lcdc_clk = fb_clk;
par->irq = platform_get_irq(device, 0);
if (par->irq < 0) {
ret = -ENOENT;
goto err_release_fb_mem;
}
ret = request_irq(par->irq, lcdc_irq_handler, 0, DRIVER_NAME, par);
if (ret)
goto err_release_fb_mem;
/* Initialize par */
da8xx_fb_info->var.bits_per_pixel = lcd_cfg->bpp;
da8xx_fb_var.xres = lcdc_info->width;
da8xx_fb_var.xres_virtual = lcdc_info->width;
da8xx_fb_var.yres = lcdc_info->height;
da8xx_fb_var.yres_virtual = lcdc_info->height;
da8xx_fb_var.grayscale =
lcd_cfg->p_disp_panel->panel_shade == MONOCHROME ? 1 : 0;
da8xx_fb_var.bits_per_pixel = lcd_cfg->bpp;
da8xx_fb_var.hsync_len = lcdc_info->hsw;
da8xx_fb_var.vsync_len = lcdc_info->vsw;
/* Initialize fbinfo */
da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;
da8xx_fb_info->fix = da8xx_fb_fix;
da8xx_fb_info->var = da8xx_fb_var;
da8xx_fb_info->fbops = &da8xx_fb_ops;
da8xx_fb_info->pseudo_palette = par->pseudo_palette;
ret = fb_alloc_cmap(&da8xx_fb_info->cmap, PALETTE_SIZE, 0);
if (ret)
goto err_free_irq;
/* First palette_sz byte of the frame buffer is the palette */
da8xx_fb_info->cmap.len = par->palette_sz;
/* Flush the buffer to the screen. */
lcd_blit(LOAD_DATA, par);
/* initialize var_screeninfo */
da8xx_fb_var.activate = FB_ACTIVATE_FORCE;
fb_set_var(da8xx_fb_info, &da8xx_fb_var);
dev_set_drvdata(&device->dev, da8xx_fb_info);
/* Register the Frame Buffer */
if (register_framebuffer(da8xx_fb_info) < 0) {
dev_err(&device->dev,
"GLCD: Frame Buffer Registration Failed!\n");
ret = -EINVAL;
goto err_dealloc_cmap;
}
/* enable raster engine */
lcdc_write(lcdc_read(LCD_RASTER_CTRL_REG) |
LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
return 0;
err_dealloc_cmap:
fb_dealloc_cmap(&da8xx_fb_info->cmap);
err_free_irq:
free_irq(par->irq, par);
err_release_fb_mem:
dma_free_coherent(NULL, par->databuf_sz + PAGE_SIZE,
da8xx_fb_info->screen_base,
da8xx_fb_info->fix.smem_start);
err_release_fb:
framebuffer_release(da8xx_fb_info);
err_clk_disable:
clk_disable(fb_clk);
err_clk_put:
clk_put(fb_clk);
err_ioremap:
iounmap((void __iomem *)da8xx_fb_reg_base);
err_request_mem:
release_mem_region(lcdc_regs->start, len);
return ret;
}
#ifdef CONFIG_PM
static int fb_suspend(struct platform_device *dev, pm_message_t state)
{
return -EBUSY;
}
static int fb_resume(struct platform_device *dev)
{
return -EBUSY;
}
#else
#define fb_suspend NULL
#define fb_resume NULL
#endif
static struct platform_driver da8xx_fb_driver = {
.probe = fb_probe,
.remove = fb_remove,
.suspend = fb_suspend,
.resume = fb_resume,
.driver = {
.name = DRIVER_NAME,
.owner = THIS_MODULE,
},
};
static int __init da8xx_fb_init(void)
{
return platform_driver_register(&da8xx_fb_driver);
}
static void __exit da8xx_fb_cleanup(void)
{
platform_driver_unregister(&da8xx_fb_driver);
}
module_init(da8xx_fb_init);
module_exit(da8xx_fb_cleanup);
MODULE_DESCRIPTION("Framebuffer driver for TI da8xx/omap-l1xx");
MODULE_AUTHOR("Texas Instruments");
MODULE_LICENSE("GPL");

646
drivers/video/ep93xx-fb.c Normal file
View File

@@ -0,0 +1,646 @@
/*
* linux/drivers/video/ep93xx-fb.c
*
* Framebuffer support for the EP93xx series.
*
* Copyright (C) 2007 Bluewater Systems Ltd
* Author: Ryan Mallon <ryan@bluewatersys.com>
*
* Copyright (c) 2009 H Hartley Sweeten <hsweeten@visionengravers.com>
*
* Based on the Cirrus Logic ep93xxfb driver, and various other ep93xxfb
* drivers.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/clk.h>
#include <linux/fb.h>
#include <mach/fb.h>
/* Vertical Frame Timing Registers */
#define EP93XXFB_VLINES_TOTAL 0x0000 /* SW locked */
#define EP93XXFB_VSYNC 0x0004 /* SW locked */
#define EP93XXFB_VACTIVE 0x0008 /* SW locked */
#define EP93XXFB_VBLANK 0x0228 /* SW locked */
#define EP93XXFB_VCLK 0x000c /* SW locked */
/* Horizontal Frame Timing Registers */
#define EP93XXFB_HCLKS_TOTAL 0x0010 /* SW locked */
#define EP93XXFB_HSYNC 0x0014 /* SW locked */
#define EP93XXFB_HACTIVE 0x0018 /* SW locked */
#define EP93XXFB_HBLANK 0x022c /* SW locked */
#define EP93XXFB_HCLK 0x001c /* SW locked */
/* Frame Buffer Memory Configuration Registers */
#define EP93XXFB_SCREEN_PAGE 0x0028
#define EP93XXFB_SCREEN_HPAGE 0x002c
#define EP93XXFB_SCREEN_LINES 0x0030
#define EP93XXFB_LINE_LENGTH 0x0034
#define EP93XXFB_VLINE_STEP 0x0038
#define EP93XXFB_LINE_CARRY 0x003c /* SW locked */
#define EP93XXFB_EOL_OFFSET 0x0230
/* Other Video Registers */
#define EP93XXFB_BRIGHTNESS 0x0020
#define EP93XXFB_ATTRIBS 0x0024 /* SW locked */
#define EP93XXFB_SWLOCK 0x007c /* SW locked */
#define EP93XXFB_AC_RATE 0x0214
#define EP93XXFB_FIFO_LEVEL 0x0234
#define EP93XXFB_PIXELMODE 0x0054
#define EP93XXFB_PIXELMODE_32BPP (0x7 << 0)
#define EP93XXFB_PIXELMODE_24BPP (0x6 << 0)
#define EP93XXFB_PIXELMODE_16BPP (0x4 << 0)
#define EP93XXFB_PIXELMODE_8BPP (0x2 << 0)
#define EP93XXFB_PIXELMODE_SHIFT_1P_24B (0x0 << 3)
#define EP93XXFB_PIXELMODE_SHIFT_1P_18B (0x1 << 3)
#define EP93XXFB_PIXELMODE_COLOR_LUT (0x0 << 10)
#define EP93XXFB_PIXELMODE_COLOR_888 (0x4 << 10)
#define EP93XXFB_PIXELMODE_COLOR_555 (0x5 << 10)
#define EP93XXFB_PARL_IF_OUT 0x0058
#define EP93XXFB_PARL_IF_IN 0x005c
/* Blink Control Registers */
#define EP93XXFB_BLINK_RATE 0x0040
#define EP93XXFB_BLINK_MASK 0x0044
#define EP93XXFB_BLINK_PATTRN 0x0048
#define EP93XXFB_PATTRN_MASK 0x004c
#define EP93XXFB_BKGRND_OFFSET 0x0050
/* Hardware Cursor Registers */
#define EP93XXFB_CURSOR_ADR_START 0x0060
#define EP93XXFB_CURSOR_ADR_RESET 0x0064
#define EP93XXFB_CURSOR_SIZE 0x0068
#define EP93XXFB_CURSOR_COLOR1 0x006c
#define EP93XXFB_CURSOR_COLOR2 0x0070
#define EP93XXFB_CURSOR_BLINK_COLOR1 0x021c
#define EP93XXFB_CURSOR_BLINK_COLOR2 0x0220
#define EP93XXFB_CURSOR_XY_LOC 0x0074
#define EP93XXFB_CURSOR_DSCAN_HY_LOC 0x0078
#define EP93XXFB_CURSOR_BLINK_RATE_CTRL 0x0224
/* LUT Registers */
#define EP93XXFB_GRY_SCL_LUTR 0x0080
#define EP93XXFB_GRY_SCL_LUTG 0x0280
#define EP93XXFB_GRY_SCL_LUTB 0x0300
#define EP93XXFB_LUT_SW_CONTROL 0x0218
#define EP93XXFB_LUT_SW_CONTROL_SWTCH (1 << 0)
#define EP93XXFB_LUT_SW_CONTROL_SSTAT (1 << 1)
#define EP93XXFB_COLOR_LUT 0x0400
/* Video Signature Registers */
#define EP93XXFB_VID_SIG_RSLT_VAL 0x0200
#define EP93XXFB_VID_SIG_CTRL 0x0204
#define EP93XXFB_VSIG 0x0208
#define EP93XXFB_HSIG 0x020c
#define EP93XXFB_SIG_CLR_STR 0x0210
/* Minimum / Maximum resolutions supported */
#define EP93XXFB_MIN_XRES 64
#define EP93XXFB_MIN_YRES 64
#define EP93XXFB_MAX_XRES 1024
#define EP93XXFB_MAX_YRES 768
struct ep93xx_fbi {
struct ep93xxfb_mach_info *mach_info;
struct clk *clk;
struct resource *res;
void __iomem *mmio_base;
unsigned int pseudo_palette[256];
};
static int check_screenpage_bug = 1;
module_param(check_screenpage_bug, int, 0644);
MODULE_PARM_DESC(check_screenpage_bug,
"Check for bit 27 screen page bug. Default = 1");
static inline unsigned int ep93xxfb_readl(struct ep93xx_fbi *fbi,
unsigned int off)
{
return __raw_readl(fbi->mmio_base + off);
}
static inline void ep93xxfb_writel(struct ep93xx_fbi *fbi,
unsigned int val, unsigned int off)
{
__raw_writel(val, fbi->mmio_base + off);
}
/*
* Write to one of the locked raster registers.
*/
static inline void ep93xxfb_out_locked(struct ep93xx_fbi *fbi,
unsigned int val, unsigned int reg)
{
/*
* We don't need a lock or delay here since the raster register
* block will remain unlocked until the next access.
*/
ep93xxfb_writel(fbi, 0xaa, EP93XXFB_SWLOCK);
ep93xxfb_writel(fbi, val, reg);
}
static void ep93xxfb_set_video_attribs(struct fb_info *info)
{
struct ep93xx_fbi *fbi = info->par;
unsigned int attribs;
attribs = EP93XXFB_ENABLE;
attribs |= fbi->mach_info->flags;
ep93xxfb_out_locked(fbi, attribs, EP93XXFB_ATTRIBS);
}
static int ep93xxfb_set_pixelmode(struct fb_info *info)
{
struct ep93xx_fbi *fbi = info->par;
unsigned int val;
info->var.transp.offset = 0;
info->var.transp.length = 0;
switch (info->var.bits_per_pixel) {
case 8:
val = EP93XXFB_PIXELMODE_8BPP | EP93XXFB_PIXELMODE_COLOR_LUT |
EP93XXFB_PIXELMODE_SHIFT_1P_18B;
info->var.red.offset = 0;
info->var.red.length = 8;
info->var.green.offset = 0;
info->var.green.length = 8;
info->var.blue.offset = 0;
info->var.blue.length = 8;
info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
break;
case 16:
val = EP93XXFB_PIXELMODE_16BPP | EP93XXFB_PIXELMODE_COLOR_555 |
EP93XXFB_PIXELMODE_SHIFT_1P_18B;
info->var.red.offset = 11;
info->var.red.length = 5;
info->var.green.offset = 5;
info->var.green.length = 6;
info->var.blue.offset = 0;
info->var.blue.length = 5;
info->fix.visual = FB_VISUAL_TRUECOLOR;
break;
case 24:
val = EP93XXFB_PIXELMODE_24BPP | EP93XXFB_PIXELMODE_COLOR_888 |
EP93XXFB_PIXELMODE_SHIFT_1P_24B;
info->var.red.offset = 16;
info->var.red.length = 8;
info->var.green.offset = 8;
info->var.green.length = 8;
info->var.blue.offset = 0;
info->var.blue.length = 8;
info->fix.visual = FB_VISUAL_TRUECOLOR;
break;
case 32:
val = EP93XXFB_PIXELMODE_32BPP | EP93XXFB_PIXELMODE_COLOR_888 |
EP93XXFB_PIXELMODE_SHIFT_1P_24B;
info->var.red.offset = 16;
info->var.red.length = 8;
info->var.green.offset = 8;
info->var.green.length = 8;
info->var.blue.offset = 0;
info->var.blue.length = 8;
info->fix.visual = FB_VISUAL_TRUECOLOR;
break;
default:
return -EINVAL;
}
ep93xxfb_writel(fbi, val, EP93XXFB_PIXELMODE);
return 0;
}
static void ep93xxfb_set_timing(struct fb_info *info)
{
struct ep93xx_fbi *fbi = info->par;
unsigned int vlines_total, hclks_total, start, stop;
vlines_total = info->var.yres + info->var.upper_margin +
info->var.lower_margin + info->var.vsync_len - 1;
hclks_total = info->var.xres + info->var.left_margin +
info->var.right_margin + info->var.hsync_len - 1;
ep93xxfb_out_locked(fbi, vlines_total, EP93XXFB_VLINES_TOTAL);
ep93xxfb_out_locked(fbi, hclks_total, EP93XXFB_HCLKS_TOTAL);
start = vlines_total;
stop = vlines_total - info->var.vsync_len;
ep93xxfb_out_locked(fbi, start | (stop << 16), EP93XXFB_VSYNC);
start = vlines_total - info->var.vsync_len - info->var.upper_margin;
stop = info->var.lower_margin - 1;
ep93xxfb_out_locked(fbi, start | (stop << 16), EP93XXFB_VBLANK);
ep93xxfb_out_locked(fbi, start | (stop << 16), EP93XXFB_VACTIVE);
start = vlines_total;
stop = vlines_total + 1;
ep93xxfb_out_locked(fbi, start | (stop << 16), EP93XXFB_VCLK);
start = hclks_total;
stop = hclks_total - info->var.hsync_len;
ep93xxfb_out_locked(fbi, start | (stop << 16), EP93XXFB_HSYNC);
start = hclks_total - info->var.hsync_len - info->var.left_margin;
stop = info->var.right_margin - 1;
ep93xxfb_out_locked(fbi, start | (stop << 16), EP93XXFB_HBLANK);
ep93xxfb_out_locked(fbi, start | (stop << 16), EP93XXFB_HACTIVE);
start = hclks_total;
stop = hclks_total;
ep93xxfb_out_locked(fbi, start | (stop << 16), EP93XXFB_HCLK);
ep93xxfb_out_locked(fbi, 0x0, EP93XXFB_LINE_CARRY);
}
static int ep93xxfb_set_par(struct fb_info *info)
{
struct ep93xx_fbi *fbi = info->par;
clk_set_rate(fbi->clk, 1000 * PICOS2KHZ(info->var.pixclock));
ep93xxfb_set_timing(info);
info->fix.line_length = info->var.xres_virtual *
info->var.bits_per_pixel / 8;
ep93xxfb_writel(fbi, info->fix.smem_start, EP93XXFB_SCREEN_PAGE);
ep93xxfb_writel(fbi, info->var.yres - 1, EP93XXFB_SCREEN_LINES);
ep93xxfb_writel(fbi, ((info->var.xres * info->var.bits_per_pixel)
/ 32) - 1, EP93XXFB_LINE_LENGTH);
ep93xxfb_writel(fbi, info->fix.line_length / 4, EP93XXFB_VLINE_STEP);
ep93xxfb_set_video_attribs(info);
return 0;
}
static int ep93xxfb_check_var(struct fb_var_screeninfo *var,
struct fb_info *info)
{
int err;
err = ep93xxfb_set_pixelmode(info);
if (err)
return err;
var->xres = max_t(unsigned int, var->xres, EP93XXFB_MIN_XRES);
var->xres = min_t(unsigned int, var->xres, EP93XXFB_MAX_XRES);
var->xres_virtual = max(var->xres_virtual, var->xres);
var->yres = max_t(unsigned int, var->yres, EP93XXFB_MIN_YRES);
var->yres = min_t(unsigned int, var->yres, EP93XXFB_MAX_YRES);
var->yres_virtual = max(var->yres_virtual, var->yres);
return 0;
}
static int ep93xxfb_mmap(struct fb_info *info, struct vm_area_struct *vma)
{
unsigned int offset = vma->vm_pgoff << PAGE_SHIFT;
if (offset < info->fix.smem_len) {
return dma_mmap_writecombine(info->dev, vma, info->screen_base,
info->fix.smem_start,
info->fix.smem_len);
}
return -EINVAL;
}
static int ep93xxfb_blank(int blank_mode, struct fb_info *info)
{
struct ep93xx_fbi *fbi = info->par;
unsigned int attribs = ep93xxfb_readl(fbi, EP93XXFB_ATTRIBS);
if (blank_mode) {
if (fbi->mach_info->blank)
fbi->mach_info->blank(blank_mode, info);
ep93xxfb_out_locked(fbi, attribs & ~EP93XXFB_ENABLE,
EP93XXFB_ATTRIBS);
clk_disable(fbi->clk);
} else {
clk_enable(fbi->clk);
ep93xxfb_out_locked(fbi, attribs | EP93XXFB_ENABLE,
EP93XXFB_ATTRIBS);
if (fbi->mach_info->blank)
fbi->mach_info->blank(blank_mode, info);
}
return 0;
}
static inline int ep93xxfb_convert_color(int val, int width)
{
return ((val << width) + 0x7fff - val) >> 16;
}
static int ep93xxfb_setcolreg(unsigned int regno, unsigned int red,
unsigned int green, unsigned int blue,
unsigned int transp, struct fb_info *info)
{
struct ep93xx_fbi *fbi = info->par;
unsigned int *pal = info->pseudo_palette;
unsigned int ctrl, i, rgb, lut_current, lut_stat;
switch (info->fix.visual) {
case FB_VISUAL_PSEUDOCOLOR:
rgb = ((red & 0xff00) << 8) | (green & 0xff00) |
((blue & 0xff00) >> 8);
pal[regno] = rgb;
ep93xxfb_writel(fbi, rgb, (EP93XXFB_COLOR_LUT + (regno << 2)));
ctrl = ep93xxfb_readl(fbi, EP93XXFB_LUT_SW_CONTROL);
lut_stat = !!(ctrl & EP93XXFB_LUT_SW_CONTROL_SSTAT);
lut_current = !!(ctrl & EP93XXFB_LUT_SW_CONTROL_SWTCH);
if (lut_stat == lut_current) {
for (i = 0; i < 256; i++) {
ep93xxfb_writel(fbi, pal[i],
EP93XXFB_COLOR_LUT + (i << 2));
}
ep93xxfb_writel(fbi,
ctrl ^ EP93XXFB_LUT_SW_CONTROL_SWTCH,
EP93XXFB_LUT_SW_CONTROL);
}
break;
case FB_VISUAL_TRUECOLOR:
if (regno > 16)
return 1;
red = ep93xxfb_convert_color(red, info->var.red.length);
green = ep93xxfb_convert_color(green, info->var.green.length);
blue = ep93xxfb_convert_color(blue, info->var.blue.length);
transp = ep93xxfb_convert_color(transp,
info->var.transp.length);
pal[regno] = (red << info->var.red.offset) |
(green << info->var.green.offset) |
(blue << info->var.blue.offset) |
(transp << info->var.transp.offset);
break;
default:
return 1;
}
return 0;
}
static struct fb_ops ep93xxfb_ops = {
.owner = THIS_MODULE,
.fb_check_var = ep93xxfb_check_var,
.fb_set_par = ep93xxfb_set_par,
.fb_blank = ep93xxfb_blank,
.fb_fillrect = cfb_fillrect,
.fb_copyarea = cfb_copyarea,
.fb_imageblit = cfb_imageblit,
.fb_setcolreg = ep93xxfb_setcolreg,
.fb_mmap = ep93xxfb_mmap,
};
static int __init ep93xxfb_calc_fbsize(struct ep93xxfb_mach_info *mach_info)
{
int i, fb_size = 0;
if (mach_info->num_modes == EP93XXFB_USE_MODEDB) {
fb_size = EP93XXFB_MAX_XRES * EP93XXFB_MAX_YRES *
mach_info->bpp / 8;
} else {
for (i = 0; i < mach_info->num_modes; i++) {
const struct fb_videomode *mode;
int size;
mode = &mach_info->modes[i];
size = mode->xres * mode->yres * mach_info->bpp / 8;
if (size > fb_size)
fb_size = size;
}
}
return fb_size;
}
static int __init ep93xxfb_alloc_videomem(struct fb_info *info)
{
struct ep93xx_fbi *fbi = info->par;
char __iomem *virt_addr;
dma_addr_t phys_addr;
unsigned int fb_size;
fb_size = ep93xxfb_calc_fbsize(fbi->mach_info);
virt_addr = dma_alloc_writecombine(info->dev, fb_size,
&phys_addr, GFP_KERNEL);
if (!virt_addr)
return -ENOMEM;
/*
* There is a bug in the ep93xx framebuffer which causes problems
* if bit 27 of the physical address is set.
* See: http://marc.info/?l=linux-arm-kernel&m=110061245502000&w=2
* There does not seem to be any offical errata for this, but I
* have confirmed the problem exists on my hardware (ep9315) at
* least.
*/
if (check_screenpage_bug && phys_addr & (1 << 27)) {
dev_err(info->dev, "ep93xx framebuffer bug. phys addr (0x%x) "
"has bit 27 set: cannot init framebuffer\n",
phys_addr);
dma_free_coherent(info->dev, fb_size, virt_addr, phys_addr);
return -ENOMEM;
}
info->fix.smem_start = phys_addr;
info->fix.smem_len = fb_size;
info->screen_base = virt_addr;
return 0;
}
static void ep93xxfb_dealloc_videomem(struct fb_info *info)
{
if (info->screen_base)
dma_free_coherent(info->dev, info->fix.smem_len,
info->screen_base, info->fix.smem_start);
}
static int __init ep93xxfb_probe(struct platform_device *pdev)
{
struct ep93xxfb_mach_info *mach_info = pdev->dev.platform_data;
struct fb_info *info;
struct ep93xx_fbi *fbi;
struct resource *res;
char *video_mode;
int err;
if (!mach_info)
return -EINVAL;
info = framebuffer_alloc(sizeof(struct ep93xx_fbi), &pdev->dev);
if (!info)
return -ENOMEM;
info->dev = &pdev->dev;
platform_set_drvdata(pdev, info);
fbi = info->par;
fbi->mach_info = mach_info;
err = fb_alloc_cmap(&info->cmap, 256, 0);
if (err)
goto failed;
err = ep93xxfb_alloc_videomem(info);
if (err)
goto failed;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
err = -ENXIO;
goto failed;
}
res = request_mem_region(res->start, resource_size(res), pdev->name);
if (!res) {
err = -EBUSY;
goto failed;
}
fbi->res = res;
fbi->mmio_base = ioremap(res->start, resource_size(res));
if (!fbi->mmio_base) {
err = -ENXIO;
goto failed;
}
strcpy(info->fix.id, pdev->name);
info->fbops = &ep93xxfb_ops;
info->fix.type = FB_TYPE_PACKED_PIXELS;
info->fix.accel = FB_ACCEL_NONE;
info->var.activate = FB_ACTIVATE_NOW;
info->var.vmode = FB_VMODE_NONINTERLACED;
info->flags = FBINFO_DEFAULT;
info->node = -1;
info->state = FBINFO_STATE_RUNNING;
info->pseudo_palette = &fbi->pseudo_palette;
fb_get_options("ep93xx-fb", &video_mode);
err = fb_find_mode(&info->var, info, video_mode,
fbi->mach_info->modes, fbi->mach_info->num_modes,
fbi->mach_info->default_mode, fbi->mach_info->bpp);
if (err == 0) {
dev_err(info->dev, "No suitable video mode found\n");
err = -EINVAL;
goto failed;
}
if (mach_info->setup) {
err = mach_info->setup(pdev);
if (err)
return err;
}
err = ep93xxfb_check_var(&info->var, info);
if (err)
goto failed;
fbi->clk = clk_get(info->dev, NULL);
if (IS_ERR(fbi->clk)) {
err = PTR_ERR(fbi->clk);
fbi->clk = NULL;
goto failed;
}
ep93xxfb_set_par(info);
clk_enable(fbi->clk);
err = register_framebuffer(info);
if (err)
goto failed;
dev_info(info->dev, "registered. Mode = %dx%d-%d\n",
info->var.xres, info->var.yres, info->var.bits_per_pixel);
return 0;
failed:
if (fbi->clk)
clk_put(fbi->clk);
if (fbi->mmio_base)
iounmap(fbi->mmio_base);
if (fbi->res)
release_mem_region(fbi->res->start, resource_size(fbi->res));
ep93xxfb_dealloc_videomem(info);
if (&info->cmap)
fb_dealloc_cmap(&info->cmap);
if (fbi->mach_info->teardown)
fbi->mach_info->teardown(pdev);
kfree(info);
platform_set_drvdata(pdev, NULL);
return err;
}
static int ep93xxfb_remove(struct platform_device *pdev)
{
struct fb_info *info = platform_get_drvdata(pdev);
struct ep93xx_fbi *fbi = info->par;
unregister_framebuffer(info);
clk_disable(fbi->clk);
clk_put(fbi->clk);
iounmap(fbi->mmio_base);
release_mem_region(fbi->res->start, resource_size(fbi->res));
ep93xxfb_dealloc_videomem(info);
fb_dealloc_cmap(&info->cmap);
if (fbi->mach_info->teardown)
fbi->mach_info->teardown(pdev);
kfree(info);
platform_set_drvdata(pdev, NULL);
return 0;
}
static struct platform_driver ep93xxfb_driver = {
.probe = ep93xxfb_probe,
.remove = ep93xxfb_remove,
.driver = {
.name = "ep93xx-fb",
.owner = THIS_MODULE,
},
};
static int __devinit ep93xxfb_init(void)
{
return platform_driver_register(&ep93xxfb_driver);
}
static void __exit ep93xxfb_exit(void)
{
platform_driver_unregister(&ep93xxfb_driver);
}
module_init(ep93xxfb_init);
module_exit(ep93xxfb_exit);
MODULE_DESCRIPTION("EP93XX Framebuffer Driver");
MODULE_ALIAS("platform:ep93xx-fb");
MODULE_AUTHOR("Ryan Mallon <ryan&bluewatersys.com>, "
"H Hartley Sweeten <hsweeten@visionengravers.com");
MODULE_LICENSE("GPL");

19
drivers/video/fbmem.c
View File

@@ -871,8 +871,8 @@ fb_pan_display(struct fb_info *info, struct fb_var_screeninfo *var)
err = -EINVAL;
if (err || !info->fbops->fb_pan_display ||
var->yoffset + yres > info->var.yres_virtual ||
var->xoffset + info->var.xres > info->var.xres_virtual)
var->yoffset > info->var.yres_virtual - yres ||
var->xoffset > info->var.xres_virtual - info->var.xres)
return -EINVAL;
if ((err = info->fbops->fb_pan_display(var, info)))
@@ -954,6 +954,7 @@ fb_set_var(struct fb_info *info, struct fb_var_screeninfo *var)
goto done;
if ((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW) {
struct fb_var_screeninfo old_var;
struct fb_videomode mode;
if (info->fbops->fb_get_caps) {
@@ -963,10 +964,20 @@ fb_set_var(struct fb_info *info, struct fb_var_screeninfo *var)
goto done;
}
old_var = info->var;
info->var = *var;
if (info->fbops->fb_set_par)
info->fbops->fb_set_par(info);
if (info->fbops->fb_set_par) {
ret = info->fbops->fb_set_par(info);
if (ret) {
info->var = old_var;
printk(KERN_WARNING "detected "
"fb_set_par error, "
"error code: %d\n", ret);
goto done;
}
}
fb_pan_display(info, &info->var);
fb_set_cmap(&info->cmap, info);

2
drivers/video/imxfb.c
View File

@@ -710,7 +710,7 @@ static int __init imxfb_probe(struct platform_device *pdev)
fbi->clk = clk_get(&pdev->dev, NULL);
if (IS_ERR(fbi->clk)) {
ret = PTR_ERR(fbi->clk);;
ret = PTR_ERR(fbi->clk);
dev_err(&pdev->dev, "unable to get clock: %d\n", ret);
goto failed_getclock;
}

209
drivers/video/matrox/g450_pll.c
View File

@@ -25,16 +25,19 @@ static inline unsigned int g450_f2vco(unsigned char p, unsigned int fin) {
return (p & 0x40) ? fin : fin << ((p & 3) + 1);
}
static unsigned int g450_mnp2vco(CPMINFO unsigned int mnp) {
static unsigned int g450_mnp2vco(const struct matrox_fb_info *minfo,
unsigned int mnp)
{
unsigned int m, n;
m = ((mnp >> 16) & 0x0FF) + 1;
n = ((mnp >> 7) & 0x1FE) + 4;
return (ACCESS_FBINFO(features).pll.ref_freq * n + (m >> 1)) / m;
return (minfo->features.pll.ref_freq * n + (m >> 1)) / m;
}
unsigned int g450_mnp2f(CPMINFO unsigned int mnp) {
return g450_vco2f(mnp, g450_mnp2vco(PMINFO mnp));
unsigned int g450_mnp2f(const struct matrox_fb_info *minfo, unsigned int mnp)
{
return g450_vco2f(mnp, g450_mnp2vco(minfo, mnp));
}
static inline unsigned int pll_freq_delta(unsigned int f1, unsigned int f2) {
@@ -49,7 +52,10 @@ static inline unsigned int pll_freq_delta(unsigned int f1, unsigned int f2) {
#define NO_MORE_MNP 0x01FFFFFF
#define G450_MNP_FREQBITS (0xFFFFFF43) /* do not mask high byte so we'll catch NO_MORE_MNP */
static unsigned int g450_nextpll(CPMINFO const struct matrox_pll_limits* pi, unsigned int* fvco, unsigned int mnp) {
static unsigned int g450_nextpll(const struct matrox_fb_info *minfo,
const struct matrox_pll_limits *pi,
unsigned int *fvco, unsigned int mnp)
{
unsigned int m, n, p;
unsigned int tvco = *fvco;
@@ -90,12 +96,15 @@ static unsigned int g450_nextpll(CPMINFO const struct matrox_pll_limits* pi, uns
} else {
m--;
}
n = ((tvco * (m+1) + ACCESS_FBINFO(features).pll.ref_freq) / (ACCESS_FBINFO(features).pll.ref_freq * 2)) - 2;
n = ((tvco * (m+1) + minfo->features.pll.ref_freq) / (minfo->features.pll.ref_freq * 2)) - 2;
} while (n < 0x03 || n > 0x7A);
return (m << 16) | (n << 8) | p;
}
static unsigned int g450_firstpll(CPMINFO const struct matrox_pll_limits* pi, unsigned int* vco, unsigned int fout) {
static unsigned int g450_firstpll(const struct matrox_fb_info *minfo,
const struct matrox_pll_limits *pi,
unsigned int *vco, unsigned int fout)
{
unsigned int p;
unsigned int vcomax;
@@ -121,88 +130,94 @@ static unsigned int g450_firstpll(CPMINFO const struct matrox_pll_limits* pi, un
}
*vco = tvco;
}
return g450_nextpll(PMINFO pi, vco, 0xFF0000 | p);
return g450_nextpll(minfo, pi, vco, 0xFF0000 | p);
}
static inline unsigned int g450_setpll(CPMINFO unsigned int mnp, unsigned int pll) {
static inline unsigned int g450_setpll(const struct matrox_fb_info *minfo,
unsigned int mnp, unsigned int pll)
{
switch (pll) {
case M_PIXEL_PLL_A:
matroxfb_DAC_out(PMINFO M1064_XPIXPLLAM, mnp >> 16);
matroxfb_DAC_out(PMINFO M1064_XPIXPLLAN, mnp >> 8);
matroxfb_DAC_out(PMINFO M1064_XPIXPLLAP, mnp);
matroxfb_DAC_out(minfo, M1064_XPIXPLLAM, mnp >> 16);
matroxfb_DAC_out(minfo, M1064_XPIXPLLAN, mnp >> 8);
matroxfb_DAC_out(minfo, M1064_XPIXPLLAP, mnp);
return M1064_XPIXPLLSTAT;
case M_PIXEL_PLL_B:
matroxfb_DAC_out(PMINFO M1064_XPIXPLLBM, mnp >> 16);
matroxfb_DAC_out(PMINFO M1064_XPIXPLLBN, mnp >> 8);
matroxfb_DAC_out(PMINFO M1064_XPIXPLLBP, mnp);
matroxfb_DAC_out(minfo, M1064_XPIXPLLBM, mnp >> 16);
matroxfb_DAC_out(minfo, M1064_XPIXPLLBN, mnp >> 8);
matroxfb_DAC_out(minfo, M1064_XPIXPLLBP, mnp);
return M1064_XPIXPLLSTAT;
case M_PIXEL_PLL_C:
matroxfb_DAC_out(PMINFO M1064_XPIXPLLCM, mnp >> 16);
matroxfb_DAC_out(PMINFO M1064_XPIXPLLCN, mnp >> 8);
matroxfb_DAC_out(PMINFO M1064_XPIXPLLCP, mnp);
matroxfb_DAC_out(minfo, M1064_XPIXPLLCM, mnp >> 16);
matroxfb_DAC_out(minfo, M1064_XPIXPLLCN, mnp >> 8);
matroxfb_DAC_out(minfo, M1064_XPIXPLLCP, mnp);
return M1064_XPIXPLLSTAT;
case M_SYSTEM_PLL:
matroxfb_DAC_out(PMINFO DAC1064_XSYSPLLM, mnp >> 16);
matroxfb_DAC_out(PMINFO DAC1064_XSYSPLLN, mnp >> 8);
matroxfb_DAC_out(PMINFO DAC1064_XSYSPLLP, mnp);
matroxfb_DAC_out(minfo, DAC1064_XSYSPLLM, mnp >> 16);
matroxfb_DAC_out(minfo, DAC1064_XSYSPLLN, mnp >> 8);
matroxfb_DAC_out(minfo, DAC1064_XSYSPLLP, mnp);
return DAC1064_XSYSPLLSTAT;
case M_VIDEO_PLL:
matroxfb_DAC_out(PMINFO M1064_XVIDPLLM, mnp >> 16);
matroxfb_DAC_out(PMINFO M1064_XVIDPLLN, mnp >> 8);
matroxfb_DAC_out(PMINFO M1064_XVIDPLLP, mnp);
matroxfb_DAC_out(minfo, M1064_XVIDPLLM, mnp >> 16);
matroxfb_DAC_out(minfo, M1064_XVIDPLLN, mnp >> 8);
matroxfb_DAC_out(minfo, M1064_XVIDPLLP, mnp);
return M1064_XVIDPLLSTAT;
}
return 0;
}
static inline unsigned int g450_cmppll(CPMINFO unsigned int mnp, unsigned int pll) {
static inline unsigned int g450_cmppll(const struct matrox_fb_info *minfo,
unsigned int mnp, unsigned int pll)
{
unsigned char m = mnp >> 16;
unsigned char n = mnp >> 8;
unsigned char p = mnp;
switch (pll) {
case M_PIXEL_PLL_A:
return (matroxfb_DAC_in(PMINFO M1064_XPIXPLLAM) != m ||
matroxfb_DAC_in(PMINFO M1064_XPIXPLLAN) != n ||
matroxfb_DAC_in(PMINFO M1064_XPIXPLLAP) != p);
return (matroxfb_DAC_in(minfo, M1064_XPIXPLLAM) != m ||
matroxfb_DAC_in(minfo, M1064_XPIXPLLAN) != n ||
matroxfb_DAC_in(minfo, M1064_XPIXPLLAP) != p);
case M_PIXEL_PLL_B:
return (matroxfb_DAC_in(PMINFO M1064_XPIXPLLBM) != m ||
matroxfb_DAC_in(PMINFO M1064_XPIXPLLBN) != n ||
matroxfb_DAC_in(PMINFO M1064_XPIXPLLBP) != p);
return (matroxfb_DAC_in(minfo, M1064_XPIXPLLBM) != m ||
matroxfb_DAC_in(minfo, M1064_XPIXPLLBN) != n ||
matroxfb_DAC_in(minfo, M1064_XPIXPLLBP) != p);
case M_PIXEL_PLL_C:
return (matroxfb_DAC_in(PMINFO M1064_XPIXPLLCM) != m ||
matroxfb_DAC_in(PMINFO M1064_XPIXPLLCN) != n ||
matroxfb_DAC_in(PMINFO M1064_XPIXPLLCP) != p);
return (matroxfb_DAC_in(minfo, M1064_XPIXPLLCM) != m ||
matroxfb_DAC_in(minfo, M1064_XPIXPLLCN) != n ||
matroxfb_DAC_in(minfo, M1064_XPIXPLLCP) != p);
case M_SYSTEM_PLL:
return (matroxfb_DAC_in(PMINFO DAC1064_XSYSPLLM) != m ||
matroxfb_DAC_in(PMINFO DAC1064_XSYSPLLN) != n ||
matroxfb_DAC_in(PMINFO DAC1064_XSYSPLLP) != p);
return (matroxfb_DAC_in(minfo, DAC1064_XSYSPLLM) != m ||
matroxfb_DAC_in(minfo, DAC1064_XSYSPLLN) != n ||
matroxfb_DAC_in(minfo, DAC1064_XSYSPLLP) != p);
case M_VIDEO_PLL:
return (matroxfb_DAC_in(PMINFO M1064_XVIDPLLM) != m ||
matroxfb_DAC_in(PMINFO M1064_XVIDPLLN) != n ||
matroxfb_DAC_in(PMINFO M1064_XVIDPLLP) != p);
return (matroxfb_DAC_in(minfo, M1064_XVIDPLLM) != m ||
matroxfb_DAC_in(minfo, M1064_XVIDPLLN) != n ||
matroxfb_DAC_in(minfo, M1064_XVIDPLLP) != p);
}
return 1;
}
static inline int g450_isplllocked(CPMINFO unsigned int regidx) {
static inline int g450_isplllocked(const struct matrox_fb_info *minfo,
unsigned int regidx)
{
unsigned int j;
for (j = 0; j < 1000; j++) {
if (matroxfb_DAC_in(PMINFO regidx) & 0x40) {
if (matroxfb_DAC_in(minfo, regidx) & 0x40) {
unsigned int r = 0;
int i;
for (i = 0; i < 100; i++) {
r += matroxfb_DAC_in(PMINFO regidx) & 0x40;
r += matroxfb_DAC_in(minfo, regidx) & 0x40;
}
return r >= (90 * 0x40);
}
@@ -211,8 +226,10 @@ static inline int g450_isplllocked(CPMINFO unsigned int regidx) {
return 0;
}
static int g450_testpll(CPMINFO unsigned int mnp, unsigned int pll) {
return g450_isplllocked(PMINFO g450_setpll(PMINFO mnp, pll));
static int g450_testpll(const struct matrox_fb_info *minfo, unsigned int mnp,
unsigned int pll)
{
return g450_isplllocked(minfo, g450_setpll(minfo, mnp, pll));
}
static void updatehwstate_clk(struct matrox_hw_state* hw, unsigned int mnp, unsigned int pll) {
@@ -225,13 +242,19 @@ static void updatehwstate_clk(struct matrox_hw_state* hw, unsigned int mnp, unsi
}
}
void matroxfb_g450_setpll_cond(WPMINFO unsigned int mnp, unsigned int pll) {
if (g450_cmppll(PMINFO mnp, pll)) {
g450_setpll(PMINFO mnp, pll);
void matroxfb_g450_setpll_cond(struct matrox_fb_info *minfo, unsigned int mnp,
unsigned int pll)
{
if (g450_cmppll(minfo, mnp, pll)) {
g450_setpll(minfo, mnp, pll);
}
}
static inline unsigned int g450_findworkingpll(WPMINFO unsigned int pll, unsigned int* mnparray, unsigned int mnpcount) {
static inline unsigned int g450_findworkingpll(struct matrox_fb_info *minfo,
unsigned int pll,
unsigned int *mnparray,
unsigned int mnpcount)
{
unsigned int found = 0;
unsigned int idx;
unsigned int mnpfound = mnparray[0];
@@ -255,22 +278,22 @@ static inline unsigned int g450_findworkingpll(WPMINFO unsigned int pll, unsigne
while (sptr >= sarray) {
unsigned int mnp = *sptr--;
if (g450_testpll(PMINFO mnp - 0x0300, pll) &&
g450_testpll(PMINFO mnp + 0x0300, pll) &&
g450_testpll(PMINFO mnp - 0x0200, pll) &&
g450_testpll(PMINFO mnp + 0x0200, pll) &&
g450_testpll(PMINFO mnp - 0x0100, pll) &&
g450_testpll(PMINFO mnp + 0x0100, pll)) {
if (g450_testpll(PMINFO mnp, pll)) {
if (g450_testpll(minfo, mnp - 0x0300, pll) &&
g450_testpll(minfo, mnp + 0x0300, pll) &&
g450_testpll(minfo, mnp - 0x0200, pll) &&
g450_testpll(minfo, mnp + 0x0200, pll) &&
g450_testpll(minfo, mnp - 0x0100, pll) &&
g450_testpll(minfo, mnp + 0x0100, pll)) {
if (g450_testpll(minfo, mnp, pll)) {
return mnp;
}
} else if (!found && g450_testpll(PMINFO mnp, pll)) {
} else if (!found && g450_testpll(minfo, mnp, pll)) {
mnpfound = mnp;
found = 1;
}
}
}
g450_setpll(PMINFO mnpfound, pll);
g450_setpll(minfo, mnpfound, pll);
return mnpfound;
}
@@ -283,7 +306,9 @@ static void g450_addcache(struct matrox_pll_cache* ci, unsigned int mnp_key, uns
ci->data[0].mnp_value = mnp_value;
}
static int g450_checkcache(WPMINFO struct matrox_pll_cache* ci, unsigned int mnp_key) {
static int g450_checkcache(struct matrox_fb_info *minfo,
struct matrox_pll_cache *ci, unsigned int mnp_key)
{
unsigned int i;
mnp_key &= G450_MNP_FREQBITS;
@@ -303,8 +328,10 @@ static int g450_checkcache(WPMINFO struct matrox_pll_cache* ci, unsigned int mnp
return NO_MORE_MNP;
}
static int __g450_setclk(WPMINFO unsigned int fout, unsigned int pll,
unsigned int* mnparray, unsigned int* deltaarray) {
static int __g450_setclk(struct matrox_fb_info *minfo, unsigned int fout,
unsigned int pll, unsigned int *mnparray,
unsigned int *deltaarray)
{
unsigned int mnpcount;
unsigned int pixel_vco;
const struct matrox_pll_limits* pi;
@@ -321,19 +348,19 @@ static int __g450_setclk(WPMINFO unsigned int fout, unsigned int pll,
matroxfb_DAC_lock_irqsave(flags);
xpwrctrl = matroxfb_DAC_in(PMINFO M1064_XPWRCTRL);
matroxfb_DAC_out(PMINFO M1064_XPWRCTRL, xpwrctrl & ~M1064_XPWRCTRL_PANELPDN);
xpwrctrl = matroxfb_DAC_in(minfo, M1064_XPWRCTRL);
matroxfb_DAC_out(minfo, M1064_XPWRCTRL, xpwrctrl & ~M1064_XPWRCTRL_PANELPDN);
mga_outb(M_SEQ_INDEX, M_SEQ1);
mga_outb(M_SEQ_DATA, mga_inb(M_SEQ_DATA) | M_SEQ1_SCROFF);
tmp = matroxfb_DAC_in(PMINFO M1064_XPIXCLKCTRL);
tmp = matroxfb_DAC_in(minfo, M1064_XPIXCLKCTRL);
tmp |= M1064_XPIXCLKCTRL_DIS;
if (!(tmp & M1064_XPIXCLKCTRL_PLL_UP)) {
tmp |= M1064_XPIXCLKCTRL_PLL_UP;
}
matroxfb_DAC_out(PMINFO M1064_XPIXCLKCTRL, tmp);
matroxfb_DAC_out(minfo, M1064_XPIXCLKCTRL, tmp);
/* DVI PLL preferred for frequencies up to
panel link max, standard PLL otherwise */
if (fout >= MINFO->max_pixel_clock_panellink)
if (fout >= minfo->max_pixel_clock_panellink)
tmp = 0;
else tmp =
M1064_XDVICLKCTRL_DVIDATAPATHSEL |
@@ -341,8 +368,8 @@ static int __g450_setclk(WPMINFO unsigned int fout, unsigned int pll,
M1064_XDVICLKCTRL_C1DVICLKEN |
M1064_XDVICLKCTRL_DVILOOPCTL |
M1064_XDVICLKCTRL_P1LOOPBWDTCTL;
matroxfb_DAC_out(PMINFO M1064_XDVICLKCTRL,tmp);
matroxfb_DAC_out(PMINFO M1064_XPWRCTRL,
matroxfb_DAC_out(minfo, M1064_XDVICLKCTRL, tmp);
matroxfb_DAC_out(minfo, M1064_XPWRCTRL,
xpwrctrl);
matroxfb_DAC_unlock_irqrestore(flags);
@@ -363,20 +390,20 @@ static int __g450_setclk(WPMINFO unsigned int fout, unsigned int pll,
}
mga_outb(M_MISC_REG, misc);
}
pi = &ACCESS_FBINFO(limits.pixel);
ci = &ACCESS_FBINFO(cache.pixel);
pi = &minfo->limits.pixel;
ci = &minfo->cache.pixel;
break;
case M_SYSTEM_PLL:
{
u_int32_t opt;
pci_read_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, &opt);
pci_read_config_dword(minfo->pcidev, PCI_OPTION_REG, &opt);
if (!(opt & 0x20)) {
pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, opt | 0x20);
pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, opt | 0x20);
}
}
pi = &ACCESS_FBINFO(limits.system);
ci = &ACCESS_FBINFO(cache.system);
pi = &minfo->limits.system;
ci = &minfo->cache.system;
break;
case M_VIDEO_PLL:
{
@@ -385,18 +412,18 @@ static int __g450_setclk(WPMINFO unsigned int fout, unsigned int pll,
unsigned long flags;
matroxfb_DAC_lock_irqsave(flags);
tmp = matroxfb_DAC_in(PMINFO M1064_XPWRCTRL);
tmp = matroxfb_DAC_in(minfo, M1064_XPWRCTRL);
if (!(tmp & 2)) {
matroxfb_DAC_out(PMINFO M1064_XPWRCTRL, tmp | 2);
matroxfb_DAC_out(minfo, M1064_XPWRCTRL, tmp | 2);
}
mnp = matroxfb_DAC_in(PMINFO M1064_XPIXPLLCM) << 16;
mnp |= matroxfb_DAC_in(PMINFO M1064_XPIXPLLCN) << 8;
pixel_vco = g450_mnp2vco(PMINFO mnp);
mnp = matroxfb_DAC_in(minfo, M1064_XPIXPLLCM) << 16;
mnp |= matroxfb_DAC_in(minfo, M1064_XPIXPLLCN) << 8;
pixel_vco = g450_mnp2vco(minfo, mnp);
matroxfb_DAC_unlock_irqrestore(flags);
}
pi = &ACCESS_FBINFO(limits.video);
ci = &ACCESS_FBINFO(cache.video);
pi = &minfo->limits.video;
ci = &minfo->cache.video;
break;
default:
return -EINVAL;
@@ -407,12 +434,12 @@ static int __g450_setclk(WPMINFO unsigned int fout, unsigned int pll,
unsigned int mnp;
unsigned int xvco;
for(mnp = g450_firstpll(PMINFO pi, &xvco, fout); mnp != NO_MORE_MNP; mnp = g450_nextpll(PMINFO pi, &xvco, mnp)) {
for (mnp = g450_firstpll(minfo, pi, &xvco, fout); mnp != NO_MORE_MNP; mnp = g450_nextpll(minfo, pi, &xvco, mnp)) {
unsigned int idx;
unsigned int vco;
unsigned int delta;
vco = g450_mnp2vco(PMINFO mnp);
vco = g450_mnp2vco(minfo, mnp);
#if 0
if (pll == M_VIDEO_PLL) {
unsigned int big, small;
@@ -444,7 +471,7 @@ static int __g450_setclk(WPMINFO unsigned int fout, unsigned int pll,
* (freqs near VCOmin aren't as stable)
*/
if (delta == deltaarray[idx-1]
&& vco != g450_mnp2vco(PMINFO mnparray[idx-1])
&& vco != g450_mnp2vco(minfo, mnparray[idx-1])
&& vco < (pi->vcomin * 17 / 16)) {
break;
}
@@ -468,14 +495,14 @@ static int __g450_setclk(WPMINFO unsigned int fout, unsigned int pll,
unsigned int mnp;
matroxfb_DAC_lock_irqsave(flags);
mnp = g450_checkcache(PMINFO ci, mnparray[0]);
mnp = g450_checkcache(minfo, ci, mnparray[0]);
if (mnp != NO_MORE_MNP) {
matroxfb_g450_setpll_cond(PMINFO mnp, pll);
matroxfb_g450_setpll_cond(minfo, mnp, pll);
} else {
mnp = g450_findworkingpll(PMINFO pll, mnparray, mnpcount);
mnp = g450_findworkingpll(minfo, pll, mnparray, mnpcount);
g450_addcache(ci, mnparray[0], mnp);
}
updatehwstate_clk(&ACCESS_FBINFO(hw), mnp, pll);
updatehwstate_clk(&minfo->hw, mnp, pll);
matroxfb_DAC_unlock_irqrestore(flags);
return mnp;
}
@@ -485,14 +512,16 @@ static int __g450_setclk(WPMINFO unsigned int fout, unsigned int pll,
* Currently there is 5(p) * 10(m) = 50 possible values. */
#define MNP_TABLE_SIZE 64
int matroxfb_g450_setclk(WPMINFO unsigned int fout, unsigned int pll) {
int matroxfb_g450_setclk(struct matrox_fb_info *minfo, unsigned int fout,
unsigned int pll)
{
unsigned int* arr;
arr = kmalloc(sizeof(*arr) * MNP_TABLE_SIZE * 2, GFP_KERNEL);
if (arr) {
int r;
r = __g450_setclk(PMINFO fout, pll, arr, arr + MNP_TABLE_SIZE);
r = __g450_setclk(minfo, fout, pll, arr, arr + MNP_TABLE_SIZE);
kfree(arr);
return r;
}

8
drivers/video/matrox/g450_pll.h
View File

@@ -3,8 +3,10 @@
#include "matroxfb_base.h"
int matroxfb_g450_setclk(WPMINFO unsigned int fout, unsigned int pll);
unsigned int g450_mnp2f(CPMINFO unsigned int mnp);
void matroxfb_g450_setpll_cond(WPMINFO unsigned int mnp, unsigned int pll);
int matroxfb_g450_setclk(struct matrox_fb_info *minfo, unsigned int fout,
unsigned int pll);
unsigned int g450_mnp2f(const struct matrox_fb_info *minfo, unsigned int mnp);
void matroxfb_g450_setpll_cond(struct matrox_fb_info *minfo, unsigned int mnp,
unsigned int pll);
#endif /* __G450_PLL_H__ */

18
drivers/video/matrox/i2c-matroxfb.c
View File

@@ -41,7 +41,7 @@ static int matroxfb_read_gpio(struct matrox_fb_info* minfo) {
int v;
matroxfb_DAC_lock_irqsave(flags);
v = matroxfb_DAC_in(PMINFO DAC_XGENIODATA);
v = matroxfb_DAC_in(minfo, DAC_XGENIODATA);
matroxfb_DAC_unlock_irqrestore(flags);
return v;
}
@@ -51,10 +51,10 @@ static void matroxfb_set_gpio(struct matrox_fb_info* minfo, int mask, int val) {
int v;
matroxfb_DAC_lock_irqsave(flags);
v = (matroxfb_DAC_in(PMINFO DAC_XGENIOCTRL) & mask) | val;
matroxfb_DAC_out(PMINFO DAC_XGENIOCTRL, v);
v = (matroxfb_DAC_in(minfo, DAC_XGENIOCTRL) & mask) | val;
matroxfb_DAC_out(minfo, DAC_XGENIOCTRL, v);
/* We must reset GENIODATA very often... XFree plays with this register */
matroxfb_DAC_out(PMINFO DAC_XGENIODATA, 0x00);
matroxfb_DAC_out(minfo, DAC_XGENIODATA, 0x00);
matroxfb_DAC_unlock_irqrestore(flags);
}
@@ -112,7 +112,7 @@ static int i2c_bus_reg(struct i2c_bit_adapter* b, struct matrox_fb_info* minfo,
i2c_set_adapdata(&b->adapter, b);
b->adapter.class = class;
b->adapter.algo_data = &b->bac;
b->adapter.dev.parent = &ACCESS_FBINFO(pcidev)->dev;
b->adapter.dev.parent = &minfo->pcidev->dev;
b->bac = matrox_i2c_algo_template;
b->bac.data = b;
err = i2c_bit_add_bus(&b->adapter);
@@ -149,11 +149,11 @@ static void* i2c_matroxfb_probe(struct matrox_fb_info* minfo) {
return NULL;
matroxfb_DAC_lock_irqsave(flags);
matroxfb_DAC_out(PMINFO DAC_XGENIODATA, 0xFF);
matroxfb_DAC_out(PMINFO DAC_XGENIOCTRL, 0x00);
matroxfb_DAC_out(minfo, DAC_XGENIODATA, 0xFF);
matroxfb_DAC_out(minfo, DAC_XGENIOCTRL, 0x00);
matroxfb_DAC_unlock_irqrestore(flags);
switch (ACCESS_FBINFO(chip)) {
switch (minfo->chip) {
case MGA_2064:
case MGA_2164:
err = i2c_bus_reg(&m2info->ddc1, minfo,
@@ -168,7 +168,7 @@ static void* i2c_matroxfb_probe(struct matrox_fb_info* minfo) {
}
if (err)
goto fail_ddc1;
if (ACCESS_FBINFO(devflags.dualhead)) {
if (minfo->devflags.dualhead) {
err = i2c_bus_reg(&m2info->ddc2, minfo,
DDC2_DATA, DDC2_CLK,
"DDC:fb%u #1", I2C_CLASS_DDC);

612
drivers/video/matrox/matroxfb_DAC1064.c
View File

File diff suppressed because it is too large Load Diff

4
drivers/video/matrox/matroxfb_DAC1064.h
View File

@@ -11,8 +11,8 @@ extern struct matrox_switch matrox_mystique;
extern struct matrox_switch matrox_G100;
#endif
#ifdef NEED_DAC1064
void DAC1064_global_init(WPMINFO2);
void DAC1064_global_restore(WPMINFO2);
void DAC1064_global_init(struct matrox_fb_info *minfo);
void DAC1064_global_restore(struct matrox_fb_info *minfo);
#endif
#define M1064_INDEX 0x00

258
drivers/video/matrox/matroxfb_Ti3026.c
View File

@@ -279,27 +279,31 @@ static const unsigned char MGADACbpp32[] =
TVP3026_XCOLKEYCTRL_ZOOM1,
0x00, 0x00, TVP3026_XCURCTRL_DIS };
static int Ti3026_calcclock(CPMINFO unsigned int freq, unsigned int fmax, int* in, int* feed, int* post) {
static int Ti3026_calcclock(const struct matrox_fb_info *minfo,
unsigned int freq, unsigned int fmax, int *in,
int *feed, int *post)
{
unsigned int fvco;
unsigned int lin, lfeed, lpost;
DBG(__func__)
fvco = PLL_calcclock(PMINFO freq, fmax, &lin, &lfeed, &lpost);
fvco = PLL_calcclock(minfo, freq, fmax, &lin, &lfeed, &lpost);
fvco >>= (*post = lpost);
*in = 64 - lin;
*feed = 64 - lfeed;
return fvco;
}
static int Ti3026_setpclk(WPMINFO int clk) {
static int Ti3026_setpclk(struct matrox_fb_info *minfo, int clk)
{
unsigned int f_pll;
unsigned int pixfeed, pixin, pixpost;
struct matrox_hw_state* hw = &ACCESS_FBINFO(hw);
struct matrox_hw_state *hw = &minfo->hw;
DBG(__func__)
f_pll = Ti3026_calcclock(PMINFO clk, ACCESS_FBINFO(max_pixel_clock), &pixin, &pixfeed, &pixpost);
f_pll = Ti3026_calcclock(minfo, clk, minfo->max_pixel_clock, &pixin, &pixfeed, &pixpost);
hw->DACclk[0] = pixin | 0xC0;
hw->DACclk[1] = pixfeed;
@@ -309,9 +313,9 @@ static int Ti3026_setpclk(WPMINFO int clk) {
unsigned int loopfeed, loopin, looppost, loopdiv, z;
unsigned int Bpp;
Bpp = ACCESS_FBINFO(curr.final_bppShift);
Bpp = minfo->curr.final_bppShift;
if (ACCESS_FBINFO(fbcon).var.bits_per_pixel == 24) {
if (minfo->fbcon.var.bits_per_pixel == 24) {
loopfeed = 3; /* set lm to any possible value */
loopin = 3 * 32 / Bpp;
} else {
@@ -330,18 +334,18 @@ static int Ti3026_setpclk(WPMINFO int clk) {
looppost = 3;
loopdiv = z/16;
}
if (ACCESS_FBINFO(fbcon).var.bits_per_pixel == 24) {
if (minfo->fbcon.var.bits_per_pixel == 24) {
hw->DACclk[3] = ((65 - loopin) & 0x3F) | 0xC0;
hw->DACclk[4] = (65 - loopfeed) | 0x80;
if (ACCESS_FBINFO(accel.ramdac_rev) > 0x20) {
if (isInterleave(MINFO))
if (minfo->accel.ramdac_rev > 0x20) {
if (isInterleave(minfo))
hw->DACreg[POS3026_XLATCHCTRL] = TVP3026B_XLATCHCTRL_8_3;
else {
hw->DACclk[4] &= ~0xC0;
hw->DACreg[POS3026_XLATCHCTRL] = TVP3026B_XLATCHCTRL_4_3;
}
} else {
if (isInterleave(MINFO))
if (isInterleave(minfo))
; /* default... */
else {
hw->DACclk[4] ^= 0xC0; /* change from 0x80 to 0x40 */
@@ -349,7 +353,7 @@ static int Ti3026_setpclk(WPMINFO int clk) {
}
}
hw->DACclk[5] = looppost | 0xF8;
if (ACCESS_FBINFO(devflags.mga_24bpp_fix))
if (minfo->devflags.mga_24bpp_fix)
hw->DACclk[5] ^= 0x40;
} else {
hw->DACclk[3] = ((65 - loopin) & 0x3F) | 0xC0;
@@ -361,14 +365,15 @@ static int Ti3026_setpclk(WPMINFO int clk) {
return 0;
}
static int Ti3026_init(WPMINFO struct my_timming* m) {
u_int8_t muxctrl = isInterleave(MINFO) ? TVP3026_XMUXCTRL_MEMORY_64BIT : TVP3026_XMUXCTRL_MEMORY_32BIT;
struct matrox_hw_state* hw = &ACCESS_FBINFO(hw);
static int Ti3026_init(struct matrox_fb_info *minfo, struct my_timming *m)
{
u_int8_t muxctrl = isInterleave(minfo) ? TVP3026_XMUXCTRL_MEMORY_64BIT : TVP3026_XMUXCTRL_MEMORY_32BIT;
struct matrox_hw_state *hw = &minfo->hw;
DBG(__func__)
memcpy(hw->DACreg, MGADACbpp32, sizeof(hw->DACreg));
switch (ACCESS_FBINFO(fbcon).var.bits_per_pixel) {
switch (minfo->fbcon.var.bits_per_pixel) {
case 4: hw->DACreg[POS3026_XLATCHCTRL] = TVP3026_XLATCHCTRL_16_1; /* or _8_1, they are same */
hw->DACreg[POS3026_XTRUECOLORCTRL] = TVP3026_XTRUECOLORCTRL_PSEUDOCOLOR;
hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_4BIT;
@@ -383,7 +388,7 @@ static int Ti3026_init(WPMINFO struct my_timming* m) {
break;
case 16:
/* XLATCHCTRL should be _4_1 / _2_1... Why is not? (_2_1 is used everytime) */
hw->DACreg[POS3026_XTRUECOLORCTRL] = (ACCESS_FBINFO(fbcon).var.green.length == 5)? (TVP3026_XTRUECOLORCTRL_DIRECTCOLOR | TVP3026_XTRUECOLORCTRL_ORGB_1555 ) : (TVP3026_XTRUECOLORCTRL_DIRECTCOLOR | TVP3026_XTRUECOLORCTRL_RGB_565);
hw->DACreg[POS3026_XTRUECOLORCTRL] = (minfo->fbcon.var.green.length == 5) ? (TVP3026_XTRUECOLORCTRL_DIRECTCOLOR | TVP3026_XTRUECOLORCTRL_ORGB_1555) : (TVP3026_XTRUECOLORCTRL_DIRECTCOLOR | TVP3026_XTRUECOLORCTRL_RGB_565);
hw->DACreg[POS3026_XMUXCTRL] = muxctrl | TVP3026_XMUXCTRL_PIXEL_16BIT;
hw->DACreg[POS3026_XCLKCTRL] = TVP3026_XCLKCTRL_SRC_PLL | TVP3026_XCLKCTRL_DIV2;
break;
@@ -400,7 +405,7 @@ static int Ti3026_init(WPMINFO struct my_timming* m) {
default:
return 1; /* TODO: failed */
}
if (matroxfb_vgaHWinit(PMINFO m)) return 1;
if (matroxfb_vgaHWinit(minfo, m)) return 1;
/* set SYNC */
hw->MiscOutReg = 0xCB;
@@ -412,9 +417,9 @@ static int Ti3026_init(WPMINFO struct my_timming* m) {
hw->DACreg[POS3026_XGENCTRL] |= TVP3026_XGENCTRL_SYNC_ON_GREEN;
/* set DELAY */
if (ACCESS_FBINFO(video.len) < 0x400000)
if (minfo->video.len < 0x400000)
hw->CRTCEXT[3] |= 0x08;
else if (ACCESS_FBINFO(video.len) > 0x400000)
else if (minfo->video.len > 0x400000)
hw->CRTCEXT[3] |= 0x10;
/* set HWCURSOR */
@@ -426,14 +431,15 @@ static int Ti3026_init(WPMINFO struct my_timming* m) {
/* set interleaving */
hw->MXoptionReg &= ~0x00001000;
if (isInterleave(MINFO)) hw->MXoptionReg |= 0x00001000;
if (isInterleave(minfo)) hw->MXoptionReg |= 0x00001000;
/* set DAC */
Ti3026_setpclk(PMINFO m->pixclock);
Ti3026_setpclk(minfo, m->pixclock);
return 0;
}
static void ti3026_setMCLK(WPMINFO int fout){
static void ti3026_setMCLK(struct matrox_fb_info *minfo, int fout)
{
unsigned int f_pll;
unsigned int pclk_m, pclk_n, pclk_p;
unsigned int mclk_m, mclk_n, mclk_p;
@@ -442,29 +448,29 @@ static void ti3026_setMCLK(WPMINFO int fout){
DBG(__func__)
f_pll = Ti3026_calcclock(PMINFO fout, ACCESS_FBINFO(max_pixel_clock), &mclk_n, &mclk_m, &mclk_p);
f_pll = Ti3026_calcclock(minfo, fout, minfo->max_pixel_clock, &mclk_n, &mclk_m, &mclk_p);
/* save pclk */
outTi3026(PMINFO TVP3026_XPLLADDR, 0xFC);
pclk_n = inTi3026(PMINFO TVP3026_XPIXPLLDATA);
outTi3026(PMINFO TVP3026_XPLLADDR, 0xFD);
pclk_m = inTi3026(PMINFO TVP3026_XPIXPLLDATA);
outTi3026(PMINFO TVP3026_XPLLADDR, 0xFE);
pclk_p = inTi3026(PMINFO TVP3026_XPIXPLLDATA);
outTi3026(minfo, TVP3026_XPLLADDR, 0xFC);
pclk_n = inTi3026(minfo, TVP3026_XPIXPLLDATA);
outTi3026(minfo, TVP3026_XPLLADDR, 0xFD);
pclk_m = inTi3026(minfo, TVP3026_XPIXPLLDATA);
outTi3026(minfo, TVP3026_XPLLADDR, 0xFE);
pclk_p = inTi3026(minfo, TVP3026_XPIXPLLDATA);
/* stop pclk */
outTi3026(PMINFO TVP3026_XPLLADDR, 0xFE);
outTi3026(PMINFO TVP3026_XPIXPLLDATA, 0x00);
outTi3026(minfo, TVP3026_XPLLADDR, 0xFE);
outTi3026(minfo, TVP3026_XPIXPLLDATA, 0x00);
/* set pclk to new mclk */
outTi3026(PMINFO TVP3026_XPLLADDR, 0xFC);
outTi3026(PMINFO TVP3026_XPIXPLLDATA, mclk_n | 0xC0);
outTi3026(PMINFO TVP3026_XPIXPLLDATA, mclk_m);
outTi3026(PMINFO TVP3026_XPIXPLLDATA, mclk_p | 0xB0);
outTi3026(minfo, TVP3026_XPLLADDR, 0xFC);
outTi3026(minfo, TVP3026_XPIXPLLDATA, mclk_n | 0xC0);
outTi3026(minfo, TVP3026_XPIXPLLDATA, mclk_m);
outTi3026(minfo, TVP3026_XPIXPLLDATA, mclk_p | 0xB0);
/* wait for PLL to lock */
for (tmout = 500000; tmout; tmout--) {
if (inTi3026(PMINFO TVP3026_XPIXPLLDATA) & 0x40)
if (inTi3026(minfo, TVP3026_XPIXPLLDATA) & 0x40)
break;
udelay(10);
};
@@ -472,23 +478,23 @@ static void ti3026_setMCLK(WPMINFO int fout){
printk(KERN_ERR "matroxfb: Temporary pixel PLL not locked after 5 secs\n");
/* output pclk on mclk pin */
mclk_ctl = inTi3026(PMINFO TVP3026_XMEMPLLCTRL);
outTi3026(PMINFO TVP3026_XMEMPLLCTRL, mclk_ctl & 0xE7);
outTi3026(PMINFO TVP3026_XMEMPLLCTRL, (mclk_ctl & 0xE7) | TVP3026_XMEMPLLCTRL_STROBEMKC4);
mclk_ctl = inTi3026(minfo, TVP3026_XMEMPLLCTRL);
outTi3026(minfo, TVP3026_XMEMPLLCTRL, mclk_ctl & 0xE7);
outTi3026(minfo, TVP3026_XMEMPLLCTRL, (mclk_ctl & 0xE7) | TVP3026_XMEMPLLCTRL_STROBEMKC4);
/* stop MCLK */
outTi3026(PMINFO TVP3026_XPLLADDR, 0xFB);
outTi3026(PMINFO TVP3026_XMEMPLLDATA, 0x00);
outTi3026(minfo, TVP3026_XPLLADDR, 0xFB);
outTi3026(minfo, TVP3026_XMEMPLLDATA, 0x00);
/* set mclk to new freq */
outTi3026(PMINFO TVP3026_XPLLADDR, 0xF3);
outTi3026(PMINFO TVP3026_XMEMPLLDATA, mclk_n | 0xC0);
outTi3026(PMINFO TVP3026_XMEMPLLDATA, mclk_m);
outTi3026(PMINFO TVP3026_XMEMPLLDATA, mclk_p | 0xB0);
outTi3026(minfo, TVP3026_XPLLADDR, 0xF3);
outTi3026(minfo, TVP3026_XMEMPLLDATA, mclk_n | 0xC0);
outTi3026(minfo, TVP3026_XMEMPLLDATA, mclk_m);
outTi3026(minfo, TVP3026_XMEMPLLDATA, mclk_p | 0xB0);
/* wait for PLL to lock */
for (tmout = 500000; tmout; tmout--) {
if (inTi3026(PMINFO TVP3026_XMEMPLLDATA) & 0x40)
if (inTi3026(minfo, TVP3026_XMEMPLLDATA) & 0x40)
break;
udelay(10);
}
@@ -496,7 +502,7 @@ static void ti3026_setMCLK(WPMINFO int fout){
printk(KERN_ERR "matroxfb: Memory PLL not locked after 5 secs\n");
f_pll = f_pll * 333 / (10000 << mclk_p);
if (isMilleniumII(MINFO)) {
if (isMilleniumII(minfo)) {
rfhcnt = (f_pll - 128) / 256;
if (rfhcnt > 15)
rfhcnt = 15;
@@ -505,26 +511,26 @@ static void ti3026_setMCLK(WPMINFO int fout){
if (rfhcnt > 15)
rfhcnt = 0;
}
ACCESS_FBINFO(hw).MXoptionReg = (ACCESS_FBINFO(hw).MXoptionReg & ~0x000F0000) | (rfhcnt << 16);
pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, ACCESS_FBINFO(hw).MXoptionReg);
minfo->hw.MXoptionReg = (minfo->hw.MXoptionReg & ~0x000F0000) | (rfhcnt << 16);
pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, minfo->hw.MXoptionReg);
/* output MCLK to MCLK pin */
outTi3026(PMINFO TVP3026_XMEMPLLCTRL, (mclk_ctl & 0xE7) | TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL);
outTi3026(PMINFO TVP3026_XMEMPLLCTRL, (mclk_ctl ) | TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL | TVP3026_XMEMPLLCTRL_STROBEMKC4);
outTi3026(minfo, TVP3026_XMEMPLLCTRL, (mclk_ctl & 0xE7) | TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL);
outTi3026(minfo, TVP3026_XMEMPLLCTRL, (mclk_ctl ) | TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL | TVP3026_XMEMPLLCTRL_STROBEMKC4);
/* stop PCLK */
outTi3026(PMINFO TVP3026_XPLLADDR, 0xFE);
outTi3026(PMINFO TVP3026_XPIXPLLDATA, 0x00);
outTi3026(minfo, TVP3026_XPLLADDR, 0xFE);
outTi3026(minfo, TVP3026_XPIXPLLDATA, 0x00);
/* restore pclk */
outTi3026(PMINFO TVP3026_XPLLADDR, 0xFC);
outTi3026(PMINFO TVP3026_XPIXPLLDATA, pclk_n);
outTi3026(PMINFO TVP3026_XPIXPLLDATA, pclk_m);
outTi3026(PMINFO TVP3026_XPIXPLLDATA, pclk_p);
outTi3026(minfo, TVP3026_XPLLADDR, 0xFC);
outTi3026(minfo, TVP3026_XPIXPLLDATA, pclk_n);
outTi3026(minfo, TVP3026_XPIXPLLDATA, pclk_m);
outTi3026(minfo, TVP3026_XPIXPLLDATA, pclk_p);
/* wait for PLL to lock */
for (tmout = 500000; tmout; tmout--) {
if (inTi3026(PMINFO TVP3026_XPIXPLLDATA) & 0x40)
if (inTi3026(minfo, TVP3026_XPIXPLLDATA) & 0x40)
break;
udelay(10);
}
@@ -532,26 +538,27 @@ static void ti3026_setMCLK(WPMINFO int fout){
printk(KERN_ERR "matroxfb: Pixel PLL not locked after 5 secs\n");
}
static void ti3026_ramdac_init(WPMINFO2) {
static void ti3026_ramdac_init(struct matrox_fb_info *minfo)
{
DBG(__func__)
ACCESS_FBINFO(features.pll.vco_freq_min) = 110000;
ACCESS_FBINFO(features.pll.ref_freq) = 114545;
ACCESS_FBINFO(features.pll.feed_div_min) = 2;
ACCESS_FBINFO(features.pll.feed_div_max) = 24;
ACCESS_FBINFO(features.pll.in_div_min) = 2;
ACCESS_FBINFO(features.pll.in_div_max) = 63;
ACCESS_FBINFO(features.pll.post_shift_max) = 3;
if (ACCESS_FBINFO(devflags.noinit))
minfo->features.pll.vco_freq_min = 110000;
minfo->features.pll.ref_freq = 114545;
minfo->features.pll.feed_div_min = 2;
minfo->features.pll.feed_div_max = 24;
minfo->features.pll.in_div_min = 2;
minfo->features.pll.in_div_max = 63;
minfo->features.pll.post_shift_max = 3;
if (minfo->devflags.noinit)
return;
ti3026_setMCLK(PMINFO 60000);
ti3026_setMCLK(minfo, 60000);
}
static void Ti3026_restore(WPMINFO2) {
static void Ti3026_restore(struct matrox_fb_info *minfo)
{
int i;
unsigned char progdac[6];
struct matrox_hw_state* hw = &ACCESS_FBINFO(hw);
struct matrox_hw_state *hw = &minfo->hw;
CRITFLAGS
DBG(__func__)
@@ -565,31 +572,31 @@ static void Ti3026_restore(WPMINFO2) {
CRITBEGIN
pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, hw->MXoptionReg);
pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
CRITEND
matroxfb_vgaHWrestore(PMINFO2);
matroxfb_vgaHWrestore(minfo);
CRITBEGIN
ACCESS_FBINFO(crtc1.panpos) = -1;
minfo->crtc1.panpos = -1;
for (i = 0; i < 6; i++)
mga_setr(M_EXTVGA_INDEX, i, hw->CRTCEXT[i]);
for (i = 0; i < 21; i++) {
outTi3026(PMINFO DACseq[i], hw->DACreg[i]);
outTi3026(minfo, DACseq[i], hw->DACreg[i]);
}
outTi3026(PMINFO TVP3026_XPLLADDR, 0x00);
progdac[0] = inTi3026(PMINFO TVP3026_XPIXPLLDATA);
progdac[3] = inTi3026(PMINFO TVP3026_XLOOPPLLDATA);
outTi3026(PMINFO TVP3026_XPLLADDR, 0x15);
progdac[1] = inTi3026(PMINFO TVP3026_XPIXPLLDATA);
progdac[4] = inTi3026(PMINFO TVP3026_XLOOPPLLDATA);
outTi3026(PMINFO TVP3026_XPLLADDR, 0x2A);
progdac[2] = inTi3026(PMINFO TVP3026_XPIXPLLDATA);
progdac[5] = inTi3026(PMINFO TVP3026_XLOOPPLLDATA);
outTi3026(minfo, TVP3026_XPLLADDR, 0x00);
progdac[0] = inTi3026(minfo, TVP3026_XPIXPLLDATA);
progdac[3] = inTi3026(minfo, TVP3026_XLOOPPLLDATA);
outTi3026(minfo, TVP3026_XPLLADDR, 0x15);
progdac[1] = inTi3026(minfo, TVP3026_XPIXPLLDATA);
progdac[4] = inTi3026(minfo, TVP3026_XLOOPPLLDATA);
outTi3026(minfo, TVP3026_XPLLADDR, 0x2A);
progdac[2] = inTi3026(minfo, TVP3026_XPIXPLLDATA);
progdac[5] = inTi3026(minfo, TVP3026_XLOOPPLLDATA);
CRITEND
if (memcmp(hw->DACclk, progdac, 6)) {
@@ -598,20 +605,20 @@ static void Ti3026_restore(WPMINFO2) {
/* Maybe even we should call schedule() ? */
CRITBEGIN
outTi3026(PMINFO TVP3026_XCLKCTRL, hw->DACreg[POS3026_XCLKCTRL]);
outTi3026(PMINFO TVP3026_XPLLADDR, 0x2A);
outTi3026(PMINFO TVP3026_XLOOPPLLDATA, 0);
outTi3026(PMINFO TVP3026_XPIXPLLDATA, 0);
outTi3026(minfo, TVP3026_XCLKCTRL, hw->DACreg[POS3026_XCLKCTRL]);
outTi3026(minfo, TVP3026_XPLLADDR, 0x2A);
outTi3026(minfo, TVP3026_XLOOPPLLDATA, 0);
outTi3026(minfo, TVP3026_XPIXPLLDATA, 0);
outTi3026(PMINFO TVP3026_XPLLADDR, 0x00);
outTi3026(minfo, TVP3026_XPLLADDR, 0x00);
for (i = 0; i < 3; i++)
outTi3026(PMINFO TVP3026_XPIXPLLDATA, hw->DACclk[i]);
outTi3026(minfo, TVP3026_XPIXPLLDATA, hw->DACclk[i]);
/* wait for PLL only if PLL clock requested (always for PowerMode, never for VGA) */
if (hw->MiscOutReg & 0x08) {
int tmout;
outTi3026(PMINFO TVP3026_XPLLADDR, 0x3F);
outTi3026(minfo, TVP3026_XPLLADDR, 0x3F);
for (tmout = 500000; tmout; --tmout) {
if (inTi3026(PMINFO TVP3026_XPIXPLLDATA) & 0x40)
if (inTi3026(minfo, TVP3026_XPIXPLLDATA) & 0x40)
break;
udelay(10);
}
@@ -624,18 +631,18 @@ static void Ti3026_restore(WPMINFO2) {
dprintk(KERN_INFO "PixelPLL: %d\n", 500000-tmout);
CRITBEGIN
}
outTi3026(PMINFO TVP3026_XMEMPLLCTRL, hw->DACreg[POS3026_XMEMPLLCTRL]);
outTi3026(PMINFO TVP3026_XPLLADDR, 0x00);
outTi3026(minfo, TVP3026_XMEMPLLCTRL, hw->DACreg[POS3026_XMEMPLLCTRL]);
outTi3026(minfo, TVP3026_XPLLADDR, 0x00);
for (i = 3; i < 6; i++)
outTi3026(PMINFO TVP3026_XLOOPPLLDATA, hw->DACclk[i]);
outTi3026(minfo, TVP3026_XLOOPPLLDATA, hw->DACclk[i]);
CRITEND
if ((hw->MiscOutReg & 0x08) && ((hw->DACclk[5] & 0x80) == 0x80)) {
int tmout;
CRITBEGIN
outTi3026(PMINFO TVP3026_XPLLADDR, 0x3F);
outTi3026(minfo, TVP3026_XPLLADDR, 0x3F);
for (tmout = 500000; tmout; --tmout) {
if (inTi3026(PMINFO TVP3026_XLOOPPLLDATA) & 0x40)
if (inTi3026(minfo, TVP3026_XLOOPPLLDATA) & 0x40)
break;
udelay(10);
}
@@ -660,65 +667,66 @@ static void Ti3026_restore(WPMINFO2) {
#endif
}
static void Ti3026_reset(WPMINFO2) {
static void Ti3026_reset(struct matrox_fb_info *minfo)
{
DBG(__func__)
ti3026_ramdac_init(PMINFO2);
ti3026_ramdac_init(minfo);
}
static struct matrox_altout ti3026_output = {
.name = "Primary output",
};
static int Ti3026_preinit(WPMINFO2) {
static int Ti3026_preinit(struct matrox_fb_info *minfo)
{
static const int vxres_mill2[] = { 512, 640, 768, 800, 832, 960,
1024, 1152, 1280, 1600, 1664, 1920,
2048, 0};
static const int vxres_mill1[] = { 640, 768, 800, 960,
1024, 1152, 1280, 1600, 1920,
2048, 0};
struct matrox_hw_state* hw = &ACCESS_FBINFO(hw);
struct matrox_hw_state *hw = &minfo->hw;
DBG(__func__)
ACCESS_FBINFO(millenium) = 1;
ACCESS_FBINFO(milleniumII) = (ACCESS_FBINFO(pcidev)->device != PCI_DEVICE_ID_MATROX_MIL);
ACCESS_FBINFO(capable.cfb4) = 1;
ACCESS_FBINFO(capable.text) = 1; /* isMilleniumII(MINFO); */
ACCESS_FBINFO(capable.vxres) = isMilleniumII(MINFO)?vxres_mill2:vxres_mill1;
minfo->millenium = 1;
minfo->milleniumII = (minfo->pcidev->device != PCI_DEVICE_ID_MATROX_MIL);
minfo->capable.cfb4 = 1;
minfo->capable.text = 1; /* isMilleniumII(minfo); */
minfo->capable.vxres = isMilleniumII(minfo) ? vxres_mill2 : vxres_mill1;
ACCESS_FBINFO(outputs[0]).data = MINFO;
ACCESS_FBINFO(outputs[0]).output = &ti3026_output;
ACCESS_FBINFO(outputs[0]).src = ACCESS_FBINFO(outputs[0]).default_src;
ACCESS_FBINFO(outputs[0]).mode = MATROXFB_OUTPUT_MODE_MONITOR;
minfo->outputs[0].data = minfo;
minfo->outputs[0].output = &ti3026_output;
minfo->outputs[0].src = minfo->outputs[0].default_src;
minfo->outputs[0].mode = MATROXFB_OUTPUT_MODE_MONITOR;
if (ACCESS_FBINFO(devflags.noinit))
if (minfo->devflags.noinit)
return 0;
/* preserve VGA I/O, BIOS and PPC */
hw->MXoptionReg &= 0xC0000100;
hw->MXoptionReg |= 0x002C0000;
if (ACCESS_FBINFO(devflags.novga))
if (minfo->devflags.novga)
hw->MXoptionReg &= ~0x00000100;
if (ACCESS_FBINFO(devflags.nobios))
if (minfo->devflags.nobios)
hw->MXoptionReg &= ~0x40000000;
if (ACCESS_FBINFO(devflags.nopciretry))
if (minfo->devflags.nopciretry)
hw->MXoptionReg |= 0x20000000;
pci_write_config_dword(ACCESS_FBINFO(pcidev), PCI_OPTION_REG, hw->MXoptionReg);
pci_write_config_dword(minfo->pcidev, PCI_OPTION_REG, hw->MXoptionReg);
ACCESS_FBINFO(accel.ramdac_rev) = inTi3026(PMINFO TVP3026_XSILICONREV);
minfo->accel.ramdac_rev = inTi3026(minfo, TVP3026_XSILICONREV);
outTi3026(PMINFO TVP3026_XCLKCTRL, TVP3026_XCLKCTRL_SRC_CLK0VGA | TVP3026_XCLKCTRL_CLKSTOPPED);
outTi3026(PMINFO TVP3026_XTRUECOLORCTRL, TVP3026_XTRUECOLORCTRL_PSEUDOCOLOR);
outTi3026(PMINFO TVP3026_XMUXCTRL, TVP3026_XMUXCTRL_VGA);
outTi3026(minfo, TVP3026_XCLKCTRL, TVP3026_XCLKCTRL_SRC_CLK0VGA | TVP3026_XCLKCTRL_CLKSTOPPED);
outTi3026(minfo, TVP3026_XTRUECOLORCTRL, TVP3026_XTRUECOLORCTRL_PSEUDOCOLOR);
outTi3026(minfo, TVP3026_XMUXCTRL, TVP3026_XMUXCTRL_VGA);
outTi3026(PMINFO TVP3026_XPLLADDR, 0x2A);
outTi3026(PMINFO TVP3026_XLOOPPLLDATA, 0x00);
outTi3026(PMINFO TVP3026_XPIXPLLDATA, 0x00);
outTi3026(minfo, TVP3026_XPLLADDR, 0x2A);
outTi3026(minfo, TVP3026_XLOOPPLLDATA, 0x00);
outTi3026(minfo, TVP3026_XPIXPLLDATA, 0x00);
mga_outb(M_MISC_REG, 0x67);
outTi3026(PMINFO TVP3026_XMEMPLLCTRL, TVP3026_XMEMPLLCTRL_STROBEMKC4 | TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL);
outTi3026(minfo, TVP3026_XMEMPLLCTRL, TVP3026_XMEMPLLCTRL_STROBEMKC4 | TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL);
mga_outl(M_RESET, 1);
udelay(250);

129
drivers/video/matrox/matroxfb_accel.c
View File

@@ -81,7 +81,7 @@
#include "matroxfb_Ti3026.h"
#include "matroxfb_misc.h"
#define curr_ydstorg(x) ACCESS_FBINFO2(x, curr.ydstorg.pixels)
#define curr_ydstorg(x) ((x)->curr.ydstorg.pixels)
#define mga_ydstlen(y,l) mga_outl(M_YDSTLEN | M_EXEC, ((y) << 16) | (l))
@@ -107,7 +107,8 @@ static void matroxfb_imageblit(struct fb_info* info, const struct fb_image* imag
static void matroxfb_cfb4_fillrect(struct fb_info* info, const struct fb_fillrect* rect);
static void matroxfb_cfb4_copyarea(struct fb_info* info, const struct fb_copyarea* area);
void matrox_cfbX_init(WPMINFO2) {
void matrox_cfbX_init(struct matrox_fb_info *minfo)
{
u_int32_t maccess;
u_int32_t mpitch;
u_int32_t mopmode;
@@ -115,59 +116,59 @@ void matrox_cfbX_init(WPMINFO2) {
DBG(__func__)
mpitch = ACCESS_FBINFO(fbcon).var.xres_virtual;
mpitch = minfo->fbcon.var.xres_virtual;
ACCESS_FBINFO(fbops).fb_copyarea = cfb_copyarea;
ACCESS_FBINFO(fbops).fb_fillrect = cfb_fillrect;
ACCESS_FBINFO(fbops).fb_imageblit = cfb_imageblit;
ACCESS_FBINFO(fbops).fb_cursor = NULL;
minfo->fbops.fb_copyarea = cfb_copyarea;
minfo->fbops.fb_fillrect = cfb_fillrect;
minfo->fbops.fb_imageblit = cfb_imageblit;
minfo->fbops.fb_cursor = NULL;
accel = (ACCESS_FBINFO(fbcon).var.accel_flags & FB_ACCELF_TEXT) == FB_ACCELF_TEXT;
accel = (minfo->fbcon.var.accel_flags & FB_ACCELF_TEXT) == FB_ACCELF_TEXT;
switch (ACCESS_FBINFO(fbcon).var.bits_per_pixel) {
switch (minfo->fbcon.var.bits_per_pixel) {
case 4: maccess = 0x00000000; /* accelerate as 8bpp video */
mpitch = (mpitch >> 1) | 0x8000; /* disable linearization */
mopmode = M_OPMODE_4BPP;
matrox_cfb4_pal(ACCESS_FBINFO(cmap));
matrox_cfb4_pal(minfo->cmap);
if (accel && !(mpitch & 1)) {
ACCESS_FBINFO(fbops).fb_copyarea = matroxfb_cfb4_copyarea;
ACCESS_FBINFO(fbops).fb_fillrect = matroxfb_cfb4_fillrect;
minfo->fbops.fb_copyarea = matroxfb_cfb4_copyarea;
minfo->fbops.fb_fillrect = matroxfb_cfb4_fillrect;
}
break;
case 8: maccess = 0x00000000;
mopmode = M_OPMODE_8BPP;
matrox_cfb8_pal(ACCESS_FBINFO(cmap));
matrox_cfb8_pal(minfo->cmap);
if (accel) {
ACCESS_FBINFO(fbops).fb_copyarea = matroxfb_copyarea;
ACCESS_FBINFO(fbops).fb_fillrect = matroxfb_fillrect;
ACCESS_FBINFO(fbops).fb_imageblit = matroxfb_imageblit;
minfo->fbops.fb_copyarea = matroxfb_copyarea;
minfo->fbops.fb_fillrect = matroxfb_fillrect;
minfo->fbops.fb_imageblit = matroxfb_imageblit;
}
break;
case 16: if (ACCESS_FBINFO(fbcon).var.green.length == 5)
case 16: if (minfo->fbcon.var.green.length == 5)
maccess = 0xC0000001;
else
maccess = 0x40000001;
mopmode = M_OPMODE_16BPP;
if (accel) {
ACCESS_FBINFO(fbops).fb_copyarea = matroxfb_copyarea;
ACCESS_FBINFO(fbops).fb_fillrect = matroxfb_fillrect;
ACCESS_FBINFO(fbops).fb_imageblit = matroxfb_imageblit;
minfo->fbops.fb_copyarea = matroxfb_copyarea;
minfo->fbops.fb_fillrect = matroxfb_fillrect;
minfo->fbops.fb_imageblit = matroxfb_imageblit;
}
break;
case 24: maccess = 0x00000003;
mopmode = M_OPMODE_24BPP;
if (accel) {
ACCESS_FBINFO(fbops).fb_copyarea = matroxfb_copyarea;
ACCESS_FBINFO(fbops).fb_fillrect = matroxfb_fillrect;
ACCESS_FBINFO(fbops).fb_imageblit = matroxfb_imageblit;
minfo->fbops.fb_copyarea = matroxfb_copyarea;
minfo->fbops.fb_fillrect = matroxfb_fillrect;
minfo->fbops.fb_imageblit = matroxfb_imageblit;
}
break;
case 32: maccess = 0x00000002;
mopmode = M_OPMODE_32BPP;
if (accel) {
ACCESS_FBINFO(fbops).fb_copyarea = matroxfb_copyarea;
ACCESS_FBINFO(fbops).fb_fillrect = matroxfb_fillrect;
ACCESS_FBINFO(fbops).fb_imageblit = matroxfb_imageblit;
minfo->fbops.fb_copyarea = matroxfb_copyarea;
minfo->fbops.fb_fillrect = matroxfb_fillrect;
minfo->fbops.fb_imageblit = matroxfb_imageblit;
}
break;
default: maccess = 0x00000000;
@@ -176,10 +177,10 @@ void matrox_cfbX_init(WPMINFO2) {
}
mga_fifo(8);
mga_outl(M_PITCH, mpitch);
mga_outl(M_YDSTORG, curr_ydstorg(MINFO));
if (ACCESS_FBINFO(capable.plnwt))
mga_outl(M_YDSTORG, curr_ydstorg(minfo));
if (minfo->capable.plnwt)
mga_outl(M_PLNWT, -1);
if (ACCESS_FBINFO(capable.srcorg)) {
if (minfo->capable.srcorg) {
mga_outl(M_SRCORG, 0);
mga_outl(M_DSTORG, 0);
}
@@ -188,14 +189,16 @@ void matrox_cfbX_init(WPMINFO2) {
mga_outl(M_YTOP, 0);
mga_outl(M_YBOT, 0x01FFFFFF);
mga_outl(M_MACCESS, maccess);
ACCESS_FBINFO(accel.m_dwg_rect) = M_DWG_TRAP | M_DWG_SOLID | M_DWG_ARZERO | M_DWG_SGNZERO | M_DWG_SHIFTZERO;
if (isMilleniumII(MINFO)) ACCESS_FBINFO(accel.m_dwg_rect) |= M_DWG_TRANSC;
ACCESS_FBINFO(accel.m_opmode) = mopmode;
minfo->accel.m_dwg_rect = M_DWG_TRAP | M_DWG_SOLID | M_DWG_ARZERO | M_DWG_SGNZERO | M_DWG_SHIFTZERO;
if (isMilleniumII(minfo)) minfo->accel.m_dwg_rect |= M_DWG_TRANSC;
minfo->accel.m_opmode = mopmode;
}
EXPORT_SYMBOL(matrox_cfbX_init);
static void matrox_accel_bmove(WPMINFO int vxres, int sy, int sx, int dy, int dx, int height, int width) {
static void matrox_accel_bmove(struct matrox_fb_info *minfo, int vxres, int sy,
int sx, int dy, int dx, int height, int width)
{
int start, end;
CRITFLAGS
@@ -209,7 +212,7 @@ static void matrox_accel_bmove(WPMINFO int vxres, int sy, int sx, int dy, int dx
M_DWG_BFCOL | M_DWG_REPLACE);
mga_outl(M_AR5, vxres);
width--;
start = sy*vxres+sx+curr_ydstorg(MINFO);
start = sy*vxres+sx+curr_ydstorg(minfo);
end = start+width;
} else {
mga_fifo(3);
@@ -217,7 +220,7 @@ static void matrox_accel_bmove(WPMINFO int vxres, int sy, int sx, int dy, int dx
mga_outl(M_SGN, 5);
mga_outl(M_AR5, -vxres);
width--;
end = (sy+height-1)*vxres+sx+curr_ydstorg(MINFO);
end = (sy+height-1)*vxres+sx+curr_ydstorg(minfo);
start = end+width;
dy += height-1;
}
@@ -231,7 +234,10 @@ static void matrox_accel_bmove(WPMINFO int vxres, int sy, int sx, int dy, int dx
CRITEND
}
static void matrox_accel_bmove_lin(WPMINFO int vxres, int sy, int sx, int dy, int dx, int height, int width) {
static void matrox_accel_bmove_lin(struct matrox_fb_info *minfo, int vxres,
int sy, int sx, int dy, int dx, int height,
int width)
{
int start, end;
CRITFLAGS
@@ -245,7 +251,7 @@ static void matrox_accel_bmove_lin(WPMINFO int vxres, int sy, int sx, int dy, in
M_DWG_BFCOL | M_DWG_REPLACE);
mga_outl(M_AR5, vxres);
width--;
start = sy*vxres+sx+curr_ydstorg(MINFO);
start = sy*vxres+sx+curr_ydstorg(minfo);
end = start+width;
} else {
mga_fifo(3);
@@ -253,7 +259,7 @@ static void matrox_accel_bmove_lin(WPMINFO int vxres, int sy, int sx, int dy, in
mga_outl(M_SGN, 5);
mga_outl(M_AR5, -vxres);
width--;
end = (sy+height-1)*vxres+sx+curr_ydstorg(MINFO);
end = (sy+height-1)*vxres+sx+curr_ydstorg(minfo);
start = end+width;
dy += height-1;
}
@@ -269,22 +275,23 @@ static void matrox_accel_bmove_lin(WPMINFO int vxres, int sy, int sx, int dy, in
}
static void matroxfb_cfb4_copyarea(struct fb_info* info, const struct fb_copyarea* area) {
MINFO_FROM_INFO(info);
struct matrox_fb_info *minfo = info2minfo(info);
if ((area->sx | area->dx | area->width) & 1)
cfb_copyarea(info, area);
else
matrox_accel_bmove_lin(PMINFO ACCESS_FBINFO(fbcon.var.xres_virtual) >> 1, area->sy, area->sx >> 1, area->dy, area->dx >> 1, area->height, area->width >> 1);
matrox_accel_bmove_lin(minfo, minfo->fbcon.var.xres_virtual >> 1, area->sy, area->sx >> 1, area->dy, area->dx >> 1, area->height, area->width >> 1);
}
static void matroxfb_copyarea(struct fb_info* info, const struct fb_copyarea* area) {
MINFO_FROM_INFO(info);
struct matrox_fb_info *minfo = info2minfo(info);
matrox_accel_bmove(PMINFO ACCESS_FBINFO(fbcon.var.xres_virtual), area->sy, area->sx, area->dy, area->dx, area->height, area->width);
matrox_accel_bmove(minfo, minfo->fbcon.var.xres_virtual, area->sy, area->sx, area->dy, area->dx, area->height, area->width);
}
static void matroxfb_accel_clear(WPMINFO u_int32_t color, int sy, int sx, int height,
int width) {
static void matroxfb_accel_clear(struct matrox_fb_info *minfo, u_int32_t color,
int sy, int sx, int height, int width)
{
CRITFLAGS
DBG(__func__)
@@ -292,7 +299,7 @@ static void matroxfb_accel_clear(WPMINFO u_int32_t color, int sy, int sx, int he
CRITBEGIN
mga_fifo(5);
mga_outl(M_DWGCTL, ACCESS_FBINFO(accel.m_dwg_rect) | M_DWG_REPLACE);
mga_outl(M_DWGCTL, minfo->accel.m_dwg_rect | M_DWG_REPLACE);
mga_outl(M_FCOL, color);
mga_outl(M_FXBNDRY, ((sx + width) << 16) | sx);
mga_ydstlen(sy, height);
@@ -302,16 +309,18 @@ static void matroxfb_accel_clear(WPMINFO u_int32_t color, int sy, int sx, int he
}
static void matroxfb_fillrect(struct fb_info* info, const struct fb_fillrect* rect) {
MINFO_FROM_INFO(info);
struct matrox_fb_info *minfo = info2minfo(info);
switch (rect->rop) {
case ROP_COPY:
matroxfb_accel_clear(PMINFO ((u_int32_t*)info->pseudo_palette)[rect->color], rect->dy, rect->dx, rect->height, rect->width);
matroxfb_accel_clear(minfo, ((u_int32_t *)info->pseudo_palette)[rect->color], rect->dy, rect->dx, rect->height, rect->width);
break;
}
}
static void matroxfb_cfb4_clear(WPMINFO u_int32_t bgx, int sy, int sx, int height, int width) {
static void matroxfb_cfb4_clear(struct matrox_fb_info *minfo, u_int32_t bgx,
int sy, int sx, int height, int width)
{
int whattodo;
CRITFLAGS
@@ -333,16 +342,16 @@ static void matroxfb_cfb4_clear(WPMINFO u_int32_t bgx, int sy, int sx, int heigh
sx >>= 1;
if (width) {
mga_fifo(5);
mga_outl(M_DWGCTL, ACCESS_FBINFO(accel.m_dwg_rect) | M_DWG_REPLACE2);
mga_outl(M_DWGCTL, minfo->accel.m_dwg_rect | M_DWG_REPLACE2);
mga_outl(M_FCOL, bgx);
mga_outl(M_FXBNDRY, ((sx + width) << 16) | sx);
mga_outl(M_YDST, sy * ACCESS_FBINFO(fbcon).var.xres_virtual >> 6);
mga_outl(M_YDST, sy * minfo->fbcon.var.xres_virtual >> 6);
mga_outl(M_LEN | M_EXEC, height);
WaitTillIdle();
}
if (whattodo) {
u_int32_t step = ACCESS_FBINFO(fbcon).var.xres_virtual >> 1;
vaddr_t vbase = ACCESS_FBINFO(video.vbase);
u_int32_t step = minfo->fbcon.var.xres_virtual >> 1;
vaddr_t vbase = minfo->video.vbase;
if (whattodo & 1) {
unsigned int uaddr = sy * step + sx - 1;
u_int32_t loop;
@@ -367,17 +376,19 @@ static void matroxfb_cfb4_clear(WPMINFO u_int32_t bgx, int sy, int sx, int heigh
}
static void matroxfb_cfb4_fillrect(struct fb_info* info, const struct fb_fillrect* rect) {
MINFO_FROM_INFO(info);
struct matrox_fb_info *minfo = info2minfo(info);
switch (rect->rop) {
case ROP_COPY:
matroxfb_cfb4_clear(PMINFO ((u_int32_t*)info->pseudo_palette)[rect->color], rect->dy, rect->dx, rect->height, rect->width);
matroxfb_cfb4_clear(minfo, ((u_int32_t *)info->pseudo_palette)[rect->color], rect->dy, rect->dx, rect->height, rect->width);
break;
}
}
static void matroxfb_1bpp_imageblit(WPMINFO u_int32_t fgx, u_int32_t bgx,
const u_int8_t* chardata, int width, int height, int yy, int xx) {
static void matroxfb_1bpp_imageblit(struct matrox_fb_info *minfo, u_int32_t fgx,
u_int32_t bgx, const u_int8_t *chardata,
int width, int height, int yy, int xx)
{
u_int32_t step;
u_int32_t ydstlen;
u_int32_t xlen;
@@ -412,7 +423,7 @@ static void matroxfb_1bpp_imageblit(WPMINFO u_int32_t fgx, u_int32_t bgx,
mga_outl(M_FCOL, fgx);
mga_outl(M_BCOL, bgx);
fxbndry = ((xx + width - 1) << 16) | xx;
mmio = ACCESS_FBINFO(mmio.vbase);
mmio = minfo->mmio.vbase;
mga_fifo(6);
mga_writel(mmio, M_FXBNDRY, fxbndry);
@@ -467,7 +478,7 @@ static void matroxfb_1bpp_imageblit(WPMINFO u_int32_t fgx, u_int32_t bgx,
static void matroxfb_imageblit(struct fb_info* info, const struct fb_image* image) {
MINFO_FROM_INFO(info);
struct matrox_fb_info *minfo = info2minfo(info);
DBG_HEAVY(__func__);
@@ -476,7 +487,7 @@ static void matroxfb_imageblit(struct fb_info* info, const struct fb_image* imag
fgx = ((u_int32_t*)info->pseudo_palette)[image->fg_color];
bgx = ((u_int32_t*)info->pseudo_palette)[image->bg_color];
matroxfb_1bpp_imageblit(PMINFO fgx, bgx, image->data, image->width, image->height, image->dy, image->dx);
matroxfb_1bpp_imageblit(minfo, fgx, bgx, image->data, image->width, image->height, image->dy, image->dx);
} else {
/* Danger! image->depth is useless: logo painting code always
passes framebuffer color depth here, although logo data are

2
drivers/video/matrox/matroxfb_accel.h
View File

@@ -3,6 +3,6 @@
#include "matroxfb_base.h"
void matrox_cfbX_init(WPMINFO2);
void matrox_cfbX_init(struct matrox_fb_info *minfo);
#endif

762
drivers/video/matrox/matroxfb_base.c
View File

File diff suppressed because it is too large Load Diff

80
drivers/video/matrox/matroxfb_base.h
View File

@@ -54,9 +54,6 @@
#include "../macmodes.h"
#endif
/* always compile support for 32MB... It cost almost nothing */
#define CONFIG_FB_MATROX_32MB
#ifdef MATROXFB_DEBUG
#define DEBUG
@@ -464,9 +461,7 @@ struct matrox_fb_info {
int nopciretry;
int noinit;
int sgram;
#ifdef CONFIG_FB_MATROX_32MB
int support32MB;
#endif
int accelerator;
int text_type_aux;
@@ -524,47 +519,11 @@ struct matrox_fb_info {
#define info2minfo(info) container_of(info, struct matrox_fb_info, fbcon)
#ifdef CONFIG_FB_MATROX_MULTIHEAD
#define ACCESS_FBINFO2(info, x) (info->x)
#define ACCESS_FBINFO(x) ACCESS_FBINFO2(minfo,x)
#define MINFO minfo
#define WPMINFO2 struct matrox_fb_info* minfo
#define WPMINFO WPMINFO2 ,
#define CPMINFO2 const struct matrox_fb_info* minfo
#define CPMINFO CPMINFO2 ,
#define PMINFO2 minfo
#define PMINFO PMINFO2 ,
#define MINFO_FROM(x) struct matrox_fb_info* minfo = x
#else
extern struct matrox_fb_info matroxfb_global_mxinfo;
#define ACCESS_FBINFO(x) (matroxfb_global_mxinfo.x)
#define ACCESS_FBINFO2(info, x) (matroxfb_global_mxinfo.x)
#define MINFO (&matroxfb_global_mxinfo)
#define WPMINFO2 void
#define WPMINFO
#define CPMINFO2 void
#define CPMINFO
#define PMINFO2
#define PMINFO
#define MINFO_FROM(x)
#endif
#define MINFO_FROM_INFO(x) MINFO_FROM(info2minfo(x))
struct matrox_switch {
int (*preinit)(WPMINFO2);
void (*reset)(WPMINFO2);
int (*init)(WPMINFO struct my_timming*);
void (*restore)(WPMINFO2);
int (*preinit)(struct matrox_fb_info *minfo);
void (*reset)(struct matrox_fb_info *minfo);
int (*init)(struct matrox_fb_info *minfo, struct my_timming*);
void (*restore)(struct matrox_fb_info *minfo);
};
struct matroxfb_driver {
@@ -727,11 +686,11 @@ void matroxfb_unregister_driver(struct matroxfb_driver* drv);
#endif
#endif
#define mga_inb(addr) mga_readb(ACCESS_FBINFO(mmio.vbase), (addr))
#define mga_inl(addr) mga_readl(ACCESS_FBINFO(mmio.vbase), (addr))
#define mga_outb(addr,val) mga_writeb(ACCESS_FBINFO(mmio.vbase), (addr), (val))
#define mga_outw(addr,val) mga_writew(ACCESS_FBINFO(mmio.vbase), (addr), (val))
#define mga_outl(addr,val) mga_writel(ACCESS_FBINFO(mmio.vbase), (addr), (val))
#define mga_inb(addr) mga_readb(minfo->mmio.vbase, (addr))
#define mga_inl(addr) mga_readl(minfo->mmio.vbase, (addr))
#define mga_outb(addr,val) mga_writeb(minfo->mmio.vbase, (addr), (val))
#define mga_outw(addr,val) mga_writew(minfo->mmio.vbase, (addr), (val))
#define mga_outl(addr,val) mga_writel(minfo->mmio.vbase, (addr), (val))
#define mga_readr(port,idx) (mga_outb((port),(idx)), mga_inb((port)+1))
#define mga_setr(addr,port,val) mga_outw(addr, ((val)<<8) | (port))
@@ -750,19 +709,20 @@ void matroxfb_unregister_driver(struct matroxfb_driver* drv);
#define isMilleniumII(x) (0)
#endif
#define matroxfb_DAC_lock() spin_lock(&ACCESS_FBINFO(lock.DAC))
#define matroxfb_DAC_unlock() spin_unlock(&ACCESS_FBINFO(lock.DAC))
#define matroxfb_DAC_lock_irqsave(flags) spin_lock_irqsave(&ACCESS_FBINFO(lock.DAC),flags)
#define matroxfb_DAC_unlock_irqrestore(flags) spin_unlock_irqrestore(&ACCESS_FBINFO(lock.DAC),flags)
extern void matroxfb_DAC_out(CPMINFO int reg, int val);
extern int matroxfb_DAC_in(CPMINFO int reg);
#define matroxfb_DAC_lock() spin_lock(&minfo->lock.DAC)
#define matroxfb_DAC_unlock() spin_unlock(&minfo->lock.DAC)
#define matroxfb_DAC_lock_irqsave(flags) spin_lock_irqsave(&minfo->lock.DAC, flags)
#define matroxfb_DAC_unlock_irqrestore(flags) spin_unlock_irqrestore(&minfo->lock.DAC, flags)
extern void matroxfb_DAC_out(const struct matrox_fb_info *minfo, int reg,
int val);
extern int matroxfb_DAC_in(const struct matrox_fb_info *minfo, int reg);
extern void matroxfb_var2my(struct fb_var_screeninfo* fvsi, struct my_timming* mt);
extern int matroxfb_wait_for_sync(WPMINFO u_int32_t crtc);
extern int matroxfb_enable_irq(WPMINFO int reenable);
extern int matroxfb_wait_for_sync(struct matrox_fb_info *minfo, u_int32_t crtc);
extern int matroxfb_enable_irq(struct matrox_fb_info *minfo, int reenable);
#ifdef MATROXFB_USE_SPINLOCKS
#define CRITBEGIN spin_lock_irqsave(&ACCESS_FBINFO(lock.accel), critflags);
#define CRITEND spin_unlock_irqrestore(&ACCESS_FBINFO(lock.accel), critflags);
#define CRITBEGIN spin_lock_irqsave(&minfo->lock.accel, critflags);
#define CRITEND spin_unlock_irqrestore(&minfo->lock.accel, critflags);
#define CRITFLAGS unsigned long critflags;
#else
#define CRITBEGIN

160
drivers/video/matrox/matroxfb_crtc2.c
View File

@@ -65,7 +65,7 @@ static void matroxfb_dh_restore(struct matroxfb_dh_fb_info* m2info,
unsigned int pos) {
u_int32_t tmp;
u_int32_t datactl;
MINFO_FROM(m2info->primary_dev);
struct matrox_fb_info *minfo = m2info->primary_dev;
switch (mode) {
case 15:
@@ -81,11 +81,11 @@ static void matroxfb_dh_restore(struct matroxfb_dh_fb_info* m2info,
}
tmp |= 0x00000001; /* enable CRTC2 */
datactl = 0;
if (ACCESS_FBINFO(outputs[1]).src == MATROXFB_SRC_CRTC2) {
if (ACCESS_FBINFO(devflags.g450dac)) {
if (minfo->outputs[1].src == MATROXFB_SRC_CRTC2) {
if (minfo->devflags.g450dac) {
tmp |= 0x00000006; /* source from secondary pixel PLL */
/* no vidrst when in monitor mode */
if (ACCESS_FBINFO(outputs[1]).mode != MATROXFB_OUTPUT_MODE_MONITOR) {
if (minfo->outputs[1].mode != MATROXFB_OUTPUT_MODE_MONITOR) {
tmp |= 0xC0001000; /* Enable H/V vidrst */
}
} else {
@@ -93,11 +93,11 @@ static void matroxfb_dh_restore(struct matroxfb_dh_fb_info* m2info,
tmp |= 0xC0000000; /* enable vvidrst & hvidrst */
/* MGA TVO is our clock source */
}
} else if (ACCESS_FBINFO(outputs[0]).src == MATROXFB_SRC_CRTC2) {
} else if (minfo->outputs[0].src == MATROXFB_SRC_CRTC2) {
tmp |= 0x00000004; /* source from pixclock */
/* PIXPLL is our clock source */
}
if (ACCESS_FBINFO(outputs[0]).src == MATROXFB_SRC_CRTC2) {
if (minfo->outputs[0].src == MATROXFB_SRC_CRTC2) {
tmp |= 0x00100000; /* connect CRTC2 to DAC */
}
if (mt->interlaced) {
@@ -146,7 +146,7 @@ static void matroxfb_dh_restore(struct matroxfb_dh_fb_info* m2info,
}
}
mga_outl(0x3C10, tmp);
ACCESS_FBINFO(hw).crtc2.ctl = tmp;
minfo->hw.crtc2.ctl = tmp;
tmp = mt->VDisplay << 16; /* line compare */
if (mt->sync & FB_SYNC_HOR_HIGH_ACT)
@@ -157,10 +157,10 @@ static void matroxfb_dh_restore(struct matroxfb_dh_fb_info* m2info,
}
static void matroxfb_dh_disable(struct matroxfb_dh_fb_info* m2info) {
MINFO_FROM(m2info->primary_dev);
struct matrox_fb_info *minfo = m2info->primary_dev;
mga_outl(0x3C10, 0x00000004); /* disable CRTC2, CRTC1->DAC1, PLL as clock source */
ACCESS_FBINFO(hw).crtc2.ctl = 0x00000004;
minfo->hw.crtc2.ctl = 0x00000004;
}
static void matroxfb_dh_pan_var(struct matroxfb_dh_fb_info* m2info,
@@ -168,7 +168,7 @@ static void matroxfb_dh_pan_var(struct matroxfb_dh_fb_info* m2info,
unsigned int pos;
unsigned int linelen;
unsigned int pixelsize;
MINFO_FROM(m2info->primary_dev);
struct matrox_fb_info *minfo = m2info->primary_dev;
m2info->fbcon.var.xoffset = var->xoffset;
m2info->fbcon.var.yoffset = var->yoffset;
@@ -260,15 +260,15 @@ static int matroxfb_dh_decode_var(struct matroxfb_dh_fb_info* m2info,
static int matroxfb_dh_open(struct fb_info* info, int user) {
#define m2info (container_of(info, struct matroxfb_dh_fb_info, fbcon))
MINFO_FROM(m2info->primary_dev);
struct matrox_fb_info *minfo = m2info->primary_dev;
if (MINFO) {
if (minfo) {
int err;
if (ACCESS_FBINFO(dead)) {
if (minfo->dead) {
return -ENXIO;
}
err = ACCESS_FBINFO(fbops).fb_open(&ACCESS_FBINFO(fbcon), user);
err = minfo->fbops.fb_open(&minfo->fbcon, user);
if (err) {
return err;
}
@@ -280,10 +280,10 @@ static int matroxfb_dh_open(struct fb_info* info, int user) {
static int matroxfb_dh_release(struct fb_info* info, int user) {
#define m2info (container_of(info, struct matroxfb_dh_fb_info, fbcon))
int err = 0;
MINFO_FROM(m2info->primary_dev);
struct matrox_fb_info *minfo = m2info->primary_dev;
if (MINFO) {
err = ACCESS_FBINFO(fbops).fb_release(&ACCESS_FBINFO(fbcon), user);
if (minfo) {
err = minfo->fbops.fb_release(&minfo->fbcon, user);
}
return err;
#undef m2info
@@ -326,7 +326,7 @@ static int matroxfb_dh_set_par(struct fb_info* info) {
int mode;
int err;
struct fb_var_screeninfo* var = &info->var;
MINFO_FROM(m2info->primary_dev);
struct matrox_fb_info *minfo = m2info->primary_dev;
if ((err = matroxfb_dh_decode_var(m2info, var, &visual, &cmap_len, &mode)) != 0)
return err;
@@ -352,39 +352,39 @@ static int matroxfb_dh_set_par(struct fb_info* info) {
pos = (m2info->fbcon.var.yoffset * m2info->fbcon.var.xres_virtual + m2info->fbcon.var.xoffset) * m2info->fbcon.var.bits_per_pixel >> 3;
pos += m2info->video.offbase;
cnt = 0;
down_read(&ACCESS_FBINFO(altout).lock);
down_read(&minfo->altout.lock);
for (out = 0; out < MATROXFB_MAX_OUTPUTS; out++) {
if (ACCESS_FBINFO(outputs[out]).src == MATROXFB_SRC_CRTC2) {
if (minfo->outputs[out].src == MATROXFB_SRC_CRTC2) {
cnt++;
if (ACCESS_FBINFO(outputs[out]).output->compute) {
ACCESS_FBINFO(outputs[out]).output->compute(ACCESS_FBINFO(outputs[out]).data, &mt);
if (minfo->outputs[out].output->compute) {
minfo->outputs[out].output->compute(minfo->outputs[out].data, &mt);
}
}
}
ACCESS_FBINFO(crtc2).pixclock = mt.pixclock;
ACCESS_FBINFO(crtc2).mnp = mt.mnp;
up_read(&ACCESS_FBINFO(altout).lock);
minfo->crtc2.pixclock = mt.pixclock;
minfo->crtc2.mnp = mt.mnp;
up_read(&minfo->altout.lock);
if (cnt) {
matroxfb_dh_restore(m2info, &mt, mode, pos);
} else {
matroxfb_dh_disable(m2info);
}
DAC1064_global_init(PMINFO2);
DAC1064_global_restore(PMINFO2);
down_read(&ACCESS_FBINFO(altout).lock);
DAC1064_global_init(minfo);
DAC1064_global_restore(minfo);
down_read(&minfo->altout.lock);
for (out = 0; out < MATROXFB_MAX_OUTPUTS; out++) {
if (ACCESS_FBINFO(outputs[out]).src == MATROXFB_SRC_CRTC2 &&
ACCESS_FBINFO(outputs[out]).output->program) {
ACCESS_FBINFO(outputs[out]).output->program(ACCESS_FBINFO(outputs[out]).data);
if (minfo->outputs[out].src == MATROXFB_SRC_CRTC2 &&
minfo->outputs[out].output->program) {
minfo->outputs[out].output->program(minfo->outputs[out].data);
}
}
for (out = 0; out < MATROXFB_MAX_OUTPUTS; out++) {
if (ACCESS_FBINFO(outputs[out]).src == MATROXFB_SRC_CRTC2 &&
ACCESS_FBINFO(outputs[out]).output->start) {
ACCESS_FBINFO(outputs[out]).output->start(ACCESS_FBINFO(outputs[out]).data);
if (minfo->outputs[out].src == MATROXFB_SRC_CRTC2 &&
minfo->outputs[out].output->start) {
minfo->outputs[out].output->start(minfo->outputs[out].data);
}
}
up_read(&ACCESS_FBINFO(altout).lock);
up_read(&minfo->altout.lock);
}
m2info->initialized = 1;
return 0;
@@ -399,9 +399,9 @@ static int matroxfb_dh_pan_display(struct fb_var_screeninfo* var, struct fb_info
}
static int matroxfb_dh_get_vblank(const struct matroxfb_dh_fb_info* m2info, struct fb_vblank* vblank) {
MINFO_FROM(m2info->primary_dev);
struct matrox_fb_info *minfo = m2info->primary_dev;
matroxfb_enable_irq(PMINFO 0);
matroxfb_enable_irq(minfo, 0);
memset(vblank, 0, sizeof(*vblank));
vblank->flags = FB_VBLANK_HAVE_VCOUNT | FB_VBLANK_HAVE_VBLANK;
/* mask out reserved bits + field number (odd/even) */
@@ -409,11 +409,11 @@ static int matroxfb_dh_get_vblank(const struct matroxfb_dh_fb_info* m2info, stru
/* compatibility stuff */
if (vblank->vcount >= m2info->fbcon.var.yres)
vblank->flags |= FB_VBLANK_VBLANKING;
if (test_bit(0, &ACCESS_FBINFO(irq_flags))) {
if (test_bit(0, &minfo->irq_flags)) {
vblank->flags |= FB_VBLANK_HAVE_COUNT;
/* Only one writer, aligned int value...
it should work without lock and without atomic_t */
vblank->count = ACCESS_FBINFO(crtc2).vsync.cnt;
vblank->count = minfo->crtc2.vsync.cnt;
}
return 0;
}
@@ -423,7 +423,7 @@ static int matroxfb_dh_ioctl(struct fb_info *info,
unsigned long arg)
{
#define m2info (container_of(info, struct matroxfb_dh_fb_info, fbcon))
MINFO_FROM(m2info->primary_dev);
struct matrox_fb_info *minfo = m2info->primary_dev;
DBG(__func__)
@@ -449,13 +449,13 @@ static int matroxfb_dh_ioctl(struct fb_info *info,
if (crt != 0)
return -ENODEV;
return matroxfb_wait_for_sync(PMINFO 1);
return matroxfb_wait_for_sync(minfo, 1);
}
case MATROXFB_SET_OUTPUT_MODE:
case MATROXFB_GET_OUTPUT_MODE:
case MATROXFB_GET_ALL_OUTPUTS:
{
return ACCESS_FBINFO(fbcon.fbops)->fb_ioctl(&ACCESS_FBINFO(fbcon), cmd, arg);
return minfo->fbcon.fbops->fb_ioctl(&minfo->fbcon, cmd, arg);
}
case MATROXFB_SET_OUTPUT_CONNECTION:
{
@@ -469,9 +469,9 @@ static int matroxfb_dh_ioctl(struct fb_info *info,
if (tmp & (1 << out)) {
if (out >= MATROXFB_MAX_OUTPUTS)
return -ENXIO;
if (!ACCESS_FBINFO(outputs[out]).output)
if (!minfo->outputs[out].output)
return -ENXIO;
switch (ACCESS_FBINFO(outputs[out]).src) {
switch (minfo->outputs[out].src) {
case MATROXFB_SRC_NONE:
case MATROXFB_SRC_CRTC2:
break;
@@ -480,22 +480,22 @@ static int matroxfb_dh_ioctl(struct fb_info *info,
}
}
}
if (ACCESS_FBINFO(devflags.panellink)) {
if (minfo->devflags.panellink) {
if (tmp & MATROXFB_OUTPUT_CONN_DFP)
return -EINVAL;
if ((ACCESS_FBINFO(outputs[2]).src == MATROXFB_SRC_CRTC1) && tmp)
if ((minfo->outputs[2].src == MATROXFB_SRC_CRTC1) && tmp)
return -EBUSY;
}
changes = 0;
for (out = 0; out < MATROXFB_MAX_OUTPUTS; out++) {
if (tmp & (1 << out)) {
if (ACCESS_FBINFO(outputs[out]).src != MATROXFB_SRC_CRTC2) {
if (minfo->outputs[out].src != MATROXFB_SRC_CRTC2) {
changes = 1;
ACCESS_FBINFO(outputs[out]).src = MATROXFB_SRC_CRTC2;
minfo->outputs[out].src = MATROXFB_SRC_CRTC2;
}
} else if (ACCESS_FBINFO(outputs[out]).src == MATROXFB_SRC_CRTC2) {
} else if (minfo->outputs[out].src == MATROXFB_SRC_CRTC2) {
changes = 1;
ACCESS_FBINFO(outputs[out]).src = MATROXFB_SRC_NONE;
minfo->outputs[out].src = MATROXFB_SRC_NONE;
}
}
if (!changes)
@@ -509,7 +509,7 @@ static int matroxfb_dh_ioctl(struct fb_info *info,
int out;
for (out = 0; out < MATROXFB_MAX_OUTPUTS; out++) {
if (ACCESS_FBINFO(outputs[out]).src == MATROXFB_SRC_CRTC2) {
if (minfo->outputs[out].src == MATROXFB_SRC_CRTC2) {
conn |= 1 << out;
}
}
@@ -523,8 +523,8 @@ static int matroxfb_dh_ioctl(struct fb_info *info,
int out;
for (out = 0; out < MATROXFB_MAX_OUTPUTS; out++) {
if (ACCESS_FBINFO(outputs[out]).output) {
switch (ACCESS_FBINFO(outputs[out]).src) {
if (minfo->outputs[out].output) {
switch (minfo->outputs[out].src) {
case MATROXFB_SRC_NONE:
case MATROXFB_SRC_CRTC2:
tmp |= 1 << out;
@@ -532,9 +532,9 @@ static int matroxfb_dh_ioctl(struct fb_info *info,
}
}
}
if (ACCESS_FBINFO(devflags.panellink)) {
if (minfo->devflags.panellink) {
tmp &= ~MATROXFB_OUTPUT_CONN_DFP;
if (ACCESS_FBINFO(outputs[2]).src == MATROXFB_SRC_CRTC1) {
if (minfo->outputs[2].src == MATROXFB_SRC_CRTC1) {
tmp = 0;
}
}
@@ -595,7 +595,9 @@ static struct fb_var_screeninfo matroxfb_dh_defined = {
0, {0,0,0,0,0}
};
static int matroxfb_dh_regit(CPMINFO struct matroxfb_dh_fb_info* m2info) {
static int matroxfb_dh_regit(const struct matrox_fb_info *minfo,
struct matroxfb_dh_fb_info *m2info)
{
#define minfo (m2info->primary_dev)
void* oldcrtc2;
@@ -611,21 +613,21 @@ static int matroxfb_dh_regit(CPMINFO struct matroxfb_dh_fb_info* m2info) {
if (mem < 64*1024)
mem *= 1024;
mem &= ~0x00000FFF; /* PAGE_MASK? */
if (ACCESS_FBINFO(video.len_usable) + mem <= ACCESS_FBINFO(video.len))
m2info->video.offbase = ACCESS_FBINFO(video.len) - mem;
else if (ACCESS_FBINFO(video.len) < mem) {
if (minfo->video.len_usable + mem <= minfo->video.len)
m2info->video.offbase = minfo->video.len - mem;
else if (minfo->video.len < mem) {
return -ENOMEM;
} else { /* check yres on first head... */
m2info->video.borrowed = mem;
ACCESS_FBINFO(video.len_usable) -= mem;
m2info->video.offbase = ACCESS_FBINFO(video.len_usable);
minfo->video.len_usable -= mem;
m2info->video.offbase = minfo->video.len_usable;
}
m2info->video.base = ACCESS_FBINFO(video.base) + m2info->video.offbase;
m2info->video.base = minfo->video.base + m2info->video.offbase;
m2info->video.len = m2info->video.len_usable = m2info->video.len_maximum = mem;
m2info->video.vbase.vaddr = vaddr_va(ACCESS_FBINFO(video.vbase)) + m2info->video.offbase;
m2info->mmio.base = ACCESS_FBINFO(mmio.base);
m2info->mmio.vbase = ACCESS_FBINFO(mmio.vbase);
m2info->mmio.len = ACCESS_FBINFO(mmio.len);
m2info->video.vbase.vaddr = vaddr_va(minfo->video.vbase) + m2info->video.offbase;
m2info->mmio.base = minfo->mmio.base;
m2info->mmio.vbase = minfo->mmio.vbase;
m2info->mmio.len = minfo->mmio.len;
matroxfb_dh_init_fix(m2info);
if (register_framebuffer(&m2info->fbcon)) {
@@ -633,10 +635,10 @@ static int matroxfb_dh_regit(CPMINFO struct matroxfb_dh_fb_info* m2info) {
}
if (!m2info->initialized)
fb_set_var(&m2info->fbcon, &matroxfb_dh_defined);
down_write(&ACCESS_FBINFO(crtc2.lock));
oldcrtc2 = ACCESS_FBINFO(crtc2.info);
ACCESS_FBINFO(crtc2.info) = m2info;
up_write(&ACCESS_FBINFO(crtc2.lock));
down_write(&minfo->crtc2.lock);
oldcrtc2 = minfo->crtc2.info;
minfo->crtc2.info = m2info;
up_write(&minfo->crtc2.lock);
if (oldcrtc2) {
printk(KERN_ERR "matroxfb_crtc2: Internal consistency check failed: crtc2 already present: %p\n",
oldcrtc2);
@@ -649,12 +651,12 @@ static int matroxfb_dh_regit(CPMINFO struct matroxfb_dh_fb_info* m2info) {
static int matroxfb_dh_registerfb(struct matroxfb_dh_fb_info* m2info) {
#define minfo (m2info->primary_dev)
if (matroxfb_dh_regit(PMINFO m2info)) {
if (matroxfb_dh_regit(minfo, m2info)) {
printk(KERN_ERR "matroxfb_crtc2: secondary head failed to register\n");
return -1;
}
printk(KERN_INFO "matroxfb_crtc2: secondary head of fb%u was registered as fb%u\n",
ACCESS_FBINFO(fbcon.node), m2info->fbcon.node);
minfo->fbcon.node, m2info->fbcon.node);
m2info->fbcon_registered = 1;
return 0;
#undef minfo
@@ -666,11 +668,11 @@ static void matroxfb_dh_deregisterfb(struct matroxfb_dh_fb_info* m2info) {
int id;
struct matroxfb_dh_fb_info* crtc2;
down_write(&ACCESS_FBINFO(crtc2.lock));
crtc2 = ACCESS_FBINFO(crtc2.info);
down_write(&minfo->crtc2.lock);
crtc2 = minfo->crtc2.info;
if (crtc2 == m2info)
ACCESS_FBINFO(crtc2.info) = NULL;
up_write(&ACCESS_FBINFO(crtc2.lock));
minfo->crtc2.info = NULL;
up_write(&minfo->crtc2.lock);
if (crtc2 != m2info) {
printk(KERN_ERR "matroxfb_crtc2: Internal consistency check failed: crtc2 mismatch at unload: %p != %p\n",
crtc2, m2info);
@@ -680,7 +682,7 @@ static void matroxfb_dh_deregisterfb(struct matroxfb_dh_fb_info* m2info) {
id = m2info->fbcon.node;
unregister_framebuffer(&m2info->fbcon);
/* return memory back to primary head */
ACCESS_FBINFO(video.len_usable) += m2info->video.borrowed;
minfo->video.len_usable += m2info->video.borrowed;
printk(KERN_INFO "matroxfb_crtc2: fb%u unregistered\n", id);
m2info->fbcon_registered = 0;
}
@@ -691,14 +693,14 @@ static void* matroxfb_crtc2_probe(struct matrox_fb_info* minfo) {
struct matroxfb_dh_fb_info* m2info;
/* hardware is CRTC2 incapable... */
if (!ACCESS_FBINFO(devflags.crtc2))
if (!minfo->devflags.crtc2)
return NULL;
m2info = kzalloc(sizeof(*m2info), GFP_KERNEL);
if (!m2info) {
printk(KERN_ERR "matroxfb_crtc2: Not enough memory for CRTC2 control structs\n");
return NULL;
}
m2info->primary_dev = MINFO;
m2info->primary_dev = minfo;
if (matroxfb_dh_registerfb(m2info)) {
kfree(m2info);
printk(KERN_ERR "matroxfb_crtc2: CRTC2 framebuffer failed to register\n");

185
drivers/video/matrox/matroxfb_g450.c
View File

@@ -80,52 +80,59 @@ static int get_ctrl_id(__u32 v4l2_id) {
return -EINVAL;
}
static inline int* get_ctrl_ptr(WPMINFO unsigned int idx) {
return (int*)((char*)MINFO + g450_controls[idx].control);
static inline int *get_ctrl_ptr(struct matrox_fb_info *minfo, unsigned int idx)
{
return (int*)((char*)minfo + g450_controls[idx].control);
}
static void tvo_fill_defaults(WPMINFO2) {
static void tvo_fill_defaults(struct matrox_fb_info *minfo)
{
unsigned int i;
for (i = 0; i < G450CTRLS; i++) {
*get_ctrl_ptr(PMINFO i) = g450_controls[i].desc.default_value;
*get_ctrl_ptr(minfo, i) = g450_controls[i].desc.default_value;
}
}
static int cve2_get_reg(WPMINFO int reg) {
static int cve2_get_reg(struct matrox_fb_info *minfo, int reg)
{
unsigned long flags;
int val;
matroxfb_DAC_lock_irqsave(flags);
matroxfb_DAC_out(PMINFO 0x87, reg);
val = matroxfb_DAC_in(PMINFO 0x88);
matroxfb_DAC_out(minfo, 0x87, reg);
val = matroxfb_DAC_in(minfo, 0x88);
matroxfb_DAC_unlock_irqrestore(flags);
return val;
}
static void cve2_set_reg(WPMINFO int reg, int val) {
static void cve2_set_reg(struct matrox_fb_info *minfo, int reg, int val)
{
unsigned long flags;
matroxfb_DAC_lock_irqsave(flags);
matroxfb_DAC_out(PMINFO 0x87, reg);
matroxfb_DAC_out(PMINFO 0x88, val);
matroxfb_DAC_out(minfo, 0x87, reg);
matroxfb_DAC_out(minfo, 0x88, val);
matroxfb_DAC_unlock_irqrestore(flags);
}
static void cve2_set_reg10(WPMINFO int reg, int val) {
static void cve2_set_reg10(struct matrox_fb_info *minfo, int reg, int val)
{
unsigned long flags;
matroxfb_DAC_lock_irqsave(flags);
matroxfb_DAC_out(PMINFO 0x87, reg);
matroxfb_DAC_out(PMINFO 0x88, val >> 2);
matroxfb_DAC_out(PMINFO 0x87, reg + 1);
matroxfb_DAC_out(PMINFO 0x88, val & 3);
matroxfb_DAC_out(minfo, 0x87, reg);
matroxfb_DAC_out(minfo, 0x88, val >> 2);
matroxfb_DAC_out(minfo, 0x87, reg + 1);
matroxfb_DAC_out(minfo, 0x88, val & 3);
matroxfb_DAC_unlock_irqrestore(flags);
}
static void g450_compute_bwlevel(CPMINFO int *bl, int *wl) {
const int b = ACCESS_FBINFO(altout.tvo_params.brightness) + BLMIN;
const int c = ACCESS_FBINFO(altout.tvo_params.contrast);
static void g450_compute_bwlevel(const struct matrox_fb_info *minfo, int *bl,
int *wl)
{
const int b = minfo->altout.tvo_params.brightness + BLMIN;
const int c = minfo->altout.tvo_params.contrast;
*bl = max(b - c, BLMIN);
*wl = min(b + c, WLMAX);
@@ -154,7 +161,7 @@ static int g450_query_ctrl(void* md, struct v4l2_queryctrl *p) {
static int g450_set_ctrl(void* md, struct v4l2_control *p) {
int i;
MINFO_FROM(md);
struct matrox_fb_info *minfo = md;
i = get_ctrl_id(p->id);
if (i < 0) return -EINVAL;
@@ -162,7 +169,7 @@ static int g450_set_ctrl(void* md, struct v4l2_control *p) {
/*
* Check if changed.
*/
if (p->value == *get_ctrl_ptr(PMINFO i)) return 0;
if (p->value == *get_ctrl_ptr(minfo, i)) return 0;
/*
* Check limits.
@@ -173,31 +180,31 @@ static int g450_set_ctrl(void* md, struct v4l2_control *p) {
/*
* Store new value.
*/
*get_ctrl_ptr(PMINFO i) = p->value;
*get_ctrl_ptr(minfo, i) = p->value;
switch (p->id) {
case V4L2_CID_BRIGHTNESS:
case V4L2_CID_CONTRAST:
{
int blacklevel, whitelevel;
g450_compute_bwlevel(PMINFO &blacklevel, &whitelevel);
cve2_set_reg10(PMINFO 0x0e, blacklevel);
cve2_set_reg10(PMINFO 0x1e, whitelevel);
g450_compute_bwlevel(minfo, &blacklevel, &whitelevel);
cve2_set_reg10(minfo, 0x0e, blacklevel);
cve2_set_reg10(minfo, 0x1e, whitelevel);
}
break;
case V4L2_CID_SATURATION:
cve2_set_reg(PMINFO 0x20, p->value);
cve2_set_reg(PMINFO 0x22, p->value);
cve2_set_reg(minfo, 0x20, p->value);
cve2_set_reg(minfo, 0x22, p->value);
break;
case V4L2_CID_HUE:
cve2_set_reg(PMINFO 0x25, p->value);
cve2_set_reg(minfo, 0x25, p->value);
break;
case MATROXFB_CID_TESTOUT:
{
unsigned char val = cve2_get_reg (PMINFO 0x05);
unsigned char val = cve2_get_reg(minfo, 0x05);
if (p->value) val |= 0x02;
else val &= ~0x02;
cve2_set_reg(PMINFO 0x05, val);
cve2_set_reg(minfo, 0x05, val);
}
break;
}
@@ -208,11 +215,11 @@ static int g450_set_ctrl(void* md, struct v4l2_control *p) {
static int g450_get_ctrl(void* md, struct v4l2_control *p) {
int i;
MINFO_FROM(md);
struct matrox_fb_info *minfo = md;
i = get_ctrl_id(p->id);
if (i < 0) return -EINVAL;
p->value = *get_ctrl_ptr(PMINFO i);
p->value = *get_ctrl_ptr(minfo, i);
return 0;
}
@@ -226,7 +233,9 @@ struct output_desc {
unsigned int v_total;
};
static void computeRegs(WPMINFO struct mavenregs* r, struct my_timming* mt, const struct output_desc* outd) {
static void computeRegs(struct matrox_fb_info *minfo, struct mavenregs *r,
struct my_timming *mt, const struct output_desc *outd)
{
u_int32_t chromasc;
u_int32_t hlen;
u_int32_t hsl;
@@ -251,10 +260,10 @@ static void computeRegs(WPMINFO struct mavenregs* r, struct my_timming* mt, cons
dprintk(KERN_DEBUG "Want %u kHz pixclock\n", (unsigned int)piic);
mnp = matroxfb_g450_setclk(PMINFO piic, M_VIDEO_PLL);
mnp = matroxfb_g450_setclk(minfo, piic, M_VIDEO_PLL);
mt->mnp = mnp;
mt->pixclock = g450_mnp2f(PMINFO mnp);
mt->pixclock = g450_mnp2f(minfo, mnp);
dprintk(KERN_DEBUG "MNP=%08X\n", mnp);
@@ -490,65 +499,67 @@ static void cve2_init_TVdata(int norm, struct mavenregs* data, const struct outp
return;
}
#define LR(x) cve2_set_reg(PMINFO (x), m->regs[(x)])
static void cve2_init_TV(WPMINFO const struct mavenregs* m) {
#define LR(x) cve2_set_reg(minfo, (x), m->regs[(x)])
static void cve2_init_TV(struct matrox_fb_info *minfo,
const struct mavenregs *m)
{
int i;
LR(0x80);
LR(0x82); LR(0x83);
LR(0x84); LR(0x85);
cve2_set_reg(PMINFO 0x3E, 0x01);
cve2_set_reg(minfo, 0x3E, 0x01);
for (i = 0; i < 0x3E; i++) {
LR(i);
}
cve2_set_reg(PMINFO 0x3E, 0x00);
cve2_set_reg(minfo, 0x3E, 0x00);
}
static int matroxfb_g450_compute(void* md, struct my_timming* mt) {
MINFO_FROM(md);
struct matrox_fb_info *minfo = md;
dprintk(KERN_DEBUG "Computing, mode=%u\n", ACCESS_FBINFO(outputs[1]).mode);
dprintk(KERN_DEBUG "Computing, mode=%u\n", minfo->outputs[1].mode);
if (mt->crtc == MATROXFB_SRC_CRTC2 &&
ACCESS_FBINFO(outputs[1]).mode != MATROXFB_OUTPUT_MODE_MONITOR) {
minfo->outputs[1].mode != MATROXFB_OUTPUT_MODE_MONITOR) {
const struct output_desc* outd;
cve2_init_TVdata(ACCESS_FBINFO(outputs[1]).mode, &ACCESS_FBINFO(hw).maven, &outd);
cve2_init_TVdata(minfo->outputs[1].mode, &minfo->hw.maven, &outd);
{
int blacklevel, whitelevel;
g450_compute_bwlevel(PMINFO &blacklevel, &whitelevel);
ACCESS_FBINFO(hw).maven.regs[0x0E] = blacklevel >> 2;
ACCESS_FBINFO(hw).maven.regs[0x0F] = blacklevel & 3;
ACCESS_FBINFO(hw).maven.regs[0x1E] = whitelevel >> 2;
ACCESS_FBINFO(hw).maven.regs[0x1F] = whitelevel & 3;
g450_compute_bwlevel(minfo, &blacklevel, &whitelevel);
minfo->hw.maven.regs[0x0E] = blacklevel >> 2;
minfo->hw.maven.regs[0x0F] = blacklevel & 3;
minfo->hw.maven.regs[0x1E] = whitelevel >> 2;
minfo->hw.maven.regs[0x1F] = whitelevel & 3;
ACCESS_FBINFO(hw).maven.regs[0x20] =
ACCESS_FBINFO(hw).maven.regs[0x22] = ACCESS_FBINFO(altout.tvo_params.saturation);
minfo->hw.maven.regs[0x20] =
minfo->hw.maven.regs[0x22] = minfo->altout.tvo_params.saturation;
ACCESS_FBINFO(hw).maven.regs[0x25] = ACCESS_FBINFO(altout.tvo_params.hue);
minfo->hw.maven.regs[0x25] = minfo->altout.tvo_params.hue;
if (ACCESS_FBINFO(altout.tvo_params.testout)) {
ACCESS_FBINFO(hw).maven.regs[0x05] |= 0x02;
if (minfo->altout.tvo_params.testout) {
minfo->hw.maven.regs[0x05] |= 0x02;
}
}
computeRegs(PMINFO &ACCESS_FBINFO(hw).maven, mt, outd);
computeRegs(minfo, &minfo->hw.maven, mt, outd);
} else if (mt->mnp < 0) {
/* We must program clocks before CRTC2, otherwise interlaced mode
startup may fail */
mt->mnp = matroxfb_g450_setclk(PMINFO mt->pixclock, (mt->crtc == MATROXFB_SRC_CRTC1) ? M_PIXEL_PLL_C : M_VIDEO_PLL);
mt->pixclock = g450_mnp2f(PMINFO mt->mnp);
mt->mnp = matroxfb_g450_setclk(minfo, mt->pixclock, (mt->crtc == MATROXFB_SRC_CRTC1) ? M_PIXEL_PLL_C : M_VIDEO_PLL);
mt->pixclock = g450_mnp2f(minfo, mt->mnp);
}
dprintk(KERN_DEBUG "Pixclock = %u\n", mt->pixclock);
return 0;
}
static int matroxfb_g450_program(void* md) {
MINFO_FROM(md);
struct matrox_fb_info *minfo = md;
if (ACCESS_FBINFO(outputs[1]).mode != MATROXFB_OUTPUT_MODE_MONITOR) {
cve2_init_TV(PMINFO &ACCESS_FBINFO(hw).maven);
if (minfo->outputs[1].mode != MATROXFB_OUTPUT_MODE_MONITOR) {
cve2_init_TV(minfo, &minfo->hw.maven);
}
return 0;
}
@@ -564,11 +575,11 @@ static int matroxfb_g450_verify_mode(void* md, u_int32_t arg) {
}
static int g450_dvi_compute(void* md, struct my_timming* mt) {
MINFO_FROM(md);
struct matrox_fb_info *minfo = md;
if (mt->mnp < 0) {
mt->mnp = matroxfb_g450_setclk(PMINFO mt->pixclock, (mt->crtc == MATROXFB_SRC_CRTC1) ? M_PIXEL_PLL_C : M_VIDEO_PLL);
mt->pixclock = g450_mnp2f(PMINFO mt->mnp);
mt->mnp = matroxfb_g450_setclk(minfo, mt->pixclock, (mt->crtc == MATROXFB_SRC_CRTC1) ? M_PIXEL_PLL_C : M_VIDEO_PLL);
mt->pixclock = g450_mnp2f(minfo, mt->mnp);
}
return 0;
}
@@ -588,34 +599,36 @@ static struct matrox_altout matroxfb_g450_dvi = {
.compute = g450_dvi_compute,
};
void matroxfb_g450_connect(WPMINFO2) {
if (ACCESS_FBINFO(devflags.g450dac)) {
down_write(&ACCESS_FBINFO(altout.lock));
tvo_fill_defaults(PMINFO2);
ACCESS_FBINFO(outputs[1]).src = ACCESS_FBINFO(outputs[1]).default_src;
ACCESS_FBINFO(outputs[1]).data = MINFO;
ACCESS_FBINFO(outputs[1]).output = &matroxfb_g450_altout;
ACCESS_FBINFO(outputs[1]).mode = MATROXFB_OUTPUT_MODE_MONITOR;
ACCESS_FBINFO(outputs[2]).src = ACCESS_FBINFO(outputs[2]).default_src;
ACCESS_FBINFO(outputs[2]).data = MINFO;
ACCESS_FBINFO(outputs[2]).output = &matroxfb_g450_dvi;
ACCESS_FBINFO(outputs[2]).mode = MATROXFB_OUTPUT_MODE_MONITOR;
up_write(&ACCESS_FBINFO(altout.lock));
void matroxfb_g450_connect(struct matrox_fb_info *minfo)
{
if (minfo->devflags.g450dac) {
down_write(&minfo->altout.lock);
tvo_fill_defaults(minfo);
minfo->outputs[1].src = minfo->outputs[1].default_src;
minfo->outputs[1].data = minfo;
minfo->outputs[1].output = &matroxfb_g450_altout;
minfo->outputs[1].mode = MATROXFB_OUTPUT_MODE_MONITOR;
minfo->outputs[2].src = minfo->outputs[2].default_src;
minfo->outputs[2].data = minfo;
minfo->outputs[2].output = &matroxfb_g450_dvi;
minfo->outputs[2].mode = MATROXFB_OUTPUT_MODE_MONITOR;
up_write(&minfo->altout.lock);
}
}
void matroxfb_g450_shutdown(WPMINFO2) {
if (ACCESS_FBINFO(devflags.g450dac)) {
down_write(&ACCESS_FBINFO(altout.lock));
ACCESS_FBINFO(outputs[1]).src = MATROXFB_SRC_NONE;
ACCESS_FBINFO(outputs[1]).output = NULL;
ACCESS_FBINFO(outputs[1]).data = NULL;
ACCESS_FBINFO(outputs[1]).mode = MATROXFB_OUTPUT_MODE_MONITOR;
ACCESS_FBINFO(outputs[2]).src = MATROXFB_SRC_NONE;
ACCESS_FBINFO(outputs[2]).output = NULL;
ACCESS_FBINFO(outputs[2]).data = NULL;
ACCESS_FBINFO(outputs[2]).mode = MATROXFB_OUTPUT_MODE_MONITOR;
up_write(&ACCESS_FBINFO(altout.lock));
void matroxfb_g450_shutdown(struct matrox_fb_info *minfo)
{
if (minfo->devflags.g450dac) {
down_write(&minfo->altout.lock);
minfo->outputs[1].src = MATROXFB_SRC_NONE;
minfo->outputs[1].output = NULL;
minfo->outputs[1].data = NULL;
minfo->outputs[1].mode = MATROXFB_OUTPUT_MODE_MONITOR;
minfo->outputs[2].src = MATROXFB_SRC_NONE;
minfo->outputs[2].output = NULL;
minfo->outputs[2].data = NULL;
minfo->outputs[2].mode = MATROXFB_OUTPUT_MODE_MONITOR;
up_write(&minfo->altout.lock);
}
}

8
drivers/video/matrox/matroxfb_g450.h
View File

@@ -4,11 +4,11 @@
#include "matroxfb_base.h"
#ifdef CONFIG_FB_MATROX_G
void matroxfb_g450_connect(WPMINFO2);
void matroxfb_g450_shutdown(WPMINFO2);
void matroxfb_g450_connect(struct matrox_fb_info *minfo);
void matroxfb_g450_shutdown(struct matrox_fb_info *minfo);
#else
static inline void matroxfb_g450_connect(WPMINFO2) { };
static inline void matroxfb_g450_shutdown(WPMINFO2) { };
static inline void matroxfb_g450_connect(struct matrox_fb_info *minfo) { };
static inline void matroxfb_g450_shutdown(struct matrox_fb_info *minfo) { };
#endif
#endif /* __MATROXFB_G450_H__ */

48
drivers/video/matrox/matroxfb_maven.c
View File

@@ -458,9 +458,9 @@ static void maven_init_TVdata(const struct maven_data* md, struct mavenregs* dat
0x00, /* 3E written multiple times */
0x00, /* never written */
}, MATROXFB_OUTPUT_MODE_NTSC, 525, 60 };
MINFO_FROM(md->primary_head);
struct matrox_fb_info *minfo = md->primary_head;
if (ACCESS_FBINFO(outputs[1]).mode == MATROXFB_OUTPUT_MODE_PAL)
if (minfo->outputs[1].mode == MATROXFB_OUTPUT_MODE_PAL)
*data = palregs;
else
*data = ntscregs;
@@ -496,11 +496,11 @@ static void maven_init_TVdata(const struct maven_data* md, struct mavenregs* dat
/* Set saturation */
{
data->regs[0x20] =
data->regs[0x22] = ACCESS_FBINFO(altout.tvo_params.saturation);
data->regs[0x22] = minfo->altout.tvo_params.saturation;
}
/* Set HUE */
data->regs[0x25] = ACCESS_FBINFO(altout.tvo_params.hue);
data->regs[0x25] = minfo->altout.tvo_params.hue;
return;
}
@@ -741,9 +741,9 @@ static inline int maven_compute_timming(struct maven_data* md,
struct mavenregs* m) {
unsigned int tmpi;
unsigned int a, bv, c;
MINFO_FROM(md->primary_head);
struct matrox_fb_info *minfo = md->primary_head;
m->mode = ACCESS_FBINFO(outputs[1]).mode;
m->mode = minfo->outputs[1].mode;
if (m->mode != MATROXFB_OUTPUT_MODE_MONITOR) {
unsigned int lmargin;
unsigned int umargin;
@@ -1132,7 +1132,7 @@ static int maven_get_control (struct maven_data* md,
static int maven_out_compute(void* md, struct my_timming* mt) {
#define mdinfo ((struct maven_data*)md)
#define minfo (mdinfo->primary_head)
return maven_compute_timming(md, mt, &ACCESS_FBINFO(hw).maven);
return maven_compute_timming(md, mt, &minfo->hw.maven);
#undef minfo
#undef mdinfo
}
@@ -1140,7 +1140,7 @@ static int maven_out_compute(void* md, struct my_timming* mt) {
static int maven_out_program(void* md) {
#define mdinfo ((struct maven_data*)md)
#define minfo (mdinfo->primary_head)
return maven_program_timming(md, &ACCESS_FBINFO(hw).maven);
return maven_program_timming(md, &minfo->hw.maven);
#undef minfo
#undef mdinfo
}
@@ -1184,16 +1184,18 @@ static struct matrox_altout maven_altout = {
static int maven_init_client(struct i2c_client* clnt) {
struct maven_data* md = i2c_get_clientdata(clnt);
MINFO_FROM(container_of(clnt->adapter, struct i2c_bit_adapter, adapter)->minfo);
struct matrox_fb_info *minfo = container_of(clnt->adapter,
struct i2c_bit_adapter,
adapter)->minfo;
md->primary_head = MINFO;
md->primary_head = minfo;
md->client = clnt;
down_write(&ACCESS_FBINFO(altout.lock));
ACCESS_FBINFO(outputs[1]).output = &maven_altout;
ACCESS_FBINFO(outputs[1]).src = ACCESS_FBINFO(outputs[1]).default_src;
ACCESS_FBINFO(outputs[1]).data = md;
ACCESS_FBINFO(outputs[1]).mode = MATROXFB_OUTPUT_MODE_MONITOR;
up_write(&ACCESS_FBINFO(altout.lock));
down_write(&minfo->altout.lock);
minfo->outputs[1].output = &maven_altout;
minfo->outputs[1].src = minfo->outputs[1].default_src;
minfo->outputs[1].data = md;
minfo->outputs[1].mode = MATROXFB_OUTPUT_MODE_MONITOR;
up_write(&minfo->altout.lock);
if (maven_get_reg(clnt, 0xB2) < 0x14) {
md->version = MGATVO_B;
/* Tweak some things for this old chip */
@@ -1218,14 +1220,14 @@ static int maven_shutdown_client(struct i2c_client* clnt) {
struct maven_data* md = i2c_get_clientdata(clnt);
if (md->primary_head) {
MINFO_FROM(md->primary_head);
struct matrox_fb_info *minfo = md->primary_head;
down_write(&ACCESS_FBINFO(altout.lock));
ACCESS_FBINFO(outputs[1]).src = MATROXFB_SRC_NONE;
ACCESS_FBINFO(outputs[1]).output = NULL;
ACCESS_FBINFO(outputs[1]).data = NULL;
ACCESS_FBINFO(outputs[1]).mode = MATROXFB_OUTPUT_MODE_MONITOR;
up_write(&ACCESS_FBINFO(altout.lock));
down_write(&minfo->altout.lock);
minfo->outputs[1].src = MATROXFB_SRC_NONE;
minfo->outputs[1].output = NULL;
minfo->outputs[1].data = NULL;
minfo->outputs[1].mode = MATROXFB_OUTPUT_MODE_MONITOR;
up_write(&minfo->altout.lock);
md->primary_head = NULL;
}
return 0;

288
drivers/video/matrox/matroxfb_misc.c
View File

@@ -89,13 +89,15 @@
#include <linux/interrupt.h>
#include <linux/matroxfb.h>
void matroxfb_DAC_out(CPMINFO int reg, int val) {
void matroxfb_DAC_out(const struct matrox_fb_info *minfo, int reg, int val)
{
DBG_REG(__func__)
mga_outb(M_RAMDAC_BASE+M_X_INDEX, reg);
mga_outb(M_RAMDAC_BASE+M_X_DATAREG, val);
}
int matroxfb_DAC_in(CPMINFO int reg) {
int matroxfb_DAC_in(const struct matrox_fb_info *minfo, int reg)
{
DBG_REG(__func__)
mga_outb(M_RAMDAC_BASE+M_X_INDEX, reg);
return mga_inb(M_RAMDAC_BASE+M_X_DATAREG);
@@ -184,13 +186,14 @@ int matroxfb_PLL_calcclock(const struct matrox_pll_features* pll, unsigned int f
return bestvco;
}
int matroxfb_vgaHWinit(WPMINFO struct my_timming* m) {
int matroxfb_vgaHWinit(struct matrox_fb_info *minfo, struct my_timming *m)
{
unsigned int hd, hs, he, hbe, ht;
unsigned int vd, vs, ve, vt, lc;
unsigned int wd;
unsigned int divider;
int i;
struct matrox_hw_state * const hw = &ACCESS_FBINFO(hw);
struct matrox_hw_state * const hw = &minfo->hw;
DBG(__func__)
@@ -240,7 +243,7 @@ int matroxfb_vgaHWinit(WPMINFO struct my_timming* m) {
/* standard timmings are in 8pixels, but for interleaved we cannot */
/* do it for 4bpp (because of (4bpp >> 1(interleaved))/4 == 0) */
/* using 16 or more pixels per unit can save us */
divider = ACCESS_FBINFO(curr.final_bppShift);
divider = minfo->curr.final_bppShift;
while (divider & 3) {
hd >>= 1;
hs >>= 1;
@@ -270,7 +273,7 @@ int matroxfb_vgaHWinit(WPMINFO struct my_timming* m) {
if (((ht & 0x07) == 0x06) || ((ht & 0x0F) == 0x04))
ht++;
hbe = ht;
wd = ACCESS_FBINFO(fbcon).var.xres_virtual * ACCESS_FBINFO(curr.final_bppShift) / 64;
wd = minfo->fbcon.var.xres_virtual * minfo->curr.final_bppShift / 64;
hw->CRTCEXT[0] = 0;
hw->CRTCEXT[5] = 0;
@@ -287,7 +290,7 @@ int matroxfb_vgaHWinit(WPMINFO struct my_timming* m) {
((hs & 0x100) >> 6) | /* sync start */
(hbe & 0x040); /* end hor. blanking */
/* FIXME: Enable vidrst only on G400, and only if TV-out is used */
if (ACCESS_FBINFO(outputs[1]).src == MATROXFB_SRC_CRTC1)
if (minfo->outputs[1].src == MATROXFB_SRC_CRTC1)
hw->CRTCEXT[1] |= 0x88; /* enable horizontal and vertical vidrst */
hw->CRTCEXT[2] = ((vt & 0xC00) >> 10) |
((vd & 0x400) >> 8) | /* disp end */
@@ -331,9 +334,10 @@ int matroxfb_vgaHWinit(WPMINFO struct my_timming* m) {
return 0;
};
void matroxfb_vgaHWrestore(WPMINFO2) {
void matroxfb_vgaHWrestore(struct matrox_fb_info *minfo)
{
int i;
struct matrox_hw_state * const hw = &ACCESS_FBINFO(hw);
struct matrox_hw_state * const hw = &minfo->hw;
CRITFLAGS
DBG(__func__)
@@ -522,7 +526,9 @@ static void parse_bios(unsigned char __iomem* vbios, struct matrox_bios* bd) {
#endif
}
static int parse_pins1(WPMINFO const struct matrox_bios* bd) {
static int parse_pins1(struct matrox_fb_info *minfo,
const struct matrox_bios *bd)
{
unsigned int maxdac;
switch (bd->pins[22]) {
@@ -533,173 +539,188 @@ static int parse_pins1(WPMINFO const struct matrox_bios* bd) {
if (get_unaligned_le16(bd->pins + 24)) {
maxdac = get_unaligned_le16(bd->pins + 24) * 10;
}
MINFO->limits.pixel.vcomax = maxdac;
MINFO->values.pll.system = get_unaligned_le16(bd->pins + 28) ?
minfo->limits.pixel.vcomax = maxdac;
minfo->values.pll.system = get_unaligned_le16(bd->pins + 28) ?
get_unaligned_le16(bd->pins + 28) * 10 : 50000;
/* ignore 4MB, 8MB, module clocks */
MINFO->features.pll.ref_freq = 14318;
MINFO->values.reg.mctlwtst = 0x00030101;
minfo->features.pll.ref_freq = 14318;
minfo->values.reg.mctlwtst = 0x00030101;
return 0;
}
static void default_pins1(WPMINFO2) {
static void default_pins1(struct matrox_fb_info *minfo)
{
/* Millennium */
MINFO->limits.pixel.vcomax = 220000;
MINFO->values.pll.system = 50000;
MINFO->features.pll.ref_freq = 14318;
MINFO->values.reg.mctlwtst = 0x00030101;
minfo->limits.pixel.vcomax = 220000;
minfo->values.pll.system = 50000;
minfo->features.pll.ref_freq = 14318;
minfo->values.reg.mctlwtst = 0x00030101;
}
static int parse_pins2(WPMINFO const struct matrox_bios* bd) {
MINFO->limits.pixel.vcomax =
MINFO->limits.system.vcomax = (bd->pins[41] == 0xFF) ? 230000 : ((bd->pins[41] + 100) * 1000);
MINFO->values.reg.mctlwtst = ((bd->pins[51] & 0x01) ? 0x00000001 : 0) |
static int parse_pins2(struct matrox_fb_info *minfo,
const struct matrox_bios *bd)
{
minfo->limits.pixel.vcomax =
minfo->limits.system.vcomax = (bd->pins[41] == 0xFF) ? 230000 : ((bd->pins[41] + 100) * 1000);
minfo->values.reg.mctlwtst = ((bd->pins[51] & 0x01) ? 0x00000001 : 0) |
((bd->pins[51] & 0x02) ? 0x00000100 : 0) |
((bd->pins[51] & 0x04) ? 0x00010000 : 0) |
((bd->pins[51] & 0x08) ? 0x00020000 : 0);
MINFO->values.pll.system = (bd->pins[43] == 0xFF) ? 50000 : ((bd->pins[43] + 100) * 1000);
MINFO->features.pll.ref_freq = 14318;
minfo->values.pll.system = (bd->pins[43] == 0xFF) ? 50000 : ((bd->pins[43] + 100) * 1000);
minfo->features.pll.ref_freq = 14318;
return 0;
}
static void default_pins2(WPMINFO2) {
static void default_pins2(struct matrox_fb_info *minfo)
{
/* Millennium II, Mystique */
MINFO->limits.pixel.vcomax =
MINFO->limits.system.vcomax = 230000;
MINFO->values.reg.mctlwtst = 0x00030101;
MINFO->values.pll.system = 50000;
MINFO->features.pll.ref_freq = 14318;
minfo->limits.pixel.vcomax =
minfo->limits.system.vcomax = 230000;
minfo->values.reg.mctlwtst = 0x00030101;
minfo->values.pll.system = 50000;
minfo->features.pll.ref_freq = 14318;
}
static int parse_pins3(WPMINFO const struct matrox_bios* bd) {
MINFO->limits.pixel.vcomax =
MINFO->limits.system.vcomax = (bd->pins[36] == 0xFF) ? 230000 : ((bd->pins[36] + 100) * 1000);
MINFO->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 48) == 0xFFFFFFFF ?
static int parse_pins3(struct matrox_fb_info *minfo,
const struct matrox_bios *bd)
{
minfo->limits.pixel.vcomax =
minfo->limits.system.vcomax = (bd->pins[36] == 0xFF) ? 230000 : ((bd->pins[36] + 100) * 1000);
minfo->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 48) == 0xFFFFFFFF ?
0x01250A21 : get_unaligned_le32(bd->pins + 48);
/* memory config */
MINFO->values.reg.memrdbk = ((bd->pins[57] << 21) & 0x1E000000) |
minfo->values.reg.memrdbk = ((bd->pins[57] << 21) & 0x1E000000) |
((bd->pins[57] << 22) & 0x00C00000) |
((bd->pins[56] << 1) & 0x000001E0) |
( bd->pins[56] & 0x0000000F);
MINFO->values.reg.opt = (bd->pins[54] & 7) << 10;
MINFO->values.reg.opt2 = bd->pins[58] << 12;
MINFO->features.pll.ref_freq = (bd->pins[52] & 0x20) ? 14318 : 27000;
minfo->values.reg.opt = (bd->pins[54] & 7) << 10;
minfo->values.reg.opt2 = bd->pins[58] << 12;
minfo->features.pll.ref_freq = (bd->pins[52] & 0x20) ? 14318 : 27000;
return 0;
}
static void default_pins3(WPMINFO2) {
static void default_pins3(struct matrox_fb_info *minfo)
{
/* G100, G200 */
MINFO->limits.pixel.vcomax =
MINFO->limits.system.vcomax = 230000;
MINFO->values.reg.mctlwtst = 0x01250A21;
MINFO->values.reg.memrdbk = 0x00000000;
MINFO->values.reg.opt = 0x00000C00;
MINFO->values.reg.opt2 = 0x00000000;
MINFO->features.pll.ref_freq = 27000;
minfo->limits.pixel.vcomax =
minfo->limits.system.vcomax = 230000;
minfo->values.reg.mctlwtst = 0x01250A21;
minfo->values.reg.memrdbk = 0x00000000;
minfo->values.reg.opt = 0x00000C00;
minfo->values.reg.opt2 = 0x00000000;
minfo->features.pll.ref_freq = 27000;
}
static int parse_pins4(WPMINFO const struct matrox_bios* bd) {
MINFO->limits.pixel.vcomax = (bd->pins[ 39] == 0xFF) ? 230000 : bd->pins[ 39] * 4000;
MINFO->limits.system.vcomax = (bd->pins[ 38] == 0xFF) ? MINFO->limits.pixel.vcomax : bd->pins[ 38] * 4000;
MINFO->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 71);
MINFO->values.reg.memrdbk = ((bd->pins[87] << 21) & 0x1E000000) |
static int parse_pins4(struct matrox_fb_info *minfo,
const struct matrox_bios *bd)
{
minfo->limits.pixel.vcomax = (bd->pins[ 39] == 0xFF) ? 230000 : bd->pins[ 39] * 4000;
minfo->limits.system.vcomax = (bd->pins[ 38] == 0xFF) ? minfo->limits.pixel.vcomax : bd->pins[ 38] * 4000;
minfo->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 71);
minfo->values.reg.memrdbk = ((bd->pins[87] << 21) & 0x1E000000) |
((bd->pins[87] << 22) & 0x00C00000) |
((bd->pins[86] << 1) & 0x000001E0) |
( bd->pins[86] & 0x0000000F);
MINFO->values.reg.opt = ((bd->pins[53] << 15) & 0x00400000) |
minfo->values.reg.opt = ((bd->pins[53] << 15) & 0x00400000) |
((bd->pins[53] << 22) & 0x10000000) |
((bd->pins[53] << 7) & 0x00001C00);
MINFO->values.reg.opt3 = get_unaligned_le32(bd->pins + 67);
MINFO->values.pll.system = (bd->pins[ 65] == 0xFF) ? 200000 : bd->pins[ 65] * 4000;
MINFO->features.pll.ref_freq = (bd->pins[ 92] & 0x01) ? 14318 : 27000;
minfo->values.reg.opt3 = get_unaligned_le32(bd->pins + 67);
minfo->values.pll.system = (bd->pins[ 65] == 0xFF) ? 200000 : bd->pins[ 65] * 4000;
minfo->features.pll.ref_freq = (bd->pins[ 92] & 0x01) ? 14318 : 27000;
return 0;
}
static void default_pins4(WPMINFO2) {
static void default_pins4(struct matrox_fb_info *minfo)
{
/* G400 */
MINFO->limits.pixel.vcomax =
MINFO->limits.system.vcomax = 252000;
MINFO->values.reg.mctlwtst = 0x04A450A1;
MINFO->values.reg.memrdbk = 0x000000E7;
MINFO->values.reg.opt = 0x10000400;
MINFO->values.reg.opt3 = 0x0190A419;
MINFO->values.pll.system = 200000;
MINFO->features.pll.ref_freq = 27000;
minfo->limits.pixel.vcomax =
minfo->limits.system.vcomax = 252000;
minfo->values.reg.mctlwtst = 0x04A450A1;
minfo->values.reg.memrdbk = 0x000000E7;
minfo->values.reg.opt = 0x10000400;
minfo->values.reg.opt3 = 0x0190A419;
minfo->values.pll.system = 200000;
minfo->features.pll.ref_freq = 27000;
}
static int parse_pins5(WPMINFO const struct matrox_bios* bd) {
static int parse_pins5(struct matrox_fb_info *minfo,
const struct matrox_bios *bd)
{
unsigned int mult;
mult = bd->pins[4]?8000:6000;
MINFO->limits.pixel.vcomax = (bd->pins[ 38] == 0xFF) ? 600000 : bd->pins[ 38] * mult;
MINFO->limits.system.vcomax = (bd->pins[ 36] == 0xFF) ? MINFO->limits.pixel.vcomax : bd->pins[ 36] * mult;
MINFO->limits.video.vcomax = (bd->pins[ 37] == 0xFF) ? MINFO->limits.system.vcomax : bd->pins[ 37] * mult;
MINFO->limits.pixel.vcomin = (bd->pins[123] == 0xFF) ? 256000 : bd->pins[123] * mult;
MINFO->limits.system.vcomin = (bd->pins[121] == 0xFF) ? MINFO->limits.pixel.vcomin : bd->pins[121] * mult;
MINFO->limits.video.vcomin = (bd->pins[122] == 0xFF) ? MINFO->limits.system.vcomin : bd->pins[122] * mult;
MINFO->values.pll.system =
MINFO->values.pll.video = (bd->pins[ 92] == 0xFF) ? 284000 : bd->pins[ 92] * 4000;
MINFO->values.reg.opt = get_unaligned_le32(bd->pins + 48);
MINFO->values.reg.opt2 = get_unaligned_le32(bd->pins + 52);
MINFO->values.reg.opt3 = get_unaligned_le32(bd->pins + 94);
MINFO->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 98);
MINFO->values.reg.memmisc = get_unaligned_le32(bd->pins + 102);
MINFO->values.reg.memrdbk = get_unaligned_le32(bd->pins + 106);
MINFO->features.pll.ref_freq = (bd->pins[110] & 0x01) ? 14318 : 27000;
MINFO->values.memory.ddr = (bd->pins[114] & 0x60) == 0x20;
MINFO->values.memory.dll = (bd->pins[115] & 0x02) != 0;
MINFO->values.memory.emrswen = (bd->pins[115] & 0x01) != 0;
MINFO->values.reg.maccess = MINFO->values.memory.emrswen ? 0x00004000 : 0x00000000;
minfo->limits.pixel.vcomax = (bd->pins[ 38] == 0xFF) ? 600000 : bd->pins[ 38] * mult;
minfo->limits.system.vcomax = (bd->pins[ 36] == 0xFF) ? minfo->limits.pixel.vcomax : bd->pins[ 36] * mult;
minfo->limits.video.vcomax = (bd->pins[ 37] == 0xFF) ? minfo->limits.system.vcomax : bd->pins[ 37] * mult;
minfo->limits.pixel.vcomin = (bd->pins[123] == 0xFF) ? 256000 : bd->pins[123] * mult;
minfo->limits.system.vcomin = (bd->pins[121] == 0xFF) ? minfo->limits.pixel.vcomin : bd->pins[121] * mult;
minfo->limits.video.vcomin = (bd->pins[122] == 0xFF) ? minfo->limits.system.vcomin : bd->pins[122] * mult;
minfo->values.pll.system =
minfo->values.pll.video = (bd->pins[ 92] == 0xFF) ? 284000 : bd->pins[ 92] * 4000;
minfo->values.reg.opt = get_unaligned_le32(bd->pins + 48);
minfo->values.reg.opt2 = get_unaligned_le32(bd->pins + 52);
minfo->values.reg.opt3 = get_unaligned_le32(bd->pins + 94);
minfo->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 98);
minfo->values.reg.memmisc = get_unaligned_le32(bd->pins + 102);
minfo->values.reg.memrdbk = get_unaligned_le32(bd->pins + 106);
minfo->features.pll.ref_freq = (bd->pins[110] & 0x01) ? 14318 : 27000;
minfo->values.memory.ddr = (bd->pins[114] & 0x60) == 0x20;
minfo->values.memory.dll = (bd->pins[115] & 0x02) != 0;
minfo->values.memory.emrswen = (bd->pins[115] & 0x01) != 0;
minfo->values.reg.maccess = minfo->values.memory.emrswen ? 0x00004000 : 0x00000000;
if (bd->pins[115] & 4) {
MINFO->values.reg.mctlwtst_core = MINFO->values.reg.mctlwtst;
minfo->values.reg.mctlwtst_core = minfo->values.reg.mctlwtst;
} else {
u_int32_t wtst_xlat[] = { 0, 1, 5, 6, 7, 5, 2, 3 };
MINFO->values.reg.mctlwtst_core = (MINFO->values.reg.mctlwtst & ~7) |
wtst_xlat[MINFO->values.reg.mctlwtst & 7];
minfo->values.reg.mctlwtst_core = (minfo->values.reg.mctlwtst & ~7) |
wtst_xlat[minfo->values.reg.mctlwtst & 7];
}
MINFO->max_pixel_clock_panellink = bd->pins[47] * 4000;
minfo->max_pixel_clock_panellink = bd->pins[47] * 4000;
return 0;
}
static void default_pins5(WPMINFO2) {
static void default_pins5(struct matrox_fb_info *minfo)
{
/* Mine 16MB G450 with SDRAM DDR */
MINFO->limits.pixel.vcomax =
MINFO->limits.system.vcomax =
MINFO->limits.video.vcomax = 600000;
MINFO->limits.pixel.vcomin =
MINFO->limits.system.vcomin =
MINFO->limits.video.vcomin = 256000;
MINFO->values.pll.system =
MINFO->values.pll.video = 284000;
MINFO->values.reg.opt = 0x404A1160;
MINFO->values.reg.opt2 = 0x0000AC00;
MINFO->values.reg.opt3 = 0x0090A409;
MINFO->values.reg.mctlwtst_core =
MINFO->values.reg.mctlwtst = 0x0C81462B;
MINFO->values.reg.memmisc = 0x80000004;
MINFO->values.reg.memrdbk = 0x01001103;
MINFO->features.pll.ref_freq = 27000;
MINFO->values.memory.ddr = 1;
MINFO->values.memory.dll = 1;
MINFO->values.memory.emrswen = 1;
MINFO->values.reg.maccess = 0x00004000;
minfo->limits.pixel.vcomax =
minfo->limits.system.vcomax =
minfo->limits.video.vcomax = 600000;
minfo->limits.pixel.vcomin =
minfo->limits.system.vcomin =
minfo->limits.video.vcomin = 256000;
minfo->values.pll.system =
minfo->values.pll.video = 284000;
minfo->values.reg.opt = 0x404A1160;
minfo->values.reg.opt2 = 0x0000AC00;
minfo->values.reg.opt3 = 0x0090A409;
minfo->values.reg.mctlwtst_core =
minfo->values.reg.mctlwtst = 0x0C81462B;
minfo->values.reg.memmisc = 0x80000004;
minfo->values.reg.memrdbk = 0x01001103;
minfo->features.pll.ref_freq = 27000;
minfo->values.memory.ddr = 1;
minfo->values.memory.dll = 1;
minfo->values.memory.emrswen = 1;
minfo->values.reg.maccess = 0x00004000;
}
static int matroxfb_set_limits(WPMINFO const struct matrox_bios* bd) {
static int matroxfb_set_limits(struct matrox_fb_info *minfo,
const struct matrox_bios *bd)
{
unsigned int pins_version;
static const unsigned int pinslen[] = { 64, 64, 64, 128, 128 };
switch (ACCESS_FBINFO(chip)) {
case MGA_2064: default_pins1(PMINFO2); break;
switch (minfo->chip) {
case MGA_2064: default_pins1(minfo); break;
case MGA_2164:
case MGA_1064:
case MGA_1164: default_pins2(PMINFO2); break;
case MGA_1164: default_pins2(minfo); break;
case MGA_G100:
case MGA_G200: default_pins3(PMINFO2); break;
case MGA_G400: default_pins4(PMINFO2); break;
case MGA_G200: default_pins3(minfo); break;
case MGA_G400: default_pins4(minfo); break;
case MGA_G450:
case MGA_G550: default_pins5(PMINFO2); break;
case MGA_G550: default_pins5(minfo); break;
}
if (!bd->bios_valid) {
printk(KERN_INFO "matroxfb: Your Matrox device does not have BIOS\n");
@@ -724,38 +745,39 @@ static int matroxfb_set_limits(WPMINFO const struct matrox_bios* bd) {
}
switch (pins_version) {
case 1:
return parse_pins1(PMINFO bd);
return parse_pins1(minfo, bd);
case 2:
return parse_pins2(PMINFO bd);
return parse_pins2(minfo, bd);
case 3:
return parse_pins3(PMINFO bd);
return parse_pins3(minfo, bd);
case 4:
return parse_pins4(PMINFO bd);
return parse_pins4(minfo, bd);
case 5:
return parse_pins5(PMINFO bd);
return parse_pins5(minfo, bd);
default:
printk(KERN_DEBUG "matroxfb: Powerup info version %u is not yet supported\n", pins_version);
return -1;
}
}
void matroxfb_read_pins(WPMINFO2) {
void matroxfb_read_pins(struct matrox_fb_info *minfo)
{
u32 opt;
u32 biosbase;
u32 fbbase;
struct pci_dev* pdev = ACCESS_FBINFO(pcidev);
struct pci_dev *pdev = minfo->pcidev;
memset(&ACCESS_FBINFO(bios), 0, sizeof(ACCESS_FBINFO(bios)));
memset(&minfo->bios, 0, sizeof(minfo->bios));
pci_read_config_dword(pdev, PCI_OPTION_REG, &opt);
pci_write_config_dword(pdev, PCI_OPTION_REG, opt | PCI_OPTION_ENABLE_ROM);
pci_read_config_dword(pdev, PCI_ROM_ADDRESS, &biosbase);
pci_read_config_dword(pdev, ACCESS_FBINFO(devflags.fbResource), &fbbase);
pci_read_config_dword(pdev, minfo->devflags.fbResource, &fbbase);
pci_write_config_dword(pdev, PCI_ROM_ADDRESS, (fbbase & PCI_ROM_ADDRESS_MASK) | PCI_ROM_ADDRESS_ENABLE);
parse_bios(vaddr_va(ACCESS_FBINFO(video).vbase), &ACCESS_FBINFO(bios));
parse_bios(vaddr_va(minfo->video.vbase), &minfo->bios);
pci_write_config_dword(pdev, PCI_ROM_ADDRESS, biosbase);
pci_write_config_dword(pdev, PCI_OPTION_REG, opt);
#ifdef CONFIG_X86
if (!ACCESS_FBINFO(bios).bios_valid) {
if (!minfo->bios.bios_valid) {
unsigned char __iomem* b;
b = ioremap(0x000C0000, 65536);
@@ -769,25 +791,21 @@ void matroxfb_read_pins(WPMINFO2) {
printk(KERN_INFO "matroxfb: Legacy BIOS is for %04X:%04X, while this device is %04X:%04X\n",
ven, dev, pdev->vendor, pdev->device);
} else {
parse_bios(b, &ACCESS_FBINFO(bios));
parse_bios(b, &minfo->bios);
}
iounmap(b);
}
}
#endif
matroxfb_set_limits(PMINFO &ACCESS_FBINFO(bios));
matroxfb_set_limits(minfo, &minfo->bios);
printk(KERN_INFO "PInS memtype = %u\n",
(ACCESS_FBINFO(values).reg.opt & 0x1C00) >> 10);
(minfo->values.reg.opt & 0x1C00) >> 10);
}
EXPORT_SYMBOL(matroxfb_DAC_in);
EXPORT_SYMBOL(matroxfb_DAC_out);
EXPORT_SYMBOL(matroxfb_var2my);
EXPORT_SYMBOL(matroxfb_PLL_calcclock);
#ifndef CONFIG_FB_MATROX_MULTIHEAD
struct matrox_fb_info matroxfb_global_mxinfo;
EXPORT_SYMBOL(matroxfb_global_mxinfo);
#endif
EXPORT_SYMBOL(matroxfb_vgaHWinit); /* DAC1064, Ti3026 */
EXPORT_SYMBOL(matroxfb_vgaHWrestore); /* DAC1064, Ti3026 */
EXPORT_SYMBOL(matroxfb_read_pins);

15
drivers/video/matrox/matroxfb_misc.h
View File

@@ -6,13 +6,16 @@
/* also for modules */
int matroxfb_PLL_calcclock(const struct matrox_pll_features* pll, unsigned int freq, unsigned int fmax,
unsigned int* in, unsigned int* feed, unsigned int* post);
static inline int PLL_calcclock(CPMINFO unsigned int freq, unsigned int fmax,
unsigned int* in, unsigned int* feed, unsigned int* post) {
return matroxfb_PLL_calcclock(&ACCESS_FBINFO(features.pll), freq, fmax, in, feed, post);
static inline int PLL_calcclock(const struct matrox_fb_info *minfo,
unsigned int freq, unsigned int fmax,
unsigned int *in, unsigned int *feed,
unsigned int *post)
{
return matroxfb_PLL_calcclock(&minfo->features.pll, freq, fmax, in, feed, post);
}
int matroxfb_vgaHWinit(WPMINFO struct my_timming* m);
void matroxfb_vgaHWrestore(WPMINFO2);
void matroxfb_read_pins(WPMINFO2);
int matroxfb_vgaHWinit(struct matrox_fb_info *minfo, struct my_timming* m);
void matroxfb_vgaHWrestore(struct matrox_fb_info *minfo);
void matroxfb_read_pins(struct matrox_fb_info *minfo);
#endif /* __MATROXFB_MISC_H__ */

19
drivers/video/msm/Makefile Normal file
View File

@@ -0,0 +1,19 @@
# core framebuffer
#
obj-y := msm_fb.o
# MDP DMA/PPP engine
#
obj-y += mdp.o mdp_scale_tables.o mdp_ppp.o
# MDDI interface
#
obj-y += mddi.o
# MDDI client/panel drivers
#
obj-y += mddi_client_dummy.o
obj-y += mddi_client_toshiba.o
obj-y += mddi_client_nt35399.o

828
drivers/video/msm/mddi.c Normal file
View File

@@ -0,0 +1,828 @@
/*
* MSM MDDI Transport
*
* Copyright (C) 2007 Google Incorporated
* Copyright (C) 2007 QUALCOMM Incorporated
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/dma-mapping.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/spinlock.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <mach/msm_iomap.h>
#include <mach/irqs.h>
#include <mach/board.h>
#include <linux/delay.h>
#include <mach/msm_fb.h>
#include "mddi_hw.h"
#define FLAG_DISABLE_HIBERNATION 0x0001
#define FLAG_HAVE_CAPS 0x0002
#define FLAG_HAS_VSYNC_IRQ 0x0004
#define FLAG_HAVE_STATUS 0x0008
#define CMD_GET_CLIENT_CAP 0x0601
#define CMD_GET_CLIENT_STATUS 0x0602
union mddi_rev {
unsigned char raw[MDDI_REV_BUFFER_SIZE];
struct mddi_rev_packet hdr;
struct mddi_client_status status;
struct mddi_client_caps caps;
struct mddi_register_access reg;
};
struct reg_read_info {
struct completion done;
uint32_t reg;
uint32_t status;
uint32_t result;
};
struct mddi_info {
uint16_t flags;
uint16_t version;
char __iomem *base;
int irq;
struct clk *clk;
struct msm_mddi_client_data client_data;
/* buffer for rev encap packets */
void *rev_data;
dma_addr_t rev_addr;
struct mddi_llentry *reg_write_data;
dma_addr_t reg_write_addr;
struct mddi_llentry *reg_read_data;
dma_addr_t reg_read_addr;
size_t rev_data_curr;
spinlock_t int_lock;
uint32_t int_enable;
uint32_t got_int;
wait_queue_head_t int_wait;
struct mutex reg_write_lock;
struct mutex reg_read_lock;
struct reg_read_info *reg_read;
struct mddi_client_caps caps;
struct mddi_client_status status;
void (*power_client)(struct msm_mddi_client_data *, int);
/* client device published to bind us to the
* appropriate mddi_client driver
*/
char client_name[20];
struct platform_device client_pdev;
};
static void mddi_init_rev_encap(struct mddi_info *mddi);
#define mddi_readl(r) readl(mddi->base + (MDDI_##r))
#define mddi_writel(v, r) writel((v), mddi->base + (MDDI_##r))
void mddi_activate_link(struct msm_mddi_client_data *cdata)
{
struct mddi_info *mddi = container_of(cdata, struct mddi_info,
client_data);
mddi_writel(MDDI_CMD_LINK_ACTIVE, CMD);
}
static void mddi_handle_link_list_done(struct mddi_info *mddi)
{
}
static void mddi_reset_rev_encap_ptr(struct mddi_info *mddi)
{
printk(KERN_INFO "mddi: resetting rev ptr\n");
mddi->rev_data_curr = 0;
mddi_writel(mddi->rev_addr, REV_PTR);
mddi_writel(mddi->rev_addr, REV_PTR);
mddi_writel(MDDI_CMD_FORCE_NEW_REV_PTR, CMD);
}
static void mddi_handle_rev_data(struct mddi_info *mddi, union mddi_rev *rev)
{
int i;
struct reg_read_info *ri;
if ((rev->hdr.length <= MDDI_REV_BUFFER_SIZE - 2) &&
(rev->hdr.length >= sizeof(struct mddi_rev_packet) - 2)) {
switch (rev->hdr.type) {
case TYPE_CLIENT_CAPS:
memcpy(&mddi->caps, &rev->caps,
sizeof(struct mddi_client_caps));
mddi->flags |= FLAG_HAVE_CAPS;
wake_up(&mddi->int_wait);
break;
case TYPE_CLIENT_STATUS:
memcpy(&mddi->status, &rev->status,
sizeof(struct mddi_client_status));
mddi->flags |= FLAG_HAVE_STATUS;
wake_up(&mddi->int_wait);
break;
case TYPE_REGISTER_ACCESS:
ri = mddi->reg_read;
if (ri == 0) {
printk(KERN_INFO "rev: got reg %x = %x without "
" pending read\n",
rev->reg.register_address,
rev->reg.register_data_list);
break;
}
if (ri->reg != rev->reg.register_address) {
printk(KERN_INFO "rev: got reg %x = %x for "
"wrong register, expected "
"%x\n",
rev->reg.register_address,
rev->reg.register_data_list, ri->reg);
break;
}
mddi->reg_read = NULL;
ri->status = 0;
ri->result = rev->reg.register_data_list;
complete(&ri->done);
break;
default:
printk(KERN_INFO "rev: unknown reverse packet: "
"len=%04x type=%04x CURR_REV_PTR=%x\n",
rev->hdr.length, rev->hdr.type,
mddi_readl(CURR_REV_PTR));
for (i = 0; i < rev->hdr.length + 2; i++) {
if ((i % 16) == 0)
printk(KERN_INFO "\n");
printk(KERN_INFO " %02x", rev->raw[i]);
}
printk(KERN_INFO "\n");
mddi_reset_rev_encap_ptr(mddi);
}
} else {
printk(KERN_INFO "bad rev length, %d, CURR_REV_PTR %x\n",
rev->hdr.length, mddi_readl(CURR_REV_PTR));
mddi_reset_rev_encap_ptr(mddi);
}
}
static void mddi_wait_interrupt(struct mddi_info *mddi, uint32_t intmask);
static void mddi_handle_rev_data_avail(struct mddi_info *mddi)
{
union mddi_rev *rev = mddi->rev_data;
uint32_t rev_data_count;
uint32_t rev_crc_err_count;
int i;
struct reg_read_info *ri;
size_t prev_offset;
uint16_t length;
union mddi_rev *crev = mddi->rev_data + mddi->rev_data_curr;
/* clear the interrupt */
mddi_writel(MDDI_INT_REV_DATA_AVAIL, INT);
rev_data_count = mddi_readl(REV_PKT_CNT);
rev_crc_err_count = mddi_readl(REV_CRC_ERR);
if (rev_data_count > 1)
printk(KERN_INFO "rev_data_count %d\n", rev_data_count);
if (rev_crc_err_count) {
printk(KERN_INFO "rev_crc_err_count %d, INT %x\n",
rev_crc_err_count, mddi_readl(INT));
ri = mddi->reg_read;
if (ri == 0) {
printk(KERN_INFO "rev: got crc error without pending "
"read\n");
} else {
mddi->reg_read = NULL;
ri->status = -EIO;
ri->result = -1;
complete(&ri->done);
}
}
if (rev_data_count == 0)
return;
prev_offset = mddi->rev_data_curr;
length = *((uint8_t *)mddi->rev_data + mddi->rev_data_curr);
mddi->rev_data_curr++;
if (mddi->rev_data_curr == MDDI_REV_BUFFER_SIZE)
mddi->rev_data_curr = 0;
length += *((uint8_t *)mddi->rev_data + mddi->rev_data_curr) << 8;
mddi->rev_data_curr += 1 + length;
if (mddi->rev_data_curr >= MDDI_REV_BUFFER_SIZE)
mddi->rev_data_curr =
mddi->rev_data_curr % MDDI_REV_BUFFER_SIZE;
if (length > MDDI_REV_BUFFER_SIZE - 2) {
printk(KERN_INFO "mddi: rev data length greater than buffer"
"size\n");
mddi_reset_rev_encap_ptr(mddi);
return;
}
if (prev_offset + 2 + length >= MDDI_REV_BUFFER_SIZE) {
union mddi_rev tmprev;
size_t rem = MDDI_REV_BUFFER_SIZE - prev_offset;
memcpy(&tmprev.raw[0], mddi->rev_data + prev_offset, rem);
memcpy(&tmprev.raw[rem], mddi->rev_data, 2 + length - rem);
mddi_handle_rev_data(mddi, &tmprev);
} else {
mddi_handle_rev_data(mddi, crev);
}
if (prev_offset < MDDI_REV_BUFFER_SIZE / 2 &&
mddi->rev_data_curr >= MDDI_REV_BUFFER_SIZE / 2) {
mddi_writel(mddi->rev_addr, REV_PTR);
}
}
static irqreturn_t mddi_isr(int irq, void *data)
{
struct msm_mddi_client_data *cdata = data;
struct mddi_info *mddi = container_of(cdata, struct mddi_info,
client_data);
uint32_t active, status;
spin_lock(&mddi->int_lock);
active = mddi_readl(INT);
status = mddi_readl(STAT);
mddi_writel(active, INT);
/* ignore any interrupts we have disabled */
active &= mddi->int_enable;
mddi->got_int |= active;
wake_up(&mddi->int_wait);
if (active & MDDI_INT_PRI_LINK_LIST_DONE) {
mddi->int_enable &= (~MDDI_INT_PRI_LINK_LIST_DONE);
mddi_handle_link_list_done(mddi);
}
if (active & MDDI_INT_REV_DATA_AVAIL)
mddi_handle_rev_data_avail(mddi);
if (active & ~MDDI_INT_NEED_CLEAR)
mddi->int_enable &= ~(active & ~MDDI_INT_NEED_CLEAR);
if (active & MDDI_INT_LINK_ACTIVE) {
mddi->int_enable &= (~MDDI_INT_LINK_ACTIVE);
mddi->int_enable |= MDDI_INT_IN_HIBERNATION;
}
if (active & MDDI_INT_IN_HIBERNATION) {
mddi->int_enable &= (~MDDI_INT_IN_HIBERNATION);
mddi->int_enable |= MDDI_INT_LINK_ACTIVE;
}
mddi_writel(mddi->int_enable, INTEN);
spin_unlock(&mddi->int_lock);
return IRQ_HANDLED;
}
static long mddi_wait_interrupt_timeout(struct mddi_info *mddi,
uint32_t intmask, int timeout)
{
unsigned long irq_flags;
spin_lock_irqsave(&mddi->int_lock, irq_flags);
mddi->got_int &= ~intmask;
mddi->int_enable |= intmask;
mddi_writel(mddi->int_enable, INTEN);
spin_unlock_irqrestore(&mddi->int_lock, irq_flags);
return wait_event_timeout(mddi->int_wait, mddi->got_int & intmask,
timeout);
}
static void mddi_wait_interrupt(struct mddi_info *mddi, uint32_t intmask)
{
if (mddi_wait_interrupt_timeout(mddi, intmask, HZ/10) == 0)
printk(KERN_INFO KERN_ERR "mddi_wait_interrupt %d, timeout "
"waiting for %x, INT = %x, STAT = %x gotint = %x\n",
current->pid, intmask, mddi_readl(INT), mddi_readl(STAT),
mddi->got_int);
}
static void mddi_init_rev_encap(struct mddi_info *mddi)
{
memset(mddi->rev_data, 0xee, MDDI_REV_BUFFER_SIZE);
mddi_writel(mddi->rev_addr, REV_PTR);
mddi_writel(MDDI_CMD_FORCE_NEW_REV_PTR, CMD);
mddi_wait_interrupt(mddi, MDDI_INT_NO_CMD_PKTS_PEND);
}
void mddi_set_auto_hibernate(struct msm_mddi_client_data *cdata, int on)
{
struct mddi_info *mddi = container_of(cdata, struct mddi_info,
client_data);
mddi_writel(MDDI_CMD_POWERDOWN, CMD);
mddi_wait_interrupt(mddi, MDDI_INT_IN_HIBERNATION);
mddi_writel(MDDI_CMD_HIBERNATE | !!on, CMD);
mddi_wait_interrupt(mddi, MDDI_INT_NO_CMD_PKTS_PEND);
}
static uint16_t mddi_init_registers(struct mddi_info *mddi)
{
mddi_writel(0x0001, VERSION);
mddi_writel(MDDI_HOST_BYTES_PER_SUBFRAME, BPS);
mddi_writel(0x0003, SPM); /* subframes per media */
mddi_writel(0x0005, TA1_LEN);
mddi_writel(MDDI_HOST_TA2_LEN, TA2_LEN);
mddi_writel(0x0096, DRIVE_HI);
/* 0x32 normal, 0x50 for Toshiba display */
mddi_writel(0x0050, DRIVE_LO);
mddi_writel(0x003C, DISP_WAKE); /* wakeup counter */
mddi_writel(MDDI_HOST_REV_RATE_DIV, REV_RATE_DIV);
mddi_writel(MDDI_REV_BUFFER_SIZE, REV_SIZE);
mddi_writel(MDDI_MAX_REV_PKT_SIZE, REV_ENCAP_SZ);
/* disable periodic rev encap */
mddi_writel(MDDI_CMD_PERIODIC_REV_ENCAP, CMD);
mddi_wait_interrupt(mddi, MDDI_INT_NO_CMD_PKTS_PEND);
if (mddi_readl(PAD_CTL) == 0) {
/* If we are turning on band gap, need to wait 5us before
* turning on the rest of the PAD */
mddi_writel(0x08000, PAD_CTL);
udelay(5);
}
/* Recommendation from PAD hw team */
mddi_writel(0xa850f, PAD_CTL);
/* Need an even number for counts */
mddi_writel(0x60006, DRIVER_START_CNT);
mddi_set_auto_hibernate(&mddi->client_data, 0);
mddi_writel(MDDI_CMD_DISP_IGNORE, CMD);
mddi_wait_interrupt(mddi, MDDI_INT_NO_CMD_PKTS_PEND);
mddi_init_rev_encap(mddi);
return mddi_readl(CORE_VER) & 0xffff;
}
static void mddi_suspend(struct msm_mddi_client_data *cdata)
{
struct mddi_info *mddi = container_of(cdata, struct mddi_info,
client_data);
/* turn off the client */
if (mddi->power_client)
mddi->power_client(&mddi->client_data, 0);
/* turn off the link */
mddi_writel(MDDI_CMD_RESET, CMD);
mddi_wait_interrupt(mddi, MDDI_INT_NO_CMD_PKTS_PEND);
/* turn off the clock */
clk_disable(mddi->clk);
}
static void mddi_resume(struct msm_mddi_client_data *cdata)
{
struct mddi_info *mddi = container_of(cdata, struct mddi_info,
client_data);
mddi_set_auto_hibernate(&mddi->client_data, 0);
/* turn on the client */
if (mddi->power_client)
mddi->power_client(&mddi->client_data, 1);
/* turn on the clock */
clk_enable(mddi->clk);
/* set up the local registers */
mddi->rev_data_curr = 0;
mddi_init_registers(mddi);
mddi_writel(mddi->int_enable, INTEN);
mddi_writel(MDDI_CMD_LINK_ACTIVE, CMD);
mddi_writel(MDDI_CMD_SEND_RTD, CMD);
mddi_wait_interrupt(mddi, MDDI_INT_NO_CMD_PKTS_PEND);
mddi_set_auto_hibernate(&mddi->client_data, 1);
}
static int __init mddi_get_client_caps(struct mddi_info *mddi)
{
int i, j;
/* clear any stale interrupts */
mddi_writel(0xffffffff, INT);
mddi->int_enable = MDDI_INT_LINK_ACTIVE |
MDDI_INT_IN_HIBERNATION |
MDDI_INT_PRI_LINK_LIST_DONE |
MDDI_INT_REV_DATA_AVAIL |
MDDI_INT_REV_OVERFLOW |
MDDI_INT_REV_OVERWRITE |
MDDI_INT_RTD_FAILURE;
mddi_writel(mddi->int_enable, INTEN);
mddi_writel(MDDI_CMD_LINK_ACTIVE, CMD);
mddi_wait_interrupt(mddi, MDDI_INT_NO_CMD_PKTS_PEND);
for (j = 0; j < 3; j++) {
/* the toshiba vga panel does not respond to get
* caps unless you SEND_RTD, but the first SEND_RTD
* will fail...
*/
for (i = 0; i < 4; i++) {
uint32_t stat;
mddi_writel(MDDI_CMD_SEND_RTD, CMD);
mddi_wait_interrupt(mddi, MDDI_INT_NO_CMD_PKTS_PEND);
stat = mddi_readl(STAT);
printk(KERN_INFO "mddi cmd send rtd: int %x, stat %x, "
"rtd val %x\n", mddi_readl(INT), stat,
mddi_readl(RTD_VAL));
if ((stat & MDDI_STAT_RTD_MEAS_FAIL) == 0)
break;
msleep(1);
}
mddi_writel(CMD_GET_CLIENT_CAP, CMD);
mddi_wait_interrupt(mddi, MDDI_INT_NO_CMD_PKTS_PEND);
wait_event_timeout(mddi->int_wait, mddi->flags & FLAG_HAVE_CAPS,
HZ / 100);
if (mddi->flags & FLAG_HAVE_CAPS)
break;
printk(KERN_INFO KERN_ERR "mddi_init, timeout waiting for "
"caps\n");
}
return mddi->flags & FLAG_HAVE_CAPS;
}
/* link must be active when this is called */
int mddi_check_status(struct mddi_info *mddi)
{
int ret = -1, retry = 3;
mutex_lock(&mddi->reg_read_lock);
mddi_writel(MDDI_CMD_PERIODIC_REV_ENCAP | 1, CMD);
mddi_wait_interrupt(mddi, MDDI_INT_NO_CMD_PKTS_PEND);
do {
mddi->flags &= ~FLAG_HAVE_STATUS;
mddi_writel(CMD_GET_CLIENT_STATUS, CMD);
mddi_wait_interrupt(mddi, MDDI_INT_NO_CMD_PKTS_PEND);
wait_event_timeout(mddi->int_wait,
mddi->flags & FLAG_HAVE_STATUS,
HZ / 100);
if (mddi->flags & FLAG_HAVE_STATUS) {
if (mddi->status.crc_error_count)
printk(KERN_INFO "mddi status: crc_error "
"count: %d\n",
mddi->status.crc_error_count);
else
ret = 0;
break;
} else
printk(KERN_INFO "mddi status: failed to get client "
"status\n");
mddi_writel(MDDI_CMD_SEND_RTD, CMD);
mddi_wait_interrupt(mddi, MDDI_INT_NO_CMD_PKTS_PEND);
} while (--retry);
mddi_writel(MDDI_CMD_PERIODIC_REV_ENCAP | 0, CMD);
mddi_wait_interrupt(mddi, MDDI_INT_NO_CMD_PKTS_PEND);
mutex_unlock(&mddi->reg_read_lock);
return ret;
}
void mddi_remote_write(struct msm_mddi_client_data *cdata, uint32_t val,
uint32_t reg)
{
struct mddi_info *mddi = container_of(cdata, struct mddi_info,
client_data);
struct mddi_llentry *ll;
struct mddi_register_access *ra;
mutex_lock(&mddi->reg_write_lock);
ll = mddi->reg_write_data;
ra = &(ll->u.r);
ra->length = 14 + 4;
ra->type = TYPE_REGISTER_ACCESS;
ra->client_id = 0;
ra->read_write_info = MDDI_WRITE | 1;
ra->crc16 = 0;
ra->register_address = reg;
ra->register_data_list = val;
ll->flags = 1;
ll->header_count = 14;
ll->data_count = 4;
ll->data = mddi->reg_write_addr + offsetof(struct mddi_llentry,
u.r.register_data_list);
ll->next = 0;
ll->reserved = 0;
mddi_writel(mddi->reg_write_addr, PRI_PTR);
mddi_wait_interrupt(mddi, MDDI_INT_PRI_LINK_LIST_DONE);
mutex_unlock(&mddi->reg_write_lock);
}
uint32_t mddi_remote_read(struct msm_mddi_client_data *cdata, uint32_t reg)
{
struct mddi_info *mddi = container_of(cdata, struct mddi_info,
client_data);
struct mddi_llentry *ll;
struct mddi_register_access *ra;
struct reg_read_info ri;
unsigned s;
int retry_count = 2;
unsigned long irq_flags;
mutex_lock(&mddi->reg_read_lock);
ll = mddi->reg_read_data;
ra = &(ll->u.r);
ra->length = 14;
ra->type = TYPE_REGISTER_ACCESS;
ra->client_id = 0;
ra->read_write_info = MDDI_READ | 1;
ra->crc16 = 0;
ra->register_address = reg;
ll->flags = 0x11;
ll->header_count = 14;
ll->data_count = 0;
ll->data = 0;
ll->next = 0;
ll->reserved = 0;
s = mddi_readl(STAT);
ri.reg = reg;
ri.status = -1;
do {
init_completion(&ri.done);
mddi->reg_read = &ri;
mddi_writel(mddi->reg_read_addr, PRI_PTR);
mddi_wait_interrupt(mddi, MDDI_INT_PRI_LINK_LIST_DONE);
/* Enable Periodic Reverse Encapsulation. */
mddi_writel(MDDI_CMD_PERIODIC_REV_ENCAP | 1, CMD);
mddi_wait_interrupt(mddi, MDDI_INT_NO_CMD_PKTS_PEND);
if (wait_for_completion_timeout(&ri.done, HZ/10) == 0 &&
!ri.done.done) {
printk(KERN_INFO "mddi_remote_read(%x) timeout "
"(%d %d %d)\n",
reg, ri.status, ri.result, ri.done.done);
spin_lock_irqsave(&mddi->int_lock, irq_flags);
mddi->reg_read = NULL;
spin_unlock_irqrestore(&mddi->int_lock, irq_flags);
ri.status = -1;
ri.result = -1;
}
if (ri.status == 0)
break;
mddi_writel(MDDI_CMD_SEND_RTD, CMD);
mddi_writel(MDDI_CMD_LINK_ACTIVE, CMD);
mddi_wait_interrupt(mddi, MDDI_INT_NO_CMD_PKTS_PEND);
printk(KERN_INFO "mddi_remote_read: failed, sent "
"MDDI_CMD_SEND_RTD: int %x, stat %x, rtd val %x "
"curr_rev_ptr %x\n", mddi_readl(INT), mddi_readl(STAT),
mddi_readl(RTD_VAL), mddi_readl(CURR_REV_PTR));
} while (retry_count-- > 0);
/* Disable Periodic Reverse Encapsulation. */
mddi_writel(MDDI_CMD_PERIODIC_REV_ENCAP | 0, CMD);
mddi_wait_interrupt(mddi, MDDI_INT_NO_CMD_PKTS_PEND);
mddi->reg_read = NULL;
mutex_unlock(&mddi->reg_read_lock);
return ri.result;
}
static struct mddi_info mddi_info[2];
static int __init mddi_clk_setup(struct platform_device *pdev,
struct mddi_info *mddi,
unsigned long clk_rate)
{
int ret;
/* set up the clocks */
mddi->clk = clk_get(&pdev->dev, "mddi_clk");
if (IS_ERR(mddi->clk)) {
printk(KERN_INFO "mddi: failed to get clock\n");
return PTR_ERR(mddi->clk);
}
ret = clk_enable(mddi->clk);
if (ret)
goto fail;
ret = clk_set_rate(mddi->clk, clk_rate);
if (ret)
goto fail;
return 0;
fail:
clk_put(mddi->clk);
return ret;
}
static int __init mddi_rev_data_setup(struct mddi_info *mddi)
{
void *dma;
dma_addr_t dma_addr;
/* set up dma buffer */
dma = dma_alloc_coherent(NULL, 0x1000, &dma_addr, GFP_KERNEL);
if (dma == 0)
return -ENOMEM;
mddi->rev_data = dma;
mddi->rev_data_curr = 0;
mddi->rev_addr = dma_addr;
mddi->reg_write_data = dma + MDDI_REV_BUFFER_SIZE;
mddi->reg_write_addr = dma_addr + MDDI_REV_BUFFER_SIZE;
mddi->reg_read_data = mddi->reg_write_data + 1;
mddi->reg_read_addr = mddi->reg_write_addr +
sizeof(*mddi->reg_write_data);
return 0;
}
static int __init mddi_probe(struct platform_device *pdev)
{
struct msm_mddi_platform_data *pdata = pdev->dev.platform_data;
struct mddi_info *mddi = &mddi_info[pdev->id];
struct resource *resource;
int ret, i;
resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!resource) {
printk(KERN_ERR "mddi: no associated mem resource!\n");
return -ENOMEM;
}
mddi->base = ioremap(resource->start, resource->end - resource->start);
if (!mddi->base) {
printk(KERN_ERR "mddi: failed to remap base!\n");
ret = -EINVAL;
goto error_ioremap;
}
resource = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
if (!resource) {
printk(KERN_ERR "mddi: no associated irq resource!\n");
ret = -EINVAL;
goto error_get_irq_resource;
}
mddi->irq = resource->start;
printk(KERN_INFO "mddi: init() base=0x%p irq=%d\n", mddi->base,
mddi->irq);
mddi->power_client = pdata->power_client;
mutex_init(&mddi->reg_write_lock);
mutex_init(&mddi->reg_read_lock);
spin_lock_init(&mddi->int_lock);
init_waitqueue_head(&mddi->int_wait);
ret = mddi_clk_setup(pdev, mddi, pdata->clk_rate);
if (ret) {
printk(KERN_ERR "mddi: failed to setup clock!\n");
goto error_clk_setup;
}
ret = mddi_rev_data_setup(mddi);
if (ret) {
printk(KERN_ERR "mddi: failed to setup rev data!\n");
goto error_rev_data;
}
mddi->int_enable = 0;
mddi_writel(mddi->int_enable, INTEN);
ret = request_irq(mddi->irq, mddi_isr, IRQF_DISABLED, "mddi",
&mddi->client_data);
if (ret) {
printk(KERN_ERR "mddi: failed to request enable irq!\n");
goto error_request_irq;
}
/* turn on the mddi client bridge chip */
if (mddi->power_client)
mddi->power_client(&mddi->client_data, 1);
/* initialize the mddi registers */
mddi_set_auto_hibernate(&mddi->client_data, 0);
mddi_writel(MDDI_CMD_RESET, CMD);
mddi_wait_interrupt(mddi, MDDI_INT_NO_CMD_PKTS_PEND);
mddi->version = mddi_init_registers(mddi);
if (mddi->version < 0x20) {
printk(KERN_ERR "mddi: unsupported version 0x%x\n",
mddi->version);
ret = -ENODEV;
goto error_mddi_version;
}
/* read the capabilities off the client */
if (!mddi_get_client_caps(mddi)) {
printk(KERN_INFO "mddi: no client found\n");
/* power down the panel */
mddi_writel(MDDI_CMD_POWERDOWN, CMD);
printk(KERN_INFO "mddi powerdown: stat %x\n", mddi_readl(STAT));
msleep(100);
printk(KERN_INFO "mddi powerdown: stat %x\n", mddi_readl(STAT));
return 0;
}
mddi_set_auto_hibernate(&mddi->client_data, 1);
if (mddi->caps.Mfr_Name == 0 && mddi->caps.Product_Code == 0)
pdata->fixup(&mddi->caps.Mfr_Name, &mddi->caps.Product_Code);
mddi->client_pdev.id = 0;
for (i = 0; i < pdata->num_clients; i++) {
if (pdata->client_platform_data[i].product_id ==
(mddi->caps.Mfr_Name << 16 | mddi->caps.Product_Code)) {
mddi->client_data.private_client_data =
pdata->client_platform_data[i].client_data;
mddi->client_pdev.name =
pdata->client_platform_data[i].name;
mddi->client_pdev.id =
pdata->client_platform_data[i].id;
/* XXX: possibly set clock */
break;
}
}
if (i >= pdata->num_clients)
mddi->client_pdev.name = "mddi_c_dummy";
printk(KERN_INFO "mddi: registering panel %s\n",
mddi->client_pdev.name);
mddi->client_data.suspend = mddi_suspend;
mddi->client_data.resume = mddi_resume;
mddi->client_data.activate_link = mddi_activate_link;
mddi->client_data.remote_write = mddi_remote_write;
mddi->client_data.remote_read = mddi_remote_read;
mddi->client_data.auto_hibernate = mddi_set_auto_hibernate;
mddi->client_data.fb_resource = pdata->fb_resource;
if (pdev->id == 0)
mddi->client_data.interface_type = MSM_MDDI_PMDH_INTERFACE;
else if (pdev->id == 1)
mddi->client_data.interface_type = MSM_MDDI_EMDH_INTERFACE;
else {
printk(KERN_ERR "mddi: can not determine interface %d!\n",
pdev->id);
ret = -EINVAL;
goto error_mddi_interface;
}
mddi->client_pdev.dev.platform_data = &mddi->client_data;
printk(KERN_INFO "mddi: publish: %s\n", mddi->client_name);
platform_device_register(&mddi->client_pdev);
return 0;
error_mddi_interface:
error_mddi_version:
free_irq(mddi->irq, 0);
error_request_irq:
dma_free_coherent(NULL, 0x1000, mddi->rev_data, mddi->rev_addr);
error_rev_data:
error_clk_setup:
error_get_irq_resource:
iounmap(mddi->base);
error_ioremap:
printk(KERN_INFO "mddi: mddi_init() failed (%d)\n", ret);
return ret;
}
static struct platform_driver mddi_driver = {
.probe = mddi_probe,
.driver = { .name = "msm_mddi" },
};
static int __init _mddi_init(void)
{
return platform_driver_register(&mddi_driver);
}
module_init(_mddi_init);

97
drivers/video/msm/mddi_client_dummy.c Normal file
View File

@@ -0,0 +1,97 @@
/* drivers/video/msm_fb/mddi_client_dummy.c
*
* Support for "dummy" mddi client devices which require no
* special initialization code.
*
* Copyright (C) 2007 Google Incorporated
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <mach/msm_fb.h>
struct panel_info {
struct platform_device pdev;
struct msm_panel_data panel_data;
};
static int mddi_dummy_suspend(struct msm_panel_data *panel_data)
{
return 0;
}
static int mddi_dummy_resume(struct msm_panel_data *panel_data)
{
return 0;
}
static int mddi_dummy_blank(struct msm_panel_data *panel_data)
{
return 0;
}
static int mddi_dummy_unblank(struct msm_panel_data *panel_data)
{
return 0;
}
static int mddi_dummy_probe(struct platform_device *pdev)
{
struct msm_mddi_client_data *client_data = pdev->dev.platform_data;
struct panel_info *panel =
kzalloc(sizeof(struct panel_info), GFP_KERNEL);
int ret;
if (!panel)
return -ENOMEM;
platform_set_drvdata(pdev, panel);
panel->panel_data.suspend = mddi_dummy_suspend;
panel->panel_data.resume = mddi_dummy_resume;
panel->panel_data.blank = mddi_dummy_blank;
panel->panel_data.unblank = mddi_dummy_unblank;
panel->panel_data.caps = MSMFB_CAP_PARTIAL_UPDATES;
panel->pdev.name = "msm_panel";
panel->pdev.id = pdev->id;
platform_device_add_resources(&panel->pdev,
client_data->fb_resource, 1);
panel->panel_data.fb_data = client_data->private_client_data;
panel->pdev.dev.platform_data = &panel->panel_data;
ret = platform_device_register(&panel->pdev);
if (ret) {
kfree(panel);
return ret;
}
return 0;
}
static int mddi_dummy_remove(struct platform_device *pdev)
{
struct panel_info *panel = platform_get_drvdata(pdev);
kfree(panel);
return 0;
}
static struct platform_driver mddi_client_dummy = {
.probe = mddi_dummy_probe,
.remove = mddi_dummy_remove,
.driver = { .name = "mddi_c_dummy" },
};
static int __init mddi_client_dummy_init(void)
{
platform_driver_register(&mddi_client_dummy);
return 0;
}
module_init(mddi_client_dummy_init);

255
drivers/video/msm/mddi_client_nt35399.c Normal file
View File

@@ -0,0 +1,255 @@
/* drivers/video/msm_fb/mddi_client_nt35399.c
*
* Support for Novatek NT35399 MDDI client of Sapphire
*
* Copyright (C) 2008 HTC Incorporated
* Author: Solomon Chiu (solomon_chiu@htc.com)
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/gpio.h>
#include <mach/msm_fb.h>
static DECLARE_WAIT_QUEUE_HEAD(nt35399_vsync_wait);
struct panel_info {
struct msm_mddi_client_data *client_data;
struct platform_device pdev;
struct msm_panel_data panel_data;
struct msmfb_callback *fb_callback;
struct work_struct panel_work;
struct workqueue_struct *fb_wq;
int nt35399_got_int;
};
static void
nt35399_request_vsync(struct msm_panel_data *panel_data,
struct msmfb_callback *callback)
{
struct panel_info *panel = container_of(panel_data, struct panel_info,
panel_data);
struct msm_mddi_client_data *client_data = panel->client_data;
panel->fb_callback = callback;
if (panel->nt35399_got_int) {
panel->nt35399_got_int = 0;
client_data->activate_link(client_data); /* clears interrupt */
}
}
static void nt35399_wait_vsync(struct msm_panel_data *panel_data)
{
struct panel_info *panel = container_of(panel_data, struct panel_info,
panel_data);
struct msm_mddi_client_data *client_data = panel->client_data;
if (panel->nt35399_got_int) {
panel->nt35399_got_int = 0;
client_data->activate_link(client_data); /* clears interrupt */
}
if (wait_event_timeout(nt35399_vsync_wait, panel->nt35399_got_int,
HZ/2) == 0)
printk(KERN_ERR "timeout waiting for VSYNC\n");
panel->nt35399_got_int = 0;
/* interrupt clears when screen dma starts */
}
static int nt35399_suspend(struct msm_panel_data *panel_data)
{
struct panel_info *panel = container_of(panel_data, struct panel_info,
panel_data);
struct msm_mddi_client_data *client_data = panel->client_data;
struct msm_mddi_bridge_platform_data *bridge_data =
client_data->private_client_data;
int ret;
ret = bridge_data->uninit(bridge_data, client_data);
if (ret) {
printk(KERN_INFO "mddi nt35399 client: non zero return from "
"uninit\n");
return ret;
}
client_data->suspend(client_data);
return 0;
}
static int nt35399_resume(struct msm_panel_data *panel_data)
{
struct panel_info *panel = container_of(panel_data, struct panel_info,
panel_data);
struct msm_mddi_client_data *client_data = panel->client_data;
struct msm_mddi_bridge_platform_data *bridge_data =
client_data->private_client_data;
int ret;
client_data->resume(client_data);
ret = bridge_data->init(bridge_data, client_data);
if (ret)
return ret;
return 0;
}
static int nt35399_blank(struct msm_panel_data *panel_data)
{
struct panel_info *panel = container_of(panel_data, struct panel_info,
panel_data);
struct msm_mddi_client_data *client_data = panel->client_data;
struct msm_mddi_bridge_platform_data *bridge_data =
client_data->private_client_data;
return bridge_data->blank(bridge_data, client_data);
}
static int nt35399_unblank(struct msm_panel_data *panel_data)
{
struct panel_info *panel = container_of(panel_data, struct panel_info,
panel_data);
struct msm_mddi_client_data *client_data = panel->client_data;
struct msm_mddi_bridge_platform_data *bridge_data =
client_data->private_client_data;
return bridge_data->unblank(bridge_data, client_data);
}
irqreturn_t nt35399_vsync_interrupt(int irq, void *data)
{
struct panel_info *panel = data;
panel->nt35399_got_int = 1;
if (panel->fb_callback) {
panel->fb_callback->func(panel->fb_callback);
panel->fb_callback = NULL;
}
wake_up(&nt35399_vsync_wait);
return IRQ_HANDLED;
}
static int setup_vsync(struct panel_info *panel, int init)
{
int ret;
int gpio = 97;
unsigned int irq;
if (!init) {
ret = 0;
goto uninit;
}
ret = gpio_request(gpio, "vsync");
if (ret)
goto err_request_gpio_failed;
ret = gpio_direction_input(gpio);
if (ret)
goto err_gpio_direction_input_failed;
ret = irq = gpio_to_irq(gpio);
if (ret < 0)
goto err_get_irq_num_failed;
ret = request_irq(irq, nt35399_vsync_interrupt, IRQF_TRIGGER_RISING,
"vsync", panel);
if (ret)
goto err_request_irq_failed;
printk(KERN_INFO "vsync on gpio %d now %d\n",
gpio, gpio_get_value(gpio));
return 0;
uninit:
free_irq(gpio_to_irq(gpio), panel->client_data);
err_request_irq_failed:
err_get_irq_num_failed:
err_gpio_direction_input_failed:
gpio_free(gpio);
err_request_gpio_failed:
return ret;
}
static int mddi_nt35399_probe(struct platform_device *pdev)
{
struct msm_mddi_client_data *client_data = pdev->dev.platform_data;
struct msm_mddi_bridge_platform_data *bridge_data =
client_data->private_client_data;
int ret;
struct panel_info *panel = kzalloc(sizeof(struct panel_info),
GFP_KERNEL);
printk(KERN_DEBUG "%s: enter.\n", __func__);
if (!panel)
return -ENOMEM;
platform_set_drvdata(pdev, panel);
ret = setup_vsync(panel, 1);
if (ret) {
dev_err(&pdev->dev, "mddi_nt35399_setup_vsync failed\n");
return ret;
}
panel->client_data = client_data;
panel->panel_data.suspend = nt35399_suspend;
panel->panel_data.resume = nt35399_resume;
panel->panel_data.wait_vsync = nt35399_wait_vsync;
panel->panel_data.request_vsync = nt35399_request_vsync;
panel->panel_data.blank = nt35399_blank;
panel->panel_data.unblank = nt35399_unblank;
panel->panel_data.fb_data = &bridge_data->fb_data;
panel->panel_data.caps = 0;
panel->pdev.name = "msm_panel";
panel->pdev.id = pdev->id;
panel->pdev.resource = client_data->fb_resource;
panel->pdev.num_resources = 1;
panel->pdev.dev.platform_data = &panel->panel_data;
if (bridge_data->init)
bridge_data->init(bridge_data, client_data);
platform_device_register(&panel->pdev);
return 0;
}
static int mddi_nt35399_remove(struct platform_device *pdev)
{
struct panel_info *panel = platform_get_drvdata(pdev);
setup_vsync(panel, 0);
kfree(panel);
return 0;
}
static struct platform_driver mddi_client_0bda_8a47 = {
.probe = mddi_nt35399_probe,
.remove = mddi_nt35399_remove,
.driver = { .name = "mddi_c_0bda_8a47" },
};
static int __init mddi_client_nt35399_init(void)
{
return platform_driver_register(&mddi_client_0bda_8a47);
}
module_init(mddi_client_nt35399_init);

283
drivers/video/msm/mddi_client_toshiba.c Normal file
View File

@@ -0,0 +1,283 @@
/* drivers/video/msm_fb/mddi_client_toshiba.c
*
* Support for Toshiba TC358720XBG mddi client devices which require no
* special initialization code.
*
* Copyright (C) 2007 Google Incorporated
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/gpio.h>
#include <mach/msm_fb.h>
#define LCD_CONTROL_BLOCK_BASE 0x110000
#define CMN (LCD_CONTROL_BLOCK_BASE|0x10)
#define INTFLG (LCD_CONTROL_BLOCK_BASE|0x18)
#define HCYCLE (LCD_CONTROL_BLOCK_BASE|0x34)
#define HDE_START (LCD_CONTROL_BLOCK_BASE|0x3C)
#define VPOS (LCD_CONTROL_BLOCK_BASE|0xC0)
#define MPLFBUF (LCD_CONTROL_BLOCK_BASE|0x20)
#define WAKEUP (LCD_CONTROL_BLOCK_BASE|0x54)
#define WSYN_DLY (LCD_CONTROL_BLOCK_BASE|0x58)
#define REGENB (LCD_CONTROL_BLOCK_BASE|0x5C)
#define BASE5 0x150000
#define BASE6 0x160000
#define BASE7 0x170000
#define GPIOIEV (BASE5 + 0x10)
#define GPIOIE (BASE5 + 0x14)
#define GPIORIS (BASE5 + 0x18)
#define GPIOMIS (BASE5 + 0x1C)
#define GPIOIC (BASE5 + 0x20)
#define INTMASK (BASE6 + 0x0C)
#define INTMASK_VWAKEOUT (1U << 0)
#define INTMASK_VWAKEOUT_ACTIVE_LOW (1U << 8)
#define GPIOSEL (BASE7 + 0x00)
#define GPIOSEL_VWAKEINT (1U << 0)
static DECLARE_WAIT_QUEUE_HEAD(toshiba_vsync_wait);
struct panel_info {
struct msm_mddi_client_data *client_data;
struct platform_device pdev;
struct msm_panel_data panel_data;
struct msmfb_callback *toshiba_callback;
int toshiba_got_int;
};
static void toshiba_request_vsync(struct msm_panel_data *panel_data,
struct msmfb_callback *callback)
{
struct panel_info *panel = container_of(panel_data, struct panel_info,
panel_data);
struct msm_mddi_client_data *client_data = panel->client_data;
panel->toshiba_callback = callback;
if (panel->toshiba_got_int) {
panel->toshiba_got_int = 0;
client_data->activate_link(client_data);
}
}
static void toshiba_clear_vsync(struct msm_panel_data *panel_data)
{
struct panel_info *panel = container_of(panel_data, struct panel_info,
panel_data);
struct msm_mddi_client_data *client_data = panel->client_data;
client_data->activate_link(client_data);
}
static void toshiba_wait_vsync(struct msm_panel_data *panel_data)
{
struct panel_info *panel = container_of(panel_data, struct panel_info,
panel_data);
struct msm_mddi_client_data *client_data = panel->client_data;
if (panel->toshiba_got_int) {
panel->toshiba_got_int = 0;
client_data->activate_link(client_data); /* clears interrupt */
}
if (wait_event_timeout(toshiba_vsync_wait, panel->toshiba_got_int,
HZ/2) == 0)
printk(KERN_ERR "timeout waiting for VSYNC\n");
panel->toshiba_got_int = 0;
/* interrupt clears when screen dma starts */
}
static int toshiba_suspend(struct msm_panel_data *panel_data)
{
struct panel_info *panel = container_of(panel_data, struct panel_info,
panel_data);
struct msm_mddi_client_data *client_data = panel->client_data;
struct msm_mddi_bridge_platform_data *bridge_data =
client_data->private_client_data;
int ret;
ret = bridge_data->uninit(bridge_data, client_data);
if (ret) {
printk(KERN_INFO "mddi toshiba client: non zero return from "
"uninit\n");
return ret;
}
client_data->suspend(client_data);
return 0;
}
static int toshiba_resume(struct msm_panel_data *panel_data)
{
struct panel_info *panel = container_of(panel_data, struct panel_info,
panel_data);
struct msm_mddi_client_data *client_data = panel->client_data;
struct msm_mddi_bridge_platform_data *bridge_data =
client_data->private_client_data;
int ret;
client_data->resume(client_data);
ret = bridge_data->init(bridge_data, client_data);
if (ret)
return ret;
return 0;
}
static int toshiba_blank(struct msm_panel_data *panel_data)
{
struct panel_info *panel = container_of(panel_data, struct panel_info,
panel_data);
struct msm_mddi_client_data *client_data = panel->client_data;
struct msm_mddi_bridge_platform_data *bridge_data =
client_data->private_client_data;
return bridge_data->blank(bridge_data, client_data);
}
static int toshiba_unblank(struct msm_panel_data *panel_data)
{
struct panel_info *panel = container_of(panel_data, struct panel_info,
panel_data);
struct msm_mddi_client_data *client_data = panel->client_data;
struct msm_mddi_bridge_platform_data *bridge_data =
client_data->private_client_data;
return bridge_data->unblank(bridge_data, client_data);
}
irqreturn_t toshiba_vsync_interrupt(int irq, void *data)
{
struct panel_info *panel = data;
panel->toshiba_got_int = 1;
if (panel->toshiba_callback) {
panel->toshiba_callback->func(panel->toshiba_callback);
panel->toshiba_callback = 0;
}
wake_up(&toshiba_vsync_wait);
return IRQ_HANDLED;
}
static int setup_vsync(struct panel_info *panel,
int init)
{
int ret;
int gpio = 97;
unsigned int irq;
if (!init) {
ret = 0;
goto uninit;
}
ret = gpio_request(gpio, "vsync");
if (ret)
goto err_request_gpio_failed;
ret = gpio_direction_input(gpio);
if (ret)
goto err_gpio_direction_input_failed;
ret = irq = gpio_to_irq(gpio);
if (ret < 0)
goto err_get_irq_num_failed;
ret = request_irq(irq, toshiba_vsync_interrupt, IRQF_TRIGGER_RISING,
"vsync", panel);
if (ret)
goto err_request_irq_failed;
printk(KERN_INFO "vsync on gpio %d now %d\n",
gpio, gpio_get_value(gpio));
return 0;
uninit:
free_irq(gpio_to_irq(gpio), panel);
err_request_irq_failed:
err_get_irq_num_failed:
err_gpio_direction_input_failed:
gpio_free(gpio);
err_request_gpio_failed:
return ret;
}
static int mddi_toshiba_probe(struct platform_device *pdev)
{
int ret;
struct msm_mddi_client_data *client_data = pdev->dev.platform_data;
struct msm_mddi_bridge_platform_data *bridge_data =
client_data->private_client_data;
struct panel_info *panel =
kzalloc(sizeof(struct panel_info), GFP_KERNEL);
if (!panel)
return -ENOMEM;
platform_set_drvdata(pdev, panel);
/* mddi_remote_write(mddi, 0, WAKEUP); */
client_data->remote_write(client_data, GPIOSEL_VWAKEINT, GPIOSEL);
client_data->remote_write(client_data, INTMASK_VWAKEOUT, INTMASK);
ret = setup_vsync(panel, 1);
if (ret) {
dev_err(&pdev->dev, "mddi_bridge_setup_vsync failed\n");
return ret;
}
panel->client_data = client_data;
panel->panel_data.suspend = toshiba_suspend;
panel->panel_data.resume = toshiba_resume;
panel->panel_data.wait_vsync = toshiba_wait_vsync;
panel->panel_data.request_vsync = toshiba_request_vsync;
panel->panel_data.clear_vsync = toshiba_clear_vsync;
panel->panel_data.blank = toshiba_blank;
panel->panel_data.unblank = toshiba_unblank;
panel->panel_data.fb_data = &bridge_data->fb_data;
panel->panel_data.caps = MSMFB_CAP_PARTIAL_UPDATES;
panel->pdev.name = "msm_panel";
panel->pdev.id = pdev->id;
panel->pdev.resource = client_data->fb_resource;
panel->pdev.num_resources = 1;
panel->pdev.dev.platform_data = &panel->panel_data;
bridge_data->init(bridge_data, client_data);
platform_device_register(&panel->pdev);
return 0;
}
static int mddi_toshiba_remove(struct platform_device *pdev)
{
struct panel_info *panel = platform_get_drvdata(pdev);
setup_vsync(panel, 0);
kfree(panel);
return 0;
}
static struct platform_driver mddi_client_d263_0000 = {
.probe = mddi_toshiba_probe,
.remove = mddi_toshiba_remove,
.driver = { .name = "mddi_c_d263_0000" },
};
static int __init mddi_client_toshiba_init(void)
{
platform_driver_register(&mddi_client_d263_0000);
return 0;
}
module_init(mddi_client_toshiba_init);

305
drivers/video/msm/mddi_hw.h Normal file
View File

@@ -0,0 +1,305 @@
/* drivers/video/msm_fb/mddi_hw.h
*
* MSM MDDI Hardware Registers and Structures
*
* Copyright (C) 2007 QUALCOMM Incorporated
* Copyright (C) 2007 Google Incorporated
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _MDDI_HW_H_
#define _MDDI_HW_H_
#include <linux/types.h>
#define MDDI_CMD 0x0000
#define MDDI_VERSION 0x0004
#define MDDI_PRI_PTR 0x0008
#define MDDI_SEC_PTR 0x000c
#define MDDI_BPS 0x0010
#define MDDI_SPM 0x0014
#define MDDI_INT 0x0018
#define MDDI_INTEN 0x001c
#define MDDI_REV_PTR 0x0020
#define MDDI_REV_SIZE 0x0024
#define MDDI_STAT 0x0028
#define MDDI_REV_RATE_DIV 0x002c
#define MDDI_REV_CRC_ERR 0x0030
#define MDDI_TA1_LEN 0x0034
#define MDDI_TA2_LEN 0x0038
#define MDDI_TEST_BUS 0x003c
#define MDDI_TEST 0x0040
#define MDDI_REV_PKT_CNT 0x0044
#define MDDI_DRIVE_HI 0x0048
#define MDDI_DRIVE_LO 0x004c
#define MDDI_DISP_WAKE 0x0050
#define MDDI_REV_ENCAP_SZ 0x0054
#define MDDI_RTD_VAL 0x0058
#define MDDI_PAD_CTL 0x0068
#define MDDI_DRIVER_START_CNT 0x006c
#define MDDI_NEXT_PRI_PTR 0x0070
#define MDDI_NEXT_SEC_PTR 0x0074
#define MDDI_MISR_CTL 0x0078
#define MDDI_MISR_DATA 0x007c
#define MDDI_SF_CNT 0x0080
#define MDDI_MF_CNT 0x0084
#define MDDI_CURR_REV_PTR 0x0088
#define MDDI_CORE_VER 0x008c
#define MDDI_INT_PRI_PTR_READ 0x0001
#define MDDI_INT_SEC_PTR_READ 0x0002
#define MDDI_INT_REV_DATA_AVAIL 0x0004
#define MDDI_INT_DISP_REQ 0x0008
#define MDDI_INT_PRI_UNDERFLOW 0x0010
#define MDDI_INT_SEC_UNDERFLOW 0x0020
#define MDDI_INT_REV_OVERFLOW 0x0040
#define MDDI_INT_CRC_ERROR 0x0080
#define MDDI_INT_MDDI_IN 0x0100
#define MDDI_INT_PRI_OVERWRITE 0x0200
#define MDDI_INT_SEC_OVERWRITE 0x0400
#define MDDI_INT_REV_OVERWRITE 0x0800
#define MDDI_INT_DMA_FAILURE 0x1000
#define MDDI_INT_LINK_ACTIVE 0x2000
#define MDDI_INT_IN_HIBERNATION 0x4000
#define MDDI_INT_PRI_LINK_LIST_DONE 0x8000
#define MDDI_INT_SEC_LINK_LIST_DONE 0x10000
#define MDDI_INT_NO_CMD_PKTS_PEND 0x20000
#define MDDI_INT_RTD_FAILURE 0x40000
#define MDDI_INT_REV_PKT_RECEIVED 0x80000
#define MDDI_INT_REV_PKTS_AVAIL 0x100000
#define MDDI_INT_NEED_CLEAR ( \
MDDI_INT_REV_DATA_AVAIL | \
MDDI_INT_PRI_UNDERFLOW | \
MDDI_INT_SEC_UNDERFLOW | \
MDDI_INT_REV_OVERFLOW | \
MDDI_INT_CRC_ERROR | \
MDDI_INT_REV_PKT_RECEIVED)
#define MDDI_STAT_LINK_ACTIVE 0x0001
#define MDDI_STAT_NEW_REV_PTR 0x0002
#define MDDI_STAT_NEW_PRI_PTR 0x0004
#define MDDI_STAT_NEW_SEC_PTR 0x0008
#define MDDI_STAT_IN_HIBERNATION 0x0010
#define MDDI_STAT_PRI_LINK_LIST_DONE 0x0020
#define MDDI_STAT_SEC_LINK_LIST_DONE 0x0040
#define MDDI_STAT_PENDING_TIMING_PKT 0x0080
#define MDDI_STAT_PENDING_REV_ENCAP 0x0100
#define MDDI_STAT_PENDING_POWERDOWN 0x0200
#define MDDI_STAT_RTD_MEAS_FAIL 0x0800
#define MDDI_STAT_CLIENT_WAKEUP_REQ 0x1000
#define MDDI_CMD_POWERDOWN 0x0100
#define MDDI_CMD_POWERUP 0x0200
#define MDDI_CMD_HIBERNATE 0x0300
#define MDDI_CMD_RESET 0x0400
#define MDDI_CMD_DISP_IGNORE 0x0501
#define MDDI_CMD_DISP_LISTEN 0x0500
#define MDDI_CMD_SEND_REV_ENCAP 0x0600
#define MDDI_CMD_GET_CLIENT_CAP 0x0601
#define MDDI_CMD_GET_CLIENT_STATUS 0x0602
#define MDDI_CMD_SEND_RTD 0x0700
#define MDDI_CMD_LINK_ACTIVE 0x0900
#define MDDI_CMD_PERIODIC_REV_ENCAP 0x0A00
#define MDDI_CMD_FORCE_NEW_REV_PTR 0x0C00
#define MDDI_VIDEO_REV_PKT_SIZE 0x40
#define MDDI_CLIENT_CAPABILITY_REV_PKT_SIZE 0x60
#define MDDI_MAX_REV_PKT_SIZE 0x60
/* #define MDDI_REV_BUFFER_SIZE 128 */
#define MDDI_REV_BUFFER_SIZE (MDDI_MAX_REV_PKT_SIZE * 4)
/* MDP sends 256 pixel packets, so lower value hibernates more without
* significantly increasing latency of waiting for next subframe */
#define MDDI_HOST_BYTES_PER_SUBFRAME 0x3C00
#define MDDI_HOST_TA2_LEN 0x000c
#define MDDI_HOST_REV_RATE_DIV 0x0002
struct __attribute__((packed)) mddi_rev_packet {
uint16_t length;
uint16_t type;
uint16_t client_id;
};
struct __attribute__((packed)) mddi_client_status {
uint16_t length;
uint16_t type;
uint16_t client_id;
uint16_t reverse_link_request; /* bytes needed in rev encap message */
uint8_t crc_error_count;
uint8_t capability_change;
uint16_t graphics_busy_flags;
uint16_t crc16;
};
struct __attribute__((packed)) mddi_client_caps {
uint16_t length; /* length, exclusive of this field */
uint16_t type; /* 66 */
uint16_t client_id;
uint16_t Protocol_Version;
uint16_t Minimum_Protocol_Version;
uint16_t Data_Rate_Capability;
uint8_t Interface_Type_Capability;
uint8_t Number_of_Alt_Displays;
uint16_t PostCal_Data_Rate;
uint16_t Bitmap_Width;
uint16_t Bitmap_Height;
uint16_t Display_Window_Width;
uint16_t Display_Window_Height;
uint32_t Color_Map_Size;
uint16_t Color_Map_RGB_Width;
uint16_t RGB_Capability;
uint8_t Monochrome_Capability;
uint8_t Reserved_1;
uint16_t Y_Cb_Cr_Capability;
uint16_t Bayer_Capability;
uint16_t Alpha_Cursor_Image_Planes;
uint32_t Client_Feature_Capability_Indicators;
uint8_t Maximum_Video_Frame_Rate_Capability;
uint8_t Minimum_Video_Frame_Rate_Capability;
uint16_t Minimum_Sub_frame_Rate;
uint16_t Audio_Buffer_Depth;
uint16_t Audio_Channel_Capability;
uint16_t Audio_Sample_Rate_Capability;
uint8_t Audio_Sample_Resolution;
uint8_t Mic_Audio_Sample_Resolution;
uint16_t Mic_Sample_Rate_Capability;
uint8_t Keyboard_Data_Format;
uint8_t pointing_device_data_format;
uint16_t content_protection_type;
uint16_t Mfr_Name;
uint16_t Product_Code;
uint16_t Reserved_3;
uint32_t Serial_Number;
uint8_t Week_of_Manufacture;
uint8_t Year_of_Manufacture;
uint16_t crc16;
} mddi_client_capability_type;
struct __attribute__((packed)) mddi_video_stream {
uint16_t length;
uint16_t type; /* 16 */
uint16_t client_id; /* 0 */
uint16_t video_data_format_descriptor;
/* format of each pixel in the Pixel Data in the present stream in the
* present packet.
* If bits [15:13] = 000 monochrome
* If bits [15:13] = 001 color pixels (palette).
* If bits [15:13] = 010 color pixels in raw RGB
* If bits [15:13] = 011 data in 4:2:2 Y Cb Cr format
* If bits [15:13] = 100 Bayer pixels
*/
uint16_t pixel_data_attributes;
/* interpreted as follows:
* Bits [1:0] = 11 pixel data is displayed to both eyes
* Bits [1:0] = 10 pixel data is routed to the left eye only.
* Bits [1:0] = 01 pixel data is routed to the right eye only.
* Bits [1:0] = 00 pixel data is routed to the alternate display.
* Bit 2 is 0 Pixel Data is in the standard progressive format.
* Bit 2 is 1 Pixel Data is in interlace format.
* Bit 3 is 0 Pixel Data is in the standard progressive format.
* Bit 3 is 1 Pixel Data is in alternate pixel format.
* Bit 4 is 0 Pixel Data is to or from the display frame buffer.
* Bit 4 is 1 Pixel Data is to or from the camera.
* Bit 5 is 0 pixel data contains the next consecutive row of pixels.
* Bit 5 is 1 X Left Edge, Y Top Edge, X Right Edge, Y Bottom Edge,
* X Start, and Y Start parameters are not defined and
* shall be ignored by the client.
* Bits [7:6] = 01 Pixel data is written to the offline image buffer.
* Bits [7:6] = 00 Pixel data is written to the buffer to refresh display.
* Bits [7:6] = 11 Pixel data is written to all image buffers.
* Bits [7:6] = 10 Invalid. Reserved for future use.
* Bits 8 through 11 alternate display number.
* Bits 12 through 14 are reserved for future use and shall be set to zero.
* Bit 15 is 1 the row of pixels is the last row of pixels in a frame.
*/
uint16_t x_left_edge;
uint16_t y_top_edge;
/* X,Y coordinate of the top left edge of the screen window */
uint16_t x_right_edge;
uint16_t y_bottom_edge;
/* X,Y coordinate of the bottom right edge of the window being
* updated. */
uint16_t x_start;
uint16_t y_start;
/* (X Start, Y Start) is the first pixel in the Pixel Data field
* below. */
uint16_t pixel_count;
/* number of pixels in the Pixel Data field below. */
uint16_t parameter_CRC;
/* 16-bit CRC of all bytes from the Packet Length to the Pixel Count. */
uint16_t reserved;
/* 16-bit variable to make structure align on 4 byte boundary */
};
#define TYPE_VIDEO_STREAM 16
#define TYPE_CLIENT_CAPS 66
#define TYPE_REGISTER_ACCESS 146
#define TYPE_CLIENT_STATUS 70
struct __attribute__((packed)) mddi_register_access {
uint16_t length;
uint16_t type; /* 146 */
uint16_t client_id;
uint16_t read_write_info;
/* Bits 13:0 a 14-bit unsigned integer that specifies the number of
* 32-bit Register Data List items to be transferred in the
* Register Data List field.
* Bits[15:14] = 00 Write to register(s);
* Bits[15:14] = 10 Read from register(s);
* Bits[15:14] = 11 Response to a Read.
* Bits[15:14] = 01 this value is reserved for future use. */
#define MDDI_WRITE (0 << 14)
#define MDDI_READ (2 << 14)
#define MDDI_READ_RESP (3 << 14)
uint32_t register_address;
/* the register address that is to be written to or read from. */
uint16_t crc16;
uint32_t register_data_list;
/* list of 4-byte register data values for/from client registers */
};
struct __attribute__((packed)) mddi_llentry {
uint16_t flags;
uint16_t header_count;
uint16_t data_count;
dma_addr_t data; /* 32 bit */
struct mddi_llentry *next;
uint16_t reserved;
union {
struct mddi_video_stream v;
struct mddi_register_access r;
uint32_t _[12];
} u;
};
#endif

538
drivers/video/msm/mdp.c Normal file
View File

@@ -0,0 +1,538 @@
/* drivers/video/msm_fb/mdp.c
*
* MSM MDP Interface (used by framebuffer core)
*
* Copyright (C) 2007 QUALCOMM Incorporated
* Copyright (C) 2007 Google Incorporated
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/kernel.h>
#include <linux/fb.h>
#include <linux/msm_mdp.h>
#include <linux/interrupt.h>
#include <linux/wait.h>
#include <linux/clk.h>
#include <linux/file.h>
#ifdef CONFIG_ANDROID_PMEM
#include <linux/android_pmem.h>
#endif
#include <linux/major.h>
#include <mach/msm_iomap.h>
#include <mach/msm_fb.h>
#include <linux/platform_device.h>
#include "mdp_hw.h"
struct class *mdp_class;
#define MDP_CMD_DEBUG_ACCESS_BASE (0x10000)
static uint16_t mdp_default_ccs[] = {
0x254, 0x000, 0x331, 0x254, 0xF38, 0xE61, 0x254, 0x409, 0x000,
0x010, 0x080, 0x080
};
static DECLARE_WAIT_QUEUE_HEAD(mdp_dma2_waitqueue);
static DECLARE_WAIT_QUEUE_HEAD(mdp_ppp_waitqueue);
static struct msmfb_callback *dma_callback;
static struct clk *clk;
static unsigned int mdp_irq_mask;
static DEFINE_SPINLOCK(mdp_lock);
DEFINE_MUTEX(mdp_mutex);
static int enable_mdp_irq(struct mdp_info *mdp, uint32_t mask)
{
unsigned long irq_flags;
int ret = 0;
BUG_ON(!mask);
spin_lock_irqsave(&mdp_lock, irq_flags);
/* if the mask bits are already set return an error, this interrupt
* is already enabled */
if (mdp_irq_mask & mask) {
printk(KERN_ERR "mdp irq already on already on %x %x\n",
mdp_irq_mask, mask);
ret = -1;
}
/* if the mdp irq is not already enabled enable it */
if (!mdp_irq_mask) {
if (clk)
clk_enable(clk);
enable_irq(mdp->irq);
}
/* update the irq mask to reflect the fact that the interrupt is
* enabled */
mdp_irq_mask |= mask;
spin_unlock_irqrestore(&mdp_lock, irq_flags);
return ret;
}
static int locked_disable_mdp_irq(struct mdp_info *mdp, uint32_t mask)
{
/* this interrupt is already disabled! */
if (!(mdp_irq_mask & mask)) {
printk(KERN_ERR "mdp irq already off %x %x\n",
mdp_irq_mask, mask);
return -1;
}
/* update the irq mask to reflect the fact that the interrupt is
* disabled */
mdp_irq_mask &= ~(mask);
/* if no one is waiting on the interrupt, disable it */
if (!mdp_irq_mask) {
disable_irq(mdp->irq);
if (clk)
clk_disable(clk);
}
return 0;
}
static int disable_mdp_irq(struct mdp_info *mdp, uint32_t mask)
{
unsigned long irq_flags;
int ret;
spin_lock_irqsave(&mdp_lock, irq_flags);
ret = locked_disable_mdp_irq(mdp, mask);
spin_unlock_irqrestore(&mdp_lock, irq_flags);
return ret;
}
static irqreturn_t mdp_isr(int irq, void *data)
{
uint32_t status;
unsigned long irq_flags;
struct mdp_info *mdp = data;
spin_lock_irqsave(&mdp_lock, irq_flags);
status = mdp_readl(mdp, MDP_INTR_STATUS);
mdp_writel(mdp, status, MDP_INTR_CLEAR);
status &= mdp_irq_mask;
if (status & DL0_DMA2_TERM_DONE) {
if (dma_callback) {
dma_callback->func(dma_callback);
dma_callback = NULL;
}
wake_up(&mdp_dma2_waitqueue);
}
if (status & DL0_ROI_DONE)
wake_up(&mdp_ppp_waitqueue);
if (status)
locked_disable_mdp_irq(mdp, status);
spin_unlock_irqrestore(&mdp_lock, irq_flags);
return IRQ_HANDLED;
}
static uint32_t mdp_check_mask(uint32_t mask)
{
uint32_t ret;
unsigned long irq_flags;
spin_lock_irqsave(&mdp_lock, irq_flags);
ret = mdp_irq_mask & mask;
spin_unlock_irqrestore(&mdp_lock, irq_flags);
return ret;
}
static int mdp_wait(struct mdp_info *mdp, uint32_t mask, wait_queue_head_t *wq)
{
int ret = 0;
unsigned long irq_flags;
wait_event_timeout(*wq, !mdp_check_mask(mask), HZ);
spin_lock_irqsave(&mdp_lock, irq_flags);
if (mdp_irq_mask & mask) {
locked_disable_mdp_irq(mdp, mask);
printk(KERN_WARNING "timeout waiting for mdp to complete %x\n",
mask);
ret = -ETIMEDOUT;
}
spin_unlock_irqrestore(&mdp_lock, irq_flags);
return ret;
}
void mdp_dma_wait(struct mdp_device *mdp_dev)
{
#define MDP_MAX_TIMEOUTS 20
static int timeout_count;
struct mdp_info *mdp = container_of(mdp_dev, struct mdp_info, mdp_dev);
if (mdp_wait(mdp, DL0_DMA2_TERM_DONE, &mdp_dma2_waitqueue) == -ETIMEDOUT)
timeout_count++;
else
timeout_count = 0;
if (timeout_count > MDP_MAX_TIMEOUTS) {
printk(KERN_ERR "mdp: dma failed %d times, somethings wrong!\n",
MDP_MAX_TIMEOUTS);
BUG();
}
}
static int mdp_ppp_wait(struct mdp_info *mdp)
{
return mdp_wait(mdp, DL0_ROI_DONE, &mdp_ppp_waitqueue);
}
void mdp_dma_to_mddi(struct mdp_info *mdp, uint32_t addr, uint32_t stride,
uint32_t width, uint32_t height, uint32_t x, uint32_t y,
struct msmfb_callback *callback)
{
uint32_t dma2_cfg;
uint16_t ld_param = 0; /* 0=PRIM, 1=SECD, 2=EXT */
if (enable_mdp_irq(mdp, DL0_DMA2_TERM_DONE)) {
printk(KERN_ERR "mdp_dma_to_mddi: busy\n");
return;
}
dma_callback = callback;
dma2_cfg = DMA_PACK_TIGHT |
DMA_PACK_ALIGN_LSB |
DMA_PACK_PATTERN_RGB |
DMA_OUT_SEL_AHB |
DMA_IBUF_NONCONTIGUOUS;
dma2_cfg |= DMA_IBUF_FORMAT_RGB565;
dma2_cfg |= DMA_OUT_SEL_MDDI;
dma2_cfg |= DMA_MDDI_DMAOUT_LCD_SEL_PRIMARY;
dma2_cfg |= DMA_DITHER_EN;
/* setup size, address, and stride */
mdp_writel(mdp, (height << 16) | (width),
MDP_CMD_DEBUG_ACCESS_BASE + 0x0184);
mdp_writel(mdp, addr, MDP_CMD_DEBUG_ACCESS_BASE + 0x0188);
mdp_writel(mdp, stride, MDP_CMD_DEBUG_ACCESS_BASE + 0x018C);
/* 666 18BPP */
dma2_cfg |= DMA_DSTC0G_6BITS | DMA_DSTC1B_6BITS | DMA_DSTC2R_6BITS;
/* set y & x offset and MDDI transaction parameters */
mdp_writel(mdp, (y << 16) | (x), MDP_CMD_DEBUG_ACCESS_BASE + 0x0194);
mdp_writel(mdp, ld_param, MDP_CMD_DEBUG_ACCESS_BASE + 0x01a0);
mdp_writel(mdp, (MDDI_VDO_PACKET_DESC << 16) | MDDI_VDO_PACKET_PRIM,
MDP_CMD_DEBUG_ACCESS_BASE + 0x01a4);
mdp_writel(mdp, dma2_cfg, MDP_CMD_DEBUG_ACCESS_BASE + 0x0180);
/* start DMA2 */
mdp_writel(mdp, 0, MDP_CMD_DEBUG_ACCESS_BASE + 0x0044);
}
void mdp_dma(struct mdp_device *mdp_dev, uint32_t addr, uint32_t stride,
uint32_t width, uint32_t height, uint32_t x, uint32_t y,
struct msmfb_callback *callback, int interface)
{
struct mdp_info *mdp = container_of(mdp_dev, struct mdp_info, mdp_dev);
if (interface == MSM_MDDI_PMDH_INTERFACE) {
mdp_dma_to_mddi(mdp, addr, stride, width, height, x, y,
callback);
}
}
int get_img(struct mdp_img *img, struct fb_info *info,
unsigned long *start, unsigned long *len,
struct file **filep)
{
int put_needed, ret = 0;
struct file *file;
unsigned long vstart;
#ifdef CONFIG_ANDROID_PMEM
if (!get_pmem_file(img->memory_id, start, &vstart, len, filep))
return 0;
#endif
file = fget_light(img->memory_id, &put_needed);
if (file == NULL)
return -1;
if (MAJOR(file->f_dentry->d_inode->i_rdev) == FB_MAJOR) {
*start = info->fix.smem_start;
*len = info->fix.smem_len;
} else
ret = -1;
fput_light(file, put_needed);
return ret;
}
void put_img(struct file *src_file, struct file *dst_file)
{
#ifdef CONFIG_ANDROID_PMEM
if (src_file)
put_pmem_file(src_file);
if (dst_file)
put_pmem_file(dst_file);
#endif
}
int mdp_blit(struct mdp_device *mdp_dev, struct fb_info *fb,
struct mdp_blit_req *req)
{
int ret;
unsigned long src_start = 0, src_len = 0, dst_start = 0, dst_len = 0;
struct mdp_info *mdp = container_of(mdp_dev, struct mdp_info, mdp_dev);
struct file *src_file = 0, *dst_file = 0;
/* WORKAROUND FOR HARDWARE BUG IN BG TILE FETCH */
if (unlikely(req->src_rect.h == 0 ||
req->src_rect.w == 0)) {
printk(KERN_ERR "mpd_ppp: src img of zero size!\n");
return -EINVAL;
}
if (unlikely(req->dst_rect.h == 0 ||
req->dst_rect.w == 0))
return -EINVAL;
/* do this first so that if this fails, the caller can always
* safely call put_img */
if (unlikely(get_img(&req->src, fb, &src_start, &src_len, &src_file))) {
printk(KERN_ERR "mpd_ppp: could not retrieve src image from "
"memory\n");
return -EINVAL;
}
if (unlikely(get_img(&req->dst, fb, &dst_start, &dst_len, &dst_file))) {
printk(KERN_ERR "mpd_ppp: could not retrieve dst image from "
"memory\n");
#ifdef CONFIG_ANDROID_PMEM
put_pmem_file(src_file);
#endif
return -EINVAL;
}
mutex_lock(&mdp_mutex);
/* transp_masking unimplemented */
req->transp_mask = MDP_TRANSP_NOP;
if (unlikely((req->transp_mask != MDP_TRANSP_NOP ||
req->alpha != MDP_ALPHA_NOP ||
HAS_ALPHA(req->src.format)) &&
(req->flags & MDP_ROT_90 &&
req->dst_rect.w <= 16 && req->dst_rect.h >= 16))) {
int i;
unsigned int tiles = req->dst_rect.h / 16;
unsigned int remainder = req->dst_rect.h % 16;
req->src_rect.w = 16*req->src_rect.w / req->dst_rect.h;
req->dst_rect.h = 16;
for (i = 0; i < tiles; i++) {
enable_mdp_irq(mdp, DL0_ROI_DONE);
ret = mdp_ppp_blit(mdp, req, src_file, src_start,
src_len, dst_file, dst_start,
dst_len);
if (ret)
goto err_bad_blit;
ret = mdp_ppp_wait(mdp);
if (ret)
goto err_wait_failed;
req->dst_rect.y += 16;
req->src_rect.x += req->src_rect.w;
}
if (!remainder)
goto end;
req->src_rect.w = remainder*req->src_rect.w / req->dst_rect.h;
req->dst_rect.h = remainder;
}
enable_mdp_irq(mdp, DL0_ROI_DONE);
ret = mdp_ppp_blit(mdp, req, src_file, src_start, src_len, dst_file,
dst_start,
dst_len);
if (ret)
goto err_bad_blit;
ret = mdp_ppp_wait(mdp);
if (ret)
goto err_wait_failed;
end:
put_img(src_file, dst_file);
mutex_unlock(&mdp_mutex);
return 0;
err_bad_blit:
disable_mdp_irq(mdp, DL0_ROI_DONE);
err_wait_failed:
put_img(src_file, dst_file);
mutex_unlock(&mdp_mutex);
return ret;
}
void mdp_set_grp_disp(struct mdp_device *mdp_dev, unsigned disp_id)
{
struct mdp_info *mdp = container_of(mdp_dev, struct mdp_info, mdp_dev);
disp_id &= 0xf;
mdp_writel(mdp, disp_id, MDP_FULL_BYPASS_WORD43);
}
int register_mdp_client(struct class_interface *cint)
{
if (!mdp_class) {
pr_err("mdp: no mdp_class when registering mdp client\n");
return -ENODEV;
}
cint->class = mdp_class;
return class_interface_register(cint);
}
#include "mdp_csc_table.h"
#include "mdp_scale_tables.h"
int mdp_probe(struct platform_device *pdev)
{
struct resource *resource;
int ret;
int n;
struct mdp_info *mdp;
resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!resource) {
pr_err("mdp: can not get mdp mem resource!\n");
return -ENOMEM;
}
mdp = kzalloc(sizeof(struct mdp_info), GFP_KERNEL);
if (!mdp)
return -ENOMEM;
mdp->irq = platform_get_irq(pdev, 0);
if (mdp->irq < 0) {
pr_err("mdp: can not get mdp irq\n");
ret = mdp->irq;
goto error_get_irq;
}
mdp->base = ioremap(resource->start,
resource->end - resource->start);
if (mdp->base == 0) {
printk(KERN_ERR "msmfb: cannot allocate mdp regs!\n");
ret = -ENOMEM;
goto error_ioremap;
}
mdp->mdp_dev.dma = mdp_dma;
mdp->mdp_dev.dma_wait = mdp_dma_wait;
mdp->mdp_dev.blit = mdp_blit;
mdp->mdp_dev.set_grp_disp = mdp_set_grp_disp;
clk = clk_get(&pdev->dev, "mdp_clk");
if (IS_ERR(clk)) {
printk(KERN_INFO "mdp: failed to get mdp clk");
return PTR_ERR(clk);
}
ret = request_irq(mdp->irq, mdp_isr, IRQF_DISABLED, "msm_mdp", mdp);
if (ret)
goto error_request_irq;
disable_irq(mdp->irq);
mdp_irq_mask = 0;
/* debug interface write access */
mdp_writel(mdp, 1, 0x60);
mdp_writel(mdp, MDP_ANY_INTR_MASK, MDP_INTR_ENABLE);
mdp_writel(mdp, 1, MDP_EBI2_PORTMAP_MODE);
mdp_writel(mdp, 0, MDP_CMD_DEBUG_ACCESS_BASE + 0x01f8);
mdp_writel(mdp, 0, MDP_CMD_DEBUG_ACCESS_BASE + 0x01fc);
for (n = 0; n < ARRAY_SIZE(csc_table); n++)
mdp_writel(mdp, csc_table[n].val, csc_table[n].reg);
/* clear up unused fg/main registers */
/* comp.plane 2&3 ystride */
mdp_writel(mdp, 0, MDP_CMD_DEBUG_ACCESS_BASE + 0x0120);
/* unpacked pattern */
mdp_writel(mdp, 0, MDP_CMD_DEBUG_ACCESS_BASE + 0x012c);
mdp_writel(mdp, 0, MDP_CMD_DEBUG_ACCESS_BASE + 0x0130);
mdp_writel(mdp, 0, MDP_CMD_DEBUG_ACCESS_BASE + 0x0134);
mdp_writel(mdp, 0, MDP_CMD_DEBUG_ACCESS_BASE + 0x0158);
mdp_writel(mdp, 0, MDP_CMD_DEBUG_ACCESS_BASE + 0x015c);
mdp_writel(mdp, 0, MDP_CMD_DEBUG_ACCESS_BASE + 0x0160);
mdp_writel(mdp, 0, MDP_CMD_DEBUG_ACCESS_BASE + 0x0170);
mdp_writel(mdp, 0, MDP_CMD_DEBUG_ACCESS_BASE + 0x0174);
mdp_writel(mdp, 0, MDP_CMD_DEBUG_ACCESS_BASE + 0x017c);
/* comp.plane 2 & 3 */
mdp_writel(mdp, 0, MDP_CMD_DEBUG_ACCESS_BASE + 0x0114);
mdp_writel(mdp, 0, MDP_CMD_DEBUG_ACCESS_BASE + 0x0118);
/* clear unused bg registers */
mdp_writel(mdp, 0, MDP_CMD_DEBUG_ACCESS_BASE + 0x01c8);
mdp_writel(mdp, 0, MDP_CMD_DEBUG_ACCESS_BASE + 0x01d0);
mdp_writel(mdp, 0, MDP_CMD_DEBUG_ACCESS_BASE + 0x01dc);
mdp_writel(mdp, 0, MDP_CMD_DEBUG_ACCESS_BASE + 0x01e0);
mdp_writel(mdp, 0, MDP_CMD_DEBUG_ACCESS_BASE + 0x01e4);
for (n = 0; n < ARRAY_SIZE(mdp_upscale_table); n++)
mdp_writel(mdp, mdp_upscale_table[n].val,
mdp_upscale_table[n].reg);
for (n = 0; n < 9; n++)
mdp_writel(mdp, mdp_default_ccs[n], 0x40440 + 4 * n);
mdp_writel(mdp, mdp_default_ccs[9], 0x40500 + 4 * 0);
mdp_writel(mdp, mdp_default_ccs[10], 0x40500 + 4 * 0);
mdp_writel(mdp, mdp_default_ccs[11], 0x40500 + 4 * 0);
/* register mdp device */
mdp->mdp_dev.dev.parent = &pdev->dev;
mdp->mdp_dev.dev.class = mdp_class;
snprintf(mdp->mdp_dev.dev.bus_id, BUS_ID_SIZE, "mdp%d", pdev->id);
/* if you can remove the platform device you'd have to implement
* this:
mdp_dev.release = mdp_class; */
ret = device_register(&mdp->mdp_dev.dev);
if (ret)
goto error_device_register;
return 0;
error_device_register:
free_irq(mdp->irq, mdp);
error_request_irq:
iounmap(mdp->base);
error_get_irq:
error_ioremap:
kfree(mdp);
return ret;
}
static struct platform_driver msm_mdp_driver = {
.probe = mdp_probe,
.driver = {.name = "msm_mdp"},
};
static int __init mdp_init(void)
{
mdp_class = class_create(THIS_MODULE, "msm_mdp");
if (IS_ERR(mdp_class)) {
printk(KERN_ERR "Error creating mdp class\n");
return PTR_ERR(mdp_class);
}
return platform_driver_register(&msm_mdp_driver);
}
subsys_initcall(mdp_init);

582
drivers/video/msm/mdp_csc_table.h Normal file
View File

@@ -0,0 +1,582 @@
/* drivers/video/msm_fb/mdp_csc_table.h
*
* Copyright (C) 2007 QUALCOMM Incorporated
* Copyright (C) 2007 Google Incorporated
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
static struct {
uint32_t reg;
uint32_t val;
} csc_table[] = {
{ 0x40400, 0x83 },
{ 0x40404, 0x102 },
{ 0x40408, 0x32 },
{ 0x4040c, 0xffffffb5 },
{ 0x40410, 0xffffff6c },
{ 0x40414, 0xe1 },
{ 0x40418, 0xe1 },
{ 0x4041c, 0xffffff45 },
{ 0x40420, 0xffffffdc },
{ 0x40440, 0x254 },
{ 0x40444, 0x0 },
{ 0x40448, 0x331 },
{ 0x4044c, 0x254 },
{ 0x40450, 0xffffff38 },
{ 0x40454, 0xfffffe61 },
{ 0x40458, 0x254 },
{ 0x4045c, 0x409 },
{ 0x40460, 0x0 },
{ 0x40480, 0x5d },
{ 0x40484, 0x13a },
{ 0x40488, 0x20 },
{ 0x4048c, 0xffffffcd },
{ 0x40490, 0xffffff54 },
{ 0x40494, 0xe1 },
{ 0x40498, 0xe1 },
{ 0x4049c, 0xffffff35 },
{ 0x404a0, 0xffffffec },
{ 0x404c0, 0x254 },
{ 0x404c4, 0x0 },
{ 0x404c8, 0x396 },
{ 0x404cc, 0x254 },
{ 0x404d0, 0xffffff94 },
{ 0x404d4, 0xfffffef0 },
{ 0x404d8, 0x254 },
{ 0x404dc, 0x43a },
{ 0x404e0, 0x0 },
{ 0x40500, 0x10 },
{ 0x40504, 0x80 },
{ 0x40508, 0x80 },
{ 0x40540, 0x10 },
{ 0x40544, 0x80 },
{ 0x40548, 0x80 },
{ 0x40580, 0x10 },
{ 0x40584, 0xeb },
{ 0x40588, 0x10 },
{ 0x4058c, 0xf0 },
{ 0x405c0, 0x10 },
{ 0x405c4, 0xeb },
{ 0x405c8, 0x10 },
{ 0x405cc, 0xf0 },
{ 0x40800, 0x0 },
{ 0x40804, 0x151515 },
{ 0x40808, 0x1d1d1d },
{ 0x4080c, 0x232323 },
{ 0x40810, 0x272727 },
{ 0x40814, 0x2b2b2b },
{ 0x40818, 0x2f2f2f },
{ 0x4081c, 0x333333 },
{ 0x40820, 0x363636 },
{ 0x40824, 0x393939 },
{ 0x40828, 0x3b3b3b },
{ 0x4082c, 0x3e3e3e },
{ 0x40830, 0x404040 },
{ 0x40834, 0x434343 },
{ 0x40838, 0x454545 },
{ 0x4083c, 0x474747 },
{ 0x40840, 0x494949 },
{ 0x40844, 0x4b4b4b },
{ 0x40848, 0x4d4d4d },
{ 0x4084c, 0x4f4f4f },
{ 0x40850, 0x515151 },
{ 0x40854, 0x535353 },
{ 0x40858, 0x555555 },
{ 0x4085c, 0x565656 },
{ 0x40860, 0x585858 },
{ 0x40864, 0x5a5a5a },
{ 0x40868, 0x5b5b5b },
{ 0x4086c, 0x5d5d5d },
{ 0x40870, 0x5e5e5e },
{ 0x40874, 0x606060 },
{ 0x40878, 0x616161 },
{ 0x4087c, 0x636363 },
{ 0x40880, 0x646464 },
{ 0x40884, 0x666666 },
{ 0x40888, 0x676767 },
{ 0x4088c, 0x686868 },
{ 0x40890, 0x6a6a6a },
{ 0x40894, 0x6b6b6b },
{ 0x40898, 0x6c6c6c },
{ 0x4089c, 0x6e6e6e },
{ 0x408a0, 0x6f6f6f },
{ 0x408a4, 0x707070 },
{ 0x408a8, 0x717171 },
{ 0x408ac, 0x727272 },
{ 0x408b0, 0x747474 },
{ 0x408b4, 0x757575 },
{ 0x408b8, 0x767676 },
{ 0x408bc, 0x777777 },
{ 0x408c0, 0x787878 },
{ 0x408c4, 0x797979 },
{ 0x408c8, 0x7a7a7a },
{ 0x408cc, 0x7c7c7c },
{ 0x408d0, 0x7d7d7d },
{ 0x408d4, 0x7e7e7e },
{ 0x408d8, 0x7f7f7f },
{ 0x408dc, 0x808080 },
{ 0x408e0, 0x818181 },
{ 0x408e4, 0x828282 },
{ 0x408e8, 0x838383 },
{ 0x408ec, 0x848484 },
{ 0x408f0, 0x858585 },
{ 0x408f4, 0x868686 },
{ 0x408f8, 0x878787 },
{ 0x408fc, 0x888888 },
{ 0x40900, 0x898989 },
{ 0x40904, 0x8a8a8a },
{ 0x40908, 0x8b8b8b },
{ 0x4090c, 0x8c8c8c },
{ 0x40910, 0x8d8d8d },
{ 0x40914, 0x8e8e8e },
{ 0x40918, 0x8f8f8f },
{ 0x4091c, 0x8f8f8f },
{ 0x40920, 0x909090 },
{ 0x40924, 0x919191 },
{ 0x40928, 0x929292 },
{ 0x4092c, 0x939393 },
{ 0x40930, 0x949494 },
{ 0x40934, 0x959595 },
{ 0x40938, 0x969696 },
{ 0x4093c, 0x969696 },
{ 0x40940, 0x979797 },
{ 0x40944, 0x989898 },
{ 0x40948, 0x999999 },
{ 0x4094c, 0x9a9a9a },
{ 0x40950, 0x9b9b9b },
{ 0x40954, 0x9c9c9c },
{ 0x40958, 0x9c9c9c },
{ 0x4095c, 0x9d9d9d },
{ 0x40960, 0x9e9e9e },
{ 0x40964, 0x9f9f9f },
{ 0x40968, 0xa0a0a0 },
{ 0x4096c, 0xa0a0a0 },
{ 0x40970, 0xa1a1a1 },
{ 0x40974, 0xa2a2a2 },
{ 0x40978, 0xa3a3a3 },
{ 0x4097c, 0xa4a4a4 },
{ 0x40980, 0xa4a4a4 },
{ 0x40984, 0xa5a5a5 },
{ 0x40988, 0xa6a6a6 },
{ 0x4098c, 0xa7a7a7 },
{ 0x40990, 0xa7a7a7 },
{ 0x40994, 0xa8a8a8 },
{ 0x40998, 0xa9a9a9 },
{ 0x4099c, 0xaaaaaa },
{ 0x409a0, 0xaaaaaa },
{ 0x409a4, 0xababab },
{ 0x409a8, 0xacacac },
{ 0x409ac, 0xadadad },
{ 0x409b0, 0xadadad },
{ 0x409b4, 0xaeaeae },
{ 0x409b8, 0xafafaf },
{ 0x409bc, 0xafafaf },
{ 0x409c0, 0xb0b0b0 },
{ 0x409c4, 0xb1b1b1 },
{ 0x409c8, 0xb2b2b2 },
{ 0x409cc, 0xb2b2b2 },
{ 0x409d0, 0xb3b3b3 },
{ 0x409d4, 0xb4b4b4 },
{ 0x409d8, 0xb4b4b4 },
{ 0x409dc, 0xb5b5b5 },
{ 0x409e0, 0xb6b6b6 },
{ 0x409e4, 0xb6b6b6 },
{ 0x409e8, 0xb7b7b7 },
{ 0x409ec, 0xb8b8b8 },
{ 0x409f0, 0xb8b8b8 },
{ 0x409f4, 0xb9b9b9 },
{ 0x409f8, 0xbababa },
{ 0x409fc, 0xbababa },
{ 0x40a00, 0xbbbbbb },
{ 0x40a04, 0xbcbcbc },
{ 0x40a08, 0xbcbcbc },
{ 0x40a0c, 0xbdbdbd },
{ 0x40a10, 0xbebebe },
{ 0x40a14, 0xbebebe },
{ 0x40a18, 0xbfbfbf },
{ 0x40a1c, 0xc0c0c0 },
{ 0x40a20, 0xc0c0c0 },
{ 0x40a24, 0xc1c1c1 },
{ 0x40a28, 0xc1c1c1 },
{ 0x40a2c, 0xc2c2c2 },
{ 0x40a30, 0xc3c3c3 },
{ 0x40a34, 0xc3c3c3 },
{ 0x40a38, 0xc4c4c4 },
{ 0x40a3c, 0xc5c5c5 },
{ 0x40a40, 0xc5c5c5 },
{ 0x40a44, 0xc6c6c6 },
{ 0x40a48, 0xc6c6c6 },
{ 0x40a4c, 0xc7c7c7 },
{ 0x40a50, 0xc8c8c8 },
{ 0x40a54, 0xc8c8c8 },
{ 0x40a58, 0xc9c9c9 },
{ 0x40a5c, 0xc9c9c9 },
{ 0x40a60, 0xcacaca },
{ 0x40a64, 0xcbcbcb },
{ 0x40a68, 0xcbcbcb },
{ 0x40a6c, 0xcccccc },
{ 0x40a70, 0xcccccc },
{ 0x40a74, 0xcdcdcd },
{ 0x40a78, 0xcecece },
{ 0x40a7c, 0xcecece },
{ 0x40a80, 0xcfcfcf },
{ 0x40a84, 0xcfcfcf },
{ 0x40a88, 0xd0d0d0 },
{ 0x40a8c, 0xd0d0d0 },
{ 0x40a90, 0xd1d1d1 },
{ 0x40a94, 0xd2d2d2 },
{ 0x40a98, 0xd2d2d2 },
{ 0x40a9c, 0xd3d3d3 },
{ 0x40aa0, 0xd3d3d3 },
{ 0x40aa4, 0xd4d4d4 },
{ 0x40aa8, 0xd4d4d4 },
{ 0x40aac, 0xd5d5d5 },
{ 0x40ab0, 0xd6d6d6 },
{ 0x40ab4, 0xd6d6d6 },
{ 0x40ab8, 0xd7d7d7 },
{ 0x40abc, 0xd7d7d7 },
{ 0x40ac0, 0xd8d8d8 },
{ 0x40ac4, 0xd8d8d8 },
{ 0x40ac8, 0xd9d9d9 },
{ 0x40acc, 0xd9d9d9 },
{ 0x40ad0, 0xdadada },
{ 0x40ad4, 0xdbdbdb },
{ 0x40ad8, 0xdbdbdb },
{ 0x40adc, 0xdcdcdc },
{ 0x40ae0, 0xdcdcdc },
{ 0x40ae4, 0xdddddd },
{ 0x40ae8, 0xdddddd },
{ 0x40aec, 0xdedede },
{ 0x40af0, 0xdedede },
{ 0x40af4, 0xdfdfdf },
{ 0x40af8, 0xdfdfdf },
{ 0x40afc, 0xe0e0e0 },
{ 0x40b00, 0xe0e0e0 },
{ 0x40b04, 0xe1e1e1 },
{ 0x40b08, 0xe1e1e1 },
{ 0x40b0c, 0xe2e2e2 },
{ 0x40b10, 0xe3e3e3 },
{ 0x40b14, 0xe3e3e3 },
{ 0x40b18, 0xe4e4e4 },
{ 0x40b1c, 0xe4e4e4 },
{ 0x40b20, 0xe5e5e5 },
{ 0x40b24, 0xe5e5e5 },
{ 0x40b28, 0xe6e6e6 },
{ 0x40b2c, 0xe6e6e6 },
{ 0x40b30, 0xe7e7e7 },
{ 0x40b34, 0xe7e7e7 },
{ 0x40b38, 0xe8e8e8 },
{ 0x40b3c, 0xe8e8e8 },
{ 0x40b40, 0xe9e9e9 },
{ 0x40b44, 0xe9e9e9 },
{ 0x40b48, 0xeaeaea },
{ 0x40b4c, 0xeaeaea },
{ 0x40b50, 0xebebeb },
{ 0x40b54, 0xebebeb },
{ 0x40b58, 0xececec },
{ 0x40b5c, 0xececec },
{ 0x40b60, 0xededed },
{ 0x40b64, 0xededed },
{ 0x40b68, 0xeeeeee },
{ 0x40b6c, 0xeeeeee },
{ 0x40b70, 0xefefef },
{ 0x40b74, 0xefefef },
{ 0x40b78, 0xf0f0f0 },
{ 0x40b7c, 0xf0f0f0 },
{ 0x40b80, 0xf1f1f1 },
{ 0x40b84, 0xf1f1f1 },
{ 0x40b88, 0xf2f2f2 },
{ 0x40b8c, 0xf2f2f2 },
{ 0x40b90, 0xf2f2f2 },
{ 0x40b94, 0xf3f3f3 },
{ 0x40b98, 0xf3f3f3 },
{ 0x40b9c, 0xf4f4f4 },
{ 0x40ba0, 0xf4f4f4 },
{ 0x40ba4, 0xf5f5f5 },
{ 0x40ba8, 0xf5f5f5 },
{ 0x40bac, 0xf6f6f6 },
{ 0x40bb0, 0xf6f6f6 },
{ 0x40bb4, 0xf7f7f7 },
{ 0x40bb8, 0xf7f7f7 },
{ 0x40bbc, 0xf8f8f8 },
{ 0x40bc0, 0xf8f8f8 },
{ 0x40bc4, 0xf9f9f9 },
{ 0x40bc8, 0xf9f9f9 },
{ 0x40bcc, 0xfafafa },
{ 0x40bd0, 0xfafafa },
{ 0x40bd4, 0xfafafa },
{ 0x40bd8, 0xfbfbfb },
{ 0x40bdc, 0xfbfbfb },
{ 0x40be0, 0xfcfcfc },
{ 0x40be4, 0xfcfcfc },
{ 0x40be8, 0xfdfdfd },
{ 0x40bec, 0xfdfdfd },
{ 0x40bf0, 0xfefefe },
{ 0x40bf4, 0xfefefe },
{ 0x40bf8, 0xffffff },
{ 0x40bfc, 0xffffff },
{ 0x40c00, 0x0 },
{ 0x40c04, 0x0 },
{ 0x40c08, 0x0 },
{ 0x40c0c, 0x0 },
{ 0x40c10, 0x0 },
{ 0x40c14, 0x0 },
{ 0x40c18, 0x0 },
{ 0x40c1c, 0x0 },
{ 0x40c20, 0x0 },
{ 0x40c24, 0x0 },
{ 0x40c28, 0x0 },
{ 0x40c2c, 0x0 },
{ 0x40c30, 0x0 },
{ 0x40c34, 0x0 },
{ 0x40c38, 0x0 },
{ 0x40c3c, 0x0 },
{ 0x40c40, 0x10101 },
{ 0x40c44, 0x10101 },
{ 0x40c48, 0x10101 },
{ 0x40c4c, 0x10101 },
{ 0x40c50, 0x10101 },
{ 0x40c54, 0x10101 },
{ 0x40c58, 0x10101 },
{ 0x40c5c, 0x10101 },
{ 0x40c60, 0x10101 },
{ 0x40c64, 0x10101 },
{ 0x40c68, 0x20202 },
{ 0x40c6c, 0x20202 },
{ 0x40c70, 0x20202 },
{ 0x40c74, 0x20202 },
{ 0x40c78, 0x20202 },
{ 0x40c7c, 0x20202 },
{ 0x40c80, 0x30303 },
{ 0x40c84, 0x30303 },
{ 0x40c88, 0x30303 },
{ 0x40c8c, 0x30303 },
{ 0x40c90, 0x30303 },
{ 0x40c94, 0x40404 },
{ 0x40c98, 0x40404 },
{ 0x40c9c, 0x40404 },
{ 0x40ca0, 0x40404 },
{ 0x40ca4, 0x40404 },
{ 0x40ca8, 0x50505 },
{ 0x40cac, 0x50505 },
{ 0x40cb0, 0x50505 },
{ 0x40cb4, 0x50505 },
{ 0x40cb8, 0x60606 },
{ 0x40cbc, 0x60606 },
{ 0x40cc0, 0x60606 },
{ 0x40cc4, 0x70707 },
{ 0x40cc8, 0x70707 },
{ 0x40ccc, 0x70707 },
{ 0x40cd0, 0x70707 },
{ 0x40cd4, 0x80808 },
{ 0x40cd8, 0x80808 },
{ 0x40cdc, 0x80808 },
{ 0x40ce0, 0x90909 },
{ 0x40ce4, 0x90909 },
{ 0x40ce8, 0xa0a0a },
{ 0x40cec, 0xa0a0a },
{ 0x40cf0, 0xa0a0a },
{ 0x40cf4, 0xb0b0b },
{ 0x40cf8, 0xb0b0b },
{ 0x40cfc, 0xb0b0b },
{ 0x40d00, 0xc0c0c },
{ 0x40d04, 0xc0c0c },
{ 0x40d08, 0xd0d0d },
{ 0x40d0c, 0xd0d0d },
{ 0x40d10, 0xe0e0e },
{ 0x40d14, 0xe0e0e },
{ 0x40d18, 0xe0e0e },
{ 0x40d1c, 0xf0f0f },
{ 0x40d20, 0xf0f0f },
{ 0x40d24, 0x101010 },
{ 0x40d28, 0x101010 },
{ 0x40d2c, 0x111111 },
{ 0x40d30, 0x111111 },
{ 0x40d34, 0x121212 },
{ 0x40d38, 0x121212 },
{ 0x40d3c, 0x131313 },
{ 0x40d40, 0x131313 },
{ 0x40d44, 0x141414 },
{ 0x40d48, 0x151515 },
{ 0x40d4c, 0x151515 },
{ 0x40d50, 0x161616 },
{ 0x40d54, 0x161616 },
{ 0x40d58, 0x171717 },
{ 0x40d5c, 0x171717 },
{ 0x40d60, 0x181818 },
{ 0x40d64, 0x191919 },
{ 0x40d68, 0x191919 },
{ 0x40d6c, 0x1a1a1a },
{ 0x40d70, 0x1b1b1b },
{ 0x40d74, 0x1b1b1b },
{ 0x40d78, 0x1c1c1c },
{ 0x40d7c, 0x1c1c1c },
{ 0x40d80, 0x1d1d1d },
{ 0x40d84, 0x1e1e1e },
{ 0x40d88, 0x1f1f1f },
{ 0x40d8c, 0x1f1f1f },
{ 0x40d90, 0x202020 },
{ 0x40d94, 0x212121 },
{ 0x40d98, 0x212121 },
{ 0x40d9c, 0x222222 },
{ 0x40da0, 0x232323 },
{ 0x40da4, 0x242424 },
{ 0x40da8, 0x242424 },
{ 0x40dac, 0x252525 },
{ 0x40db0, 0x262626 },
{ 0x40db4, 0x272727 },
{ 0x40db8, 0x272727 },
{ 0x40dbc, 0x282828 },
{ 0x40dc0, 0x292929 },
{ 0x40dc4, 0x2a2a2a },
{ 0x40dc8, 0x2b2b2b },
{ 0x40dcc, 0x2c2c2c },
{ 0x40dd0, 0x2c2c2c },
{ 0x40dd4, 0x2d2d2d },
{ 0x40dd8, 0x2e2e2e },
{ 0x40ddc, 0x2f2f2f },
{ 0x40de0, 0x303030 },
{ 0x40de4, 0x313131 },
{ 0x40de8, 0x323232 },
{ 0x40dec, 0x333333 },
{ 0x40df0, 0x333333 },
{ 0x40df4, 0x343434 },
{ 0x40df8, 0x353535 },
{ 0x40dfc, 0x363636 },
{ 0x40e00, 0x373737 },
{ 0x40e04, 0x383838 },
{ 0x40e08, 0x393939 },
{ 0x40e0c, 0x3a3a3a },
{ 0x40e10, 0x3b3b3b },
{ 0x40e14, 0x3c3c3c },
{ 0x40e18, 0x3d3d3d },
{ 0x40e1c, 0x3e3e3e },
{ 0x40e20, 0x3f3f3f },
{ 0x40e24, 0x404040 },
{ 0x40e28, 0x414141 },
{ 0x40e2c, 0x424242 },
{ 0x40e30, 0x434343 },
{ 0x40e34, 0x444444 },
{ 0x40e38, 0x464646 },
{ 0x40e3c, 0x474747 },
{ 0x40e40, 0x484848 },
{ 0x40e44, 0x494949 },
{ 0x40e48, 0x4a4a4a },
{ 0x40e4c, 0x4b4b4b },
{ 0x40e50, 0x4c4c4c },
{ 0x40e54, 0x4d4d4d },
{ 0x40e58, 0x4f4f4f },
{ 0x40e5c, 0x505050 },
{ 0x40e60, 0x515151 },
{ 0x40e64, 0x525252 },
{ 0x40e68, 0x535353 },
{ 0x40e6c, 0x545454 },
{ 0x40e70, 0x565656 },
{ 0x40e74, 0x575757 },
{ 0x40e78, 0x585858 },
{ 0x40e7c, 0x595959 },
{ 0x40e80, 0x5b5b5b },
{ 0x40e84, 0x5c5c5c },
{ 0x40e88, 0x5d5d5d },
{ 0x40e8c, 0x5e5e5e },
{ 0x40e90, 0x606060 },
{ 0x40e94, 0x616161 },
{ 0x40e98, 0x626262 },
{ 0x40e9c, 0x646464 },
{ 0x40ea0, 0x656565 },
{ 0x40ea4, 0x666666 },
{ 0x40ea8, 0x686868 },
{ 0x40eac, 0x696969 },
{ 0x40eb0, 0x6a6a6a },
{ 0x40eb4, 0x6c6c6c },
{ 0x40eb8, 0x6d6d6d },
{ 0x40ebc, 0x6f6f6f },
{ 0x40ec0, 0x707070 },
{ 0x40ec4, 0x717171 },
{ 0x40ec8, 0x737373 },
{ 0x40ecc, 0x747474 },
{ 0x40ed0, 0x767676 },
{ 0x40ed4, 0x777777 },
{ 0x40ed8, 0x797979 },
{ 0x40edc, 0x7a7a7a },
{ 0x40ee0, 0x7c7c7c },
{ 0x40ee4, 0x7d7d7d },
{ 0x40ee8, 0x7f7f7f },
{ 0x40eec, 0x808080 },
{ 0x40ef0, 0x828282 },
{ 0x40ef4, 0x838383 },
{ 0x40ef8, 0x858585 },
{ 0x40efc, 0x868686 },
{ 0x40f00, 0x888888 },
{ 0x40f04, 0x898989 },
{ 0x40f08, 0x8b8b8b },
{ 0x40f0c, 0x8d8d8d },
{ 0x40f10, 0x8e8e8e },
{ 0x40f14, 0x909090 },
{ 0x40f18, 0x919191 },
{ 0x40f1c, 0x939393 },
{ 0x40f20, 0x959595 },
{ 0x40f24, 0x969696 },
{ 0x40f28, 0x989898 },
{ 0x40f2c, 0x9a9a9a },
{ 0x40f30, 0x9b9b9b },
{ 0x40f34, 0x9d9d9d },
{ 0x40f38, 0x9f9f9f },
{ 0x40f3c, 0xa1a1a1 },
{ 0x40f40, 0xa2a2a2 },
{ 0x40f44, 0xa4a4a4 },
{ 0x40f48, 0xa6a6a6 },
{ 0x40f4c, 0xa7a7a7 },
{ 0x40f50, 0xa9a9a9 },
{ 0x40f54, 0xababab },
{ 0x40f58, 0xadadad },
{ 0x40f5c, 0xafafaf },
{ 0x40f60, 0xb0b0b0 },
{ 0x40f64, 0xb2b2b2 },
{ 0x40f68, 0xb4b4b4 },
{ 0x40f6c, 0xb6b6b6 },
{ 0x40f70, 0xb8b8b8 },
{ 0x40f74, 0xbababa },
{ 0x40f78, 0xbbbbbb },
{ 0x40f7c, 0xbdbdbd },
{ 0x40f80, 0xbfbfbf },
{ 0x40f84, 0xc1c1c1 },
{ 0x40f88, 0xc3c3c3 },
{ 0x40f8c, 0xc5c5c5 },
{ 0x40f90, 0xc7c7c7 },
{ 0x40f94, 0xc9c9c9 },
{ 0x40f98, 0xcbcbcb },
{ 0x40f9c, 0xcdcdcd },
{ 0x40fa0, 0xcfcfcf },
{ 0x40fa4, 0xd1d1d1 },
{ 0x40fa8, 0xd3d3d3 },
{ 0x40fac, 0xd5d5d5 },
{ 0x40fb0, 0xd7d7d7 },
{ 0x40fb4, 0xd9d9d9 },
{ 0x40fb8, 0xdbdbdb },
{ 0x40fbc, 0xdddddd },
{ 0x40fc0, 0xdfdfdf },
{ 0x40fc4, 0xe1e1e1 },
{ 0x40fc8, 0xe3e3e3 },
{ 0x40fcc, 0xe5e5e5 },
{ 0x40fd0, 0xe7e7e7 },
{ 0x40fd4, 0xe9e9e9 },
{ 0x40fd8, 0xebebeb },
{ 0x40fdc, 0xeeeeee },
{ 0x40fe0, 0xf0f0f0 },
{ 0x40fe4, 0xf2f2f2 },
{ 0x40fe8, 0xf4f4f4 },
{ 0x40fec, 0xf6f6f6 },
{ 0x40ff0, 0xf8f8f8 },
{ 0x40ff4, 0xfbfbfb },
{ 0x40ff8, 0xfdfdfd },
{ 0x40ffc, 0xffffff },
};

621
drivers/video/msm/mdp_hw.h Normal file
View File

@@ -0,0 +1,621 @@
/* drivers/video/msm_fb/mdp_hw.h
*
* Copyright (C) 2007 QUALCOMM Incorporated
* Copyright (C) 2007 Google Incorporated
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _MDP_HW_H_
#define _MDP_HW_H_
#include <mach/msm_iomap.h>
#include <mach/msm_fb.h>
struct mdp_info {
struct mdp_device mdp_dev;
char * __iomem base;
int irq;
};
struct mdp_blit_req;
struct mdp_device;
int mdp_ppp_blit(const struct mdp_info *mdp, struct mdp_blit_req *req,
struct file *src_file, unsigned long src_start,
unsigned long src_len, struct file *dst_file,
unsigned long dst_start, unsigned long dst_len);
#define mdp_writel(mdp, value, offset) writel(value, mdp->base + offset)
#define mdp_readl(mdp, offset) readl(mdp->base + offset)
#define MDP_SYNC_CONFIG_0 (0x00000)
#define MDP_SYNC_CONFIG_1 (0x00004)
#define MDP_SYNC_CONFIG_2 (0x00008)
#define MDP_SYNC_STATUS_0 (0x0000c)
#define MDP_SYNC_STATUS_1 (0x00010)
#define MDP_SYNC_STATUS_2 (0x00014)
#define MDP_SYNC_THRESH_0 (0x00018)
#define MDP_SYNC_THRESH_1 (0x0001c)
#define MDP_INTR_ENABLE (0x00020)
#define MDP_INTR_STATUS (0x00024)
#define MDP_INTR_CLEAR (0x00028)
#define MDP_DISPLAY0_START (0x00030)
#define MDP_DISPLAY1_START (0x00034)
#define MDP_DISPLAY_STATUS (0x00038)
#define MDP_EBI2_LCD0 (0x0003c)
#define MDP_EBI2_LCD1 (0x00040)
#define MDP_DISPLAY0_ADDR (0x00054)
#define MDP_DISPLAY1_ADDR (0x00058)
#define MDP_EBI2_PORTMAP_MODE (0x0005c)
#define MDP_MODE (0x00060)
#define MDP_TV_OUT_STATUS (0x00064)
#define MDP_HW_VERSION (0x00070)
#define MDP_SW_RESET (0x00074)
#define MDP_AXI_ERROR_MASTER_STOP (0x00078)
#define MDP_SEL_CLK_OR_HCLK_TEST_BUS (0x0007c)
#define MDP_PRIMARY_VSYNC_OUT_CTRL (0x00080)
#define MDP_SECONDARY_VSYNC_OUT_CTRL (0x00084)
#define MDP_EXTERNAL_VSYNC_OUT_CTRL (0x00088)
#define MDP_VSYNC_CTRL (0x0008c)
#define MDP_CGC_EN (0x00100)
#define MDP_CMD_STATUS (0x10008)
#define MDP_PROFILE_EN (0x10010)
#define MDP_PROFILE_COUNT (0x10014)
#define MDP_DMA_START (0x10044)
#define MDP_FULL_BYPASS_WORD0 (0x10100)
#define MDP_FULL_BYPASS_WORD1 (0x10104)
#define MDP_COMMAND_CONFIG (0x10104)
#define MDP_FULL_BYPASS_WORD2 (0x10108)
#define MDP_FULL_BYPASS_WORD3 (0x1010c)
#define MDP_FULL_BYPASS_WORD4 (0x10110)
#define MDP_FULL_BYPASS_WORD6 (0x10118)
#define MDP_FULL_BYPASS_WORD7 (0x1011c)
#define MDP_FULL_BYPASS_WORD8 (0x10120)
#define MDP_FULL_BYPASS_WORD9 (0x10124)
#define MDP_PPP_SOURCE_CONFIG (0x10124)
#define MDP_FULL_BYPASS_WORD10 (0x10128)
#define MDP_FULL_BYPASS_WORD11 (0x1012c)
#define MDP_FULL_BYPASS_WORD12 (0x10130)
#define MDP_FULL_BYPASS_WORD13 (0x10134)
#define MDP_FULL_BYPASS_WORD14 (0x10138)
#define MDP_PPP_OPERATION_CONFIG (0x10138)
#define MDP_FULL_BYPASS_WORD15 (0x1013c)
#define MDP_FULL_BYPASS_WORD16 (0x10140)
#define MDP_FULL_BYPASS_WORD17 (0x10144)
#define MDP_FULL_BYPASS_WORD18 (0x10148)
#define MDP_FULL_BYPASS_WORD19 (0x1014c)
#define MDP_FULL_BYPASS_WORD20 (0x10150)
#define MDP_PPP_DESTINATION_CONFIG (0x10150)
#define MDP_FULL_BYPASS_WORD21 (0x10154)
#define MDP_FULL_BYPASS_WORD22 (0x10158)
#define MDP_FULL_BYPASS_WORD23 (0x1015c)
#define MDP_FULL_BYPASS_WORD24 (0x10160)
#define MDP_FULL_BYPASS_WORD25 (0x10164)
#define MDP_FULL_BYPASS_WORD26 (0x10168)
#define MDP_FULL_BYPASS_WORD27 (0x1016c)
#define MDP_FULL_BYPASS_WORD29 (0x10174)
#define MDP_FULL_BYPASS_WORD30 (0x10178)
#define MDP_FULL_BYPASS_WORD31 (0x1017c)
#define MDP_FULL_BYPASS_WORD32 (0x10180)
#define MDP_DMA_CONFIG (0x10180)
#define MDP_FULL_BYPASS_WORD33 (0x10184)
#define MDP_FULL_BYPASS_WORD34 (0x10188)
#define MDP_FULL_BYPASS_WORD35 (0x1018c)
#define MDP_FULL_BYPASS_WORD37 (0x10194)
#define MDP_FULL_BYPASS_WORD39 (0x1019c)
#define MDP_FULL_BYPASS_WORD40 (0x101a0)
#define MDP_FULL_BYPASS_WORD41 (0x101a4)
#define MDP_FULL_BYPASS_WORD43 (0x101ac)
#define MDP_FULL_BYPASS_WORD46 (0x101b8)
#define MDP_FULL_BYPASS_WORD47 (0x101bc)
#define MDP_FULL_BYPASS_WORD48 (0x101c0)
#define MDP_FULL_BYPASS_WORD49 (0x101c4)
#define MDP_FULL_BYPASS_WORD50 (0x101c8)
#define MDP_FULL_BYPASS_WORD51 (0x101cc)
#define MDP_FULL_BYPASS_WORD52 (0x101d0)
#define MDP_FULL_BYPASS_WORD53 (0x101d4)
#define MDP_FULL_BYPASS_WORD54 (0x101d8)
#define MDP_FULL_BYPASS_WORD55 (0x101dc)
#define MDP_FULL_BYPASS_WORD56 (0x101e0)
#define MDP_FULL_BYPASS_WORD57 (0x101e4)
#define MDP_FULL_BYPASS_WORD58 (0x101e8)
#define MDP_FULL_BYPASS_WORD59 (0x101ec)
#define MDP_FULL_BYPASS_WORD60 (0x101f0)
#define MDP_VSYNC_THRESHOLD (0x101f0)
#define MDP_FULL_BYPASS_WORD61 (0x101f4)
#define MDP_FULL_BYPASS_WORD62 (0x101f8)
#define MDP_FULL_BYPASS_WORD63 (0x101fc)
#define MDP_TFETCH_TEST_MODE (0x20004)
#define MDP_TFETCH_STATUS (0x20008)
#define MDP_TFETCH_TILE_COUNT (0x20010)
#define MDP_TFETCH_FETCH_COUNT (0x20014)
#define MDP_TFETCH_CONSTANT_COLOR (0x20040)
#define MDP_CSC_BYPASS (0x40004)
#define MDP_SCALE_COEFF_LSB (0x5fffc)
#define MDP_TV_OUT_CTL (0xc0000)
#define MDP_TV_OUT_FIR_COEFF (0xc0004)
#define MDP_TV_OUT_BUF_ADDR (0xc0008)
#define MDP_TV_OUT_CC_DATA (0xc000c)
#define MDP_TV_OUT_SOBEL (0xc0010)
#define MDP_TV_OUT_Y_CLAMP (0xc0018)
#define MDP_TV_OUT_CB_CLAMP (0xc001c)
#define MDP_TV_OUT_CR_CLAMP (0xc0020)
#define MDP_TEST_MODE_CLK (0xd0000)
#define MDP_TEST_MISR_RESET_CLK (0xd0004)
#define MDP_TEST_EXPORT_MISR_CLK (0xd0008)
#define MDP_TEST_MISR_CURR_VAL_CLK (0xd000c)
#define MDP_TEST_MODE_HCLK (0xd0100)
#define MDP_TEST_MISR_RESET_HCLK (0xd0104)
#define MDP_TEST_EXPORT_MISR_HCLK (0xd0108)
#define MDP_TEST_MISR_CURR_VAL_HCLK (0xd010c)
#define MDP_TEST_MODE_DCLK (0xd0200)
#define MDP_TEST_MISR_RESET_DCLK (0xd0204)
#define MDP_TEST_EXPORT_MISR_DCLK (0xd0208)
#define MDP_TEST_MISR_CURR_VAL_DCLK (0xd020c)
#define MDP_TEST_CAPTURED_DCLK (0xd0210)
#define MDP_TEST_MISR_CAPT_VAL_DCLK (0xd0214)
#define MDP_LCDC_CTL (0xe0000)
#define MDP_LCDC_HSYNC_CTL (0xe0004)
#define MDP_LCDC_VSYNC_CTL (0xe0008)
#define MDP_LCDC_ACTIVE_HCTL (0xe000c)
#define MDP_LCDC_ACTIVE_VCTL (0xe0010)
#define MDP_LCDC_BORDER_CLR (0xe0014)
#define MDP_LCDC_H_BLANK (0xe0018)
#define MDP_LCDC_V_BLANK (0xe001c)
#define MDP_LCDC_UNDERFLOW_CLR (0xe0020)
#define MDP_LCDC_HSYNC_SKEW (0xe0024)
#define MDP_LCDC_TEST_CTL (0xe0028)
#define MDP_LCDC_LINE_IRQ (0xe002c)
#define MDP_LCDC_CTL_POLARITY (0xe0030)
#define MDP_LCDC_DMA_CONFIG (0xe1000)
#define MDP_LCDC_DMA_SIZE (0xe1004)
#define MDP_LCDC_DMA_IBUF_ADDR (0xe1008)
#define MDP_LCDC_DMA_IBUF_Y_STRIDE (0xe100c)
#define MDP_DMA2_TERM 0x1
#define MDP_DMA3_TERM 0x2
#define MDP_PPP_TERM 0x3
/* MDP_INTR_ENABLE */
#define DL0_ROI_DONE (1<<0)
#define DL1_ROI_DONE (1<<1)
#define DL0_DMA2_TERM_DONE (1<<2)
#define DL1_DMA2_TERM_DONE (1<<3)
#define DL0_PPP_TERM_DONE (1<<4)
#define DL1_PPP_TERM_DONE (1<<5)
#define TV_OUT_DMA3_DONE (1<<6)
#define TV_ENC_UNDERRUN (1<<7)
#define DL0_FETCH_DONE (1<<11)
#define DL1_FETCH_DONE (1<<12)
#define MDP_PPP_BUSY_STATUS (DL0_ROI_DONE| \
DL1_ROI_DONE| \
DL0_PPP_TERM_DONE| \
DL1_PPP_TERM_DONE)
#define MDP_ANY_INTR_MASK (DL0_ROI_DONE| \
DL1_ROI_DONE| \
DL0_DMA2_TERM_DONE| \
DL1_DMA2_TERM_DONE| \
DL0_PPP_TERM_DONE| \
DL1_PPP_TERM_DONE| \
DL0_FETCH_DONE| \
DL1_FETCH_DONE| \
TV_ENC_UNDERRUN)
#define MDP_TOP_LUMA 16
#define MDP_TOP_CHROMA 0
#define MDP_BOTTOM_LUMA 19
#define MDP_BOTTOM_CHROMA 3
#define MDP_LEFT_LUMA 22
#define MDP_LEFT_CHROMA 6
#define MDP_RIGHT_LUMA 25
#define MDP_RIGHT_CHROMA 9
#define CLR_G 0x0
#define CLR_B 0x1
#define CLR_R 0x2
#define CLR_ALPHA 0x3
#define CLR_Y CLR_G
#define CLR_CB CLR_B
#define CLR_CR CLR_R
/* from lsb to msb */
#define MDP_GET_PACK_PATTERN(a, x, y, z, bit) \
(((a)<<(bit*3))|((x)<<(bit*2))|((y)<<bit)|(z))
/* MDP_SYNC_CONFIG_0/1/2 */
#define MDP_SYNCFG_HGT_LOC 22
#define MDP_SYNCFG_VSYNC_EXT_EN (1<<21)
#define MDP_SYNCFG_VSYNC_INT_EN (1<<20)
/* MDP_SYNC_THRESH_0 */
#define MDP_PRIM_BELOW_LOC 0
#define MDP_PRIM_ABOVE_LOC 8
/* MDP_{PRIMARY,SECONDARY,EXTERNAL}_VSYNC_OUT_CRL */
#define VSYNC_PULSE_EN (1<<31)
#define VSYNC_PULSE_INV (1<<30)
/* MDP_VSYNC_CTRL */
#define DISP0_VSYNC_MAP_VSYNC0 0
#define DISP0_VSYNC_MAP_VSYNC1 (1<<0)
#define DISP0_VSYNC_MAP_VSYNC2 ((1<<0)|(1<<1))
#define DISP1_VSYNC_MAP_VSYNC0 0
#define DISP1_VSYNC_MAP_VSYNC1 (1<<2)
#define DISP1_VSYNC_MAP_VSYNC2 ((1<<2)|(1<<3))
#define PRIMARY_LCD_SYNC_EN (1<<4)
#define PRIMARY_LCD_SYNC_DISABLE 0
#define SECONDARY_LCD_SYNC_EN (1<<5)
#define SECONDARY_LCD_SYNC_DISABLE 0
#define EXTERNAL_LCD_SYNC_EN (1<<6)
#define EXTERNAL_LCD_SYNC_DISABLE 0
/* MDP_VSYNC_THRESHOLD / MDP_FULL_BYPASS_WORD60 */
#define VSYNC_THRESHOLD_ABOVE_LOC 0
#define VSYNC_THRESHOLD_BELOW_LOC 16
#define VSYNC_ANTI_TEAR_EN (1<<31)
/* MDP_COMMAND_CONFIG / MDP_FULL_BYPASS_WORD1 */
#define MDP_CMD_DBGBUS_EN (1<<0)
/* MDP_PPP_SOURCE_CONFIG / MDP_FULL_BYPASS_WORD9&53 */
#define PPP_SRC_C0G_8BIT ((1<<1)|(1<<0))
#define PPP_SRC_C1B_8BIT ((1<<3)|(1<<2))
#define PPP_SRC_C2R_8BIT ((1<<5)|(1<<4))
#define PPP_SRC_C3A_8BIT ((1<<7)|(1<<6))
#define PPP_SRC_C0G_6BIT (1<<1)
#define PPP_SRC_C1B_6BIT (1<<3)
#define PPP_SRC_C2R_6BIT (1<<5)
#define PPP_SRC_C0G_5BIT (1<<0)
#define PPP_SRC_C1B_5BIT (1<<2)
#define PPP_SRC_C2R_5BIT (1<<4)
#define PPP_SRC_C3ALPHA_EN (1<<8)
#define PPP_SRC_BPP_1BYTES 0
#define PPP_SRC_BPP_2BYTES (1<<9)
#define PPP_SRC_BPP_3BYTES (1<<10)
#define PPP_SRC_BPP_4BYTES ((1<<10)|(1<<9))
#define PPP_SRC_BPP_ROI_ODD_X (1<<11)
#define PPP_SRC_BPP_ROI_ODD_Y (1<<12)
#define PPP_SRC_INTERLVD_2COMPONENTS (1<<13)
#define PPP_SRC_INTERLVD_3COMPONENTS (1<<14)
#define PPP_SRC_INTERLVD_4COMPONENTS ((1<<14)|(1<<13))
/* RGB666 unpack format
** TIGHT means R6+G6+B6 together
** LOOSE means R6+2 +G6+2+ B6+2 (with MSB)
** or 2+R6 +2+G6 +2+B6 (with LSB)
*/
#define PPP_SRC_PACK_TIGHT (1<<17)
#define PPP_SRC_PACK_LOOSE 0
#define PPP_SRC_PACK_ALIGN_LSB 0
#define PPP_SRC_PACK_ALIGN_MSB (1<<18)
#define PPP_SRC_PLANE_INTERLVD 0
#define PPP_SRC_PLANE_PSEUDOPLNR (1<<20)
#define PPP_SRC_WMV9_MODE (1<<21)
/* MDP_PPP_OPERATION_CONFIG / MDP_FULL_BYPASS_WORD14 */
#define PPP_OP_SCALE_X_ON (1<<0)
#define PPP_OP_SCALE_Y_ON (1<<1)
#define PPP_OP_CONVERT_RGB2YCBCR 0
#define PPP_OP_CONVERT_YCBCR2RGB (1<<2)
#define PPP_OP_CONVERT_ON (1<<3)
#define PPP_OP_CONVERT_MATRIX_PRIMARY 0
#define PPP_OP_CONVERT_MATRIX_SECONDARY (1<<4)
#define PPP_OP_LUT_C0_ON (1<<5)
#define PPP_OP_LUT_C1_ON (1<<6)
#define PPP_OP_LUT_C2_ON (1<<7)
/* rotate or blend enable */
#define PPP_OP_ROT_ON (1<<8)
#define PPP_OP_ROT_90 (1<<9)
#define PPP_OP_FLIP_LR (1<<10)
#define PPP_OP_FLIP_UD (1<<11)
#define PPP_OP_BLEND_ON (1<<12)
#define PPP_OP_BLEND_SRCPIXEL_ALPHA 0
#define PPP_OP_BLEND_DSTPIXEL_ALPHA (1<<13)
#define PPP_OP_BLEND_CONSTANT_ALPHA (1<<14)
#define PPP_OP_BLEND_SRCPIXEL_TRANSP ((1<<13)|(1<<14))
#define PPP_OP_BLEND_ALPHA_BLEND_NORMAL 0
#define PPP_OP_BLEND_ALPHA_BLEND_REVERSE (1<<15)
#define PPP_OP_DITHER_EN (1<<16)
#define PPP_OP_COLOR_SPACE_RGB 0
#define PPP_OP_COLOR_SPACE_YCBCR (1<<17)
#define PPP_OP_SRC_CHROMA_RGB 0
#define PPP_OP_SRC_CHROMA_H2V1 (1<<18)
#define PPP_OP_SRC_CHROMA_H1V2 (1<<19)
#define PPP_OP_SRC_CHROMA_420 ((1<<18)|(1<<19))
#define PPP_OP_SRC_CHROMA_COSITE 0
#define PPP_OP_SRC_CHROMA_OFFSITE (1<<20)
#define PPP_OP_DST_CHROMA_RGB 0
#define PPP_OP_DST_CHROMA_H2V1 (1<<21)
#define PPP_OP_DST_CHROMA_H1V2 (1<<22)
#define PPP_OP_DST_CHROMA_420 ((1<<21)|(1<<22))
#define PPP_OP_DST_CHROMA_COSITE 0
#define PPP_OP_DST_CHROMA_OFFSITE (1<<23)
#define PPP_BLEND_ALPHA_TRANSP (1<<24)
#define PPP_OP_BG_CHROMA_RGB 0
#define PPP_OP_BG_CHROMA_H2V1 (1<<25)
#define PPP_OP_BG_CHROMA_H1V2 (1<<26)
#define PPP_OP_BG_CHROMA_420 ((1<<25)|(1<<26))
#define PPP_OP_BG_CHROMA_SITE_COSITE 0
#define PPP_OP_BG_CHROMA_SITE_OFFSITE (1<<27)
/* MDP_PPP_DESTINATION_CONFIG / MDP_FULL_BYPASS_WORD20 */
#define PPP_DST_C0G_8BIT ((1<<0)|(1<<1))
#define PPP_DST_C1B_8BIT ((1<<3)|(1<<2))
#define PPP_DST_C2R_8BIT ((1<<5)|(1<<4))
#define PPP_DST_C3A_8BIT ((1<<7)|(1<<6))
#define PPP_DST_C0G_6BIT (1<<1)
#define PPP_DST_C1B_6BIT (1<<3)
#define PPP_DST_C2R_6BIT (1<<5)
#define PPP_DST_C0G_5BIT (1<<0)
#define PPP_DST_C1B_5BIT (1<<2)
#define PPP_DST_C2R_5BIT (1<<4)
#define PPP_DST_C3A_8BIT ((1<<7)|(1<<6))
#define PPP_DST_C3ALPHA_EN (1<<8)
#define PPP_DST_INTERLVD_2COMPONENTS (1<<9)
#define PPP_DST_INTERLVD_3COMPONENTS (1<<10)
#define PPP_DST_INTERLVD_4COMPONENTS ((1<<10)|(1<<9))
#define PPP_DST_INTERLVD_6COMPONENTS ((1<<11)|(1<<9))
#define PPP_DST_PACK_LOOSE 0
#define PPP_DST_PACK_TIGHT (1<<13)
#define PPP_DST_PACK_ALIGN_LSB 0
#define PPP_DST_PACK_ALIGN_MSB (1<<14)
#define PPP_DST_OUT_SEL_AXI 0
#define PPP_DST_OUT_SEL_MDDI (1<<15)
#define PPP_DST_BPP_2BYTES (1<<16)
#define PPP_DST_BPP_3BYTES (1<<17)
#define PPP_DST_BPP_4BYTES ((1<<17)|(1<<16))
#define PPP_DST_PLANE_INTERLVD 0
#define PPP_DST_PLANE_PLANAR (1<<18)
#define PPP_DST_PLANE_PSEUDOPLNR (1<<19)
#define PPP_DST_TO_TV (1<<20)
#define PPP_DST_MDDI_PRIMARY 0
#define PPP_DST_MDDI_SECONDARY (1<<21)
#define PPP_DST_MDDI_EXTERNAL (1<<22)
/* image configurations by image type */
#define PPP_CFG_MDP_RGB_565(dir) (PPP_##dir##_C2R_5BIT | \
PPP_##dir##_C0G_6BIT | \
PPP_##dir##_C1B_5BIT | \
PPP_##dir##_BPP_2BYTES | \
PPP_##dir##_INTERLVD_3COMPONENTS | \
PPP_##dir##_PACK_TIGHT | \
PPP_##dir##_PACK_ALIGN_LSB | \
PPP_##dir##_PLANE_INTERLVD)
#define PPP_CFG_MDP_RGB_888(dir) (PPP_##dir##_C2R_8BIT | \
PPP_##dir##_C0G_8BIT | \
PPP_##dir##_C1B_8BIT | \
PPP_##dir##_BPP_3BYTES | \
PPP_##dir##_INTERLVD_3COMPONENTS | \
PPP_##dir##_PACK_TIGHT | \
PPP_##dir##_PACK_ALIGN_LSB | \
PPP_##dir##_PLANE_INTERLVD)
#define PPP_CFG_MDP_ARGB_8888(dir) (PPP_##dir##_C2R_8BIT | \
PPP_##dir##_C0G_8BIT | \
PPP_##dir##_C1B_8BIT | \
PPP_##dir##_C3A_8BIT | \
PPP_##dir##_C3ALPHA_EN | \
PPP_##dir##_BPP_4BYTES | \
PPP_##dir##_INTERLVD_4COMPONENTS | \
PPP_##dir##_PACK_TIGHT | \
PPP_##dir##_PACK_ALIGN_LSB | \
PPP_##dir##_PLANE_INTERLVD)
#define PPP_CFG_MDP_XRGB_8888(dir) PPP_CFG_MDP_ARGB_8888(dir)
#define PPP_CFG_MDP_RGBA_8888(dir) PPP_CFG_MDP_ARGB_8888(dir)
#define PPP_CFG_MDP_BGRA_8888(dir) PPP_CFG_MDP_ARGB_8888(dir)
#define PPP_CFG_MDP_Y_CBCR_H2V2(dir) (PPP_##dir##_C2R_8BIT | \
PPP_##dir##_C0G_8BIT | \
PPP_##dir##_C1B_8BIT | \
PPP_##dir##_C3A_8BIT | \
PPP_##dir##_BPP_2BYTES | \
PPP_##dir##_INTERLVD_2COMPONENTS | \
PPP_##dir##_PACK_TIGHT | \
PPP_##dir##_PACK_ALIGN_LSB | \
PPP_##dir##_PLANE_PSEUDOPLNR)
#define PPP_CFG_MDP_Y_CRCB_H2V2(dir) PPP_CFG_MDP_Y_CBCR_H2V2(dir)
#define PPP_CFG_MDP_YCRYCB_H2V1(dir) (PPP_##dir##_C2R_8BIT | \
PPP_##dir##_C0G_8BIT | \
PPP_##dir##_C1B_8BIT | \
PPP_##dir##_C3A_8BIT | \
PPP_##dir##_BPP_2BYTES | \
PPP_##dir##_INTERLVD_4COMPONENTS | \
PPP_##dir##_PACK_TIGHT | \
PPP_##dir##_PACK_ALIGN_LSB |\
PPP_##dir##_PLANE_INTERLVD)
#define PPP_CFG_MDP_Y_CBCR_H2V1(dir) (PPP_##dir##_C2R_8BIT | \
PPP_##dir##_C0G_8BIT | \
PPP_##dir##_C1B_8BIT | \
PPP_##dir##_C3A_8BIT | \
PPP_##dir##_BPP_2BYTES | \
PPP_##dir##_INTERLVD_2COMPONENTS | \
PPP_##dir##_PACK_TIGHT | \
PPP_##dir##_PACK_ALIGN_LSB | \
PPP_##dir##_PLANE_PSEUDOPLNR)
#define PPP_CFG_MDP_Y_CRCB_H2V1(dir) PPP_CFG_MDP_Y_CBCR_H2V1(dir)
#define PPP_PACK_PATTERN_MDP_RGB_565 \
MDP_GET_PACK_PATTERN(0, CLR_R, CLR_G, CLR_B, 8)
#define PPP_PACK_PATTERN_MDP_RGB_888 PPP_PACK_PATTERN_MDP_RGB_565
#define PPP_PACK_PATTERN_MDP_XRGB_8888 \
MDP_GET_PACK_PATTERN(CLR_ALPHA, CLR_R, CLR_G, CLR_B, 8)
#define PPP_PACK_PATTERN_MDP_ARGB_8888 PPP_PACK_PATTERN_MDP_XRGB_8888
#define PPP_PACK_PATTERN_MDP_RGBA_8888 \
MDP_GET_PACK_PATTERN(CLR_ALPHA, CLR_B, CLR_G, CLR_R, 8)
#define PPP_PACK_PATTERN_MDP_BGRA_8888 \
MDP_GET_PACK_PATTERN(CLR_ALPHA, CLR_R, CLR_G, CLR_B, 8)
#define PPP_PACK_PATTERN_MDP_Y_CBCR_H2V1 \
MDP_GET_PACK_PATTERN(0, 0, CLR_CB, CLR_CR, 8)
#define PPP_PACK_PATTERN_MDP_Y_CBCR_H2V2 PPP_PACK_PATTERN_MDP_Y_CBCR_H2V1
#define PPP_PACK_PATTERN_MDP_Y_CRCB_H2V1 \
MDP_GET_PACK_PATTERN(0, 0, CLR_CR, CLR_CB, 8)
#define PPP_PACK_PATTERN_MDP_Y_CRCB_H2V2 PPP_PACK_PATTERN_MDP_Y_CRCB_H2V1
#define PPP_PACK_PATTERN_MDP_YCRYCB_H2V1 \
MDP_GET_PACK_PATTERN(CLR_Y, CLR_R, CLR_Y, CLR_B, 8)
#define PPP_CHROMA_SAMP_MDP_RGB_565(dir) PPP_OP_##dir##_CHROMA_RGB
#define PPP_CHROMA_SAMP_MDP_RGB_888(dir) PPP_OP_##dir##_CHROMA_RGB
#define PPP_CHROMA_SAMP_MDP_XRGB_8888(dir) PPP_OP_##dir##_CHROMA_RGB
#define PPP_CHROMA_SAMP_MDP_ARGB_8888(dir) PPP_OP_##dir##_CHROMA_RGB
#define PPP_CHROMA_SAMP_MDP_RGBA_8888(dir) PPP_OP_##dir##_CHROMA_RGB
#define PPP_CHROMA_SAMP_MDP_BGRA_8888(dir) PPP_OP_##dir##_CHROMA_RGB
#define PPP_CHROMA_SAMP_MDP_Y_CBCR_H2V1(dir) PPP_OP_##dir##_CHROMA_H2V1
#define PPP_CHROMA_SAMP_MDP_Y_CBCR_H2V2(dir) PPP_OP_##dir##_CHROMA_420
#define PPP_CHROMA_SAMP_MDP_Y_CRCB_H2V1(dir) PPP_OP_##dir##_CHROMA_H2V1
#define PPP_CHROMA_SAMP_MDP_Y_CRCB_H2V2(dir) PPP_OP_##dir##_CHROMA_420
#define PPP_CHROMA_SAMP_MDP_YCRYCB_H2V1(dir) PPP_OP_##dir##_CHROMA_H2V1
/* Helpful array generation macros */
#define PPP_ARRAY0(name) \
[MDP_RGB_565] = PPP_##name##_MDP_RGB_565,\
[MDP_RGB_888] = PPP_##name##_MDP_RGB_888,\
[MDP_XRGB_8888] = PPP_##name##_MDP_XRGB_8888,\
[MDP_ARGB_8888] = PPP_##name##_MDP_ARGB_8888,\
[MDP_RGBA_8888] = PPP_##name##_MDP_RGBA_8888,\
[MDP_BGRA_8888] = PPP_##name##_MDP_BGRA_8888,\
[MDP_Y_CBCR_H2V1] = PPP_##name##_MDP_Y_CBCR_H2V1,\
[MDP_Y_CBCR_H2V2] = PPP_##name##_MDP_Y_CBCR_H2V2,\
[MDP_Y_CRCB_H2V1] = PPP_##name##_MDP_Y_CRCB_H2V1,\
[MDP_Y_CRCB_H2V2] = PPP_##name##_MDP_Y_CRCB_H2V2,\
[MDP_YCRYCB_H2V1] = PPP_##name##_MDP_YCRYCB_H2V1
#define PPP_ARRAY1(name, dir) \
[MDP_RGB_565] = PPP_##name##_MDP_RGB_565(dir),\
[MDP_RGB_888] = PPP_##name##_MDP_RGB_888(dir),\
[MDP_XRGB_8888] = PPP_##name##_MDP_XRGB_8888(dir),\
[MDP_ARGB_8888] = PPP_##name##_MDP_ARGB_8888(dir),\
[MDP_RGBA_8888] = PPP_##name##_MDP_RGBA_8888(dir),\
[MDP_BGRA_8888] = PPP_##name##_MDP_BGRA_8888(dir),\
[MDP_Y_CBCR_H2V1] = PPP_##name##_MDP_Y_CBCR_H2V1(dir),\
[MDP_Y_CBCR_H2V2] = PPP_##name##_MDP_Y_CBCR_H2V2(dir),\
[MDP_Y_CRCB_H2V1] = PPP_##name##_MDP_Y_CRCB_H2V1(dir),\
[MDP_Y_CRCB_H2V2] = PPP_##name##_MDP_Y_CRCB_H2V2(dir),\
[MDP_YCRYCB_H2V1] = PPP_##name##_MDP_YCRYCB_H2V1(dir)
#define IS_YCRCB(img) ((img == MDP_Y_CRCB_H2V2) | (img == MDP_Y_CBCR_H2V2) | \
(img == MDP_Y_CRCB_H2V1) | (img == MDP_Y_CBCR_H2V1) | \
(img == MDP_YCRYCB_H2V1))
#define IS_RGB(img) ((img == MDP_RGB_565) | (img == MDP_RGB_888) | \
(img == MDP_ARGB_8888) | (img == MDP_RGBA_8888) | \
(img == MDP_XRGB_8888) | (img == MDP_BGRA_8888))
#define HAS_ALPHA(img) ((img == MDP_ARGB_8888) | (img == MDP_RGBA_8888) | \
(img == MDP_BGRA_8888))
#define IS_PSEUDOPLNR(img) ((img == MDP_Y_CRCB_H2V2) | \
(img == MDP_Y_CBCR_H2V2) | \
(img == MDP_Y_CRCB_H2V1) | \
(img == MDP_Y_CBCR_H2V1))
/* Mappings from addr to purpose */
#define PPP_ADDR_SRC_ROI MDP_FULL_BYPASS_WORD2
#define PPP_ADDR_SRC0 MDP_FULL_BYPASS_WORD3
#define PPP_ADDR_SRC1 MDP_FULL_BYPASS_WORD4
#define PPP_ADDR_SRC_YSTRIDE MDP_FULL_BYPASS_WORD7
#define PPP_ADDR_SRC_CFG MDP_FULL_BYPASS_WORD9
#define PPP_ADDR_SRC_PACK_PATTERN MDP_FULL_BYPASS_WORD10
#define PPP_ADDR_OPERATION MDP_FULL_BYPASS_WORD14
#define PPP_ADDR_PHASEX_INIT MDP_FULL_BYPASS_WORD15
#define PPP_ADDR_PHASEY_INIT MDP_FULL_BYPASS_WORD16
#define PPP_ADDR_PHASEX_STEP MDP_FULL_BYPASS_WORD17
#define PPP_ADDR_PHASEY_STEP MDP_FULL_BYPASS_WORD18
#define PPP_ADDR_ALPHA_TRANSP MDP_FULL_BYPASS_WORD19
#define PPP_ADDR_DST_CFG MDP_FULL_BYPASS_WORD20
#define PPP_ADDR_DST_PACK_PATTERN MDP_FULL_BYPASS_WORD21
#define PPP_ADDR_DST_ROI MDP_FULL_BYPASS_WORD25
#define PPP_ADDR_DST0 MDP_FULL_BYPASS_WORD26
#define PPP_ADDR_DST1 MDP_FULL_BYPASS_WORD27
#define PPP_ADDR_DST_YSTRIDE MDP_FULL_BYPASS_WORD30
#define PPP_ADDR_EDGE MDP_FULL_BYPASS_WORD46
#define PPP_ADDR_BG0 MDP_FULL_BYPASS_WORD48
#define PPP_ADDR_BG1 MDP_FULL_BYPASS_WORD49
#define PPP_ADDR_BG_YSTRIDE MDP_FULL_BYPASS_WORD51
#define PPP_ADDR_BG_CFG MDP_FULL_BYPASS_WORD53
#define PPP_ADDR_BG_PACK_PATTERN MDP_FULL_BYPASS_WORD54
/* MDP_DMA_CONFIG / MDP_FULL_BYPASS_WORD32 */
#define DMA_DSTC0G_6BITS (1<<1)
#define DMA_DSTC1B_6BITS (1<<3)
#define DMA_DSTC2R_6BITS (1<<5)
#define DMA_DSTC0G_5BITS (1<<0)
#define DMA_DSTC1B_5BITS (1<<2)
#define DMA_DSTC2R_5BITS (1<<4)
#define DMA_PACK_TIGHT (1<<6)
#define DMA_PACK_LOOSE 0
#define DMA_PACK_ALIGN_LSB 0
#define DMA_PACK_ALIGN_MSB (1<<7)
#define DMA_PACK_PATTERN_RGB \
(MDP_GET_PACK_PATTERN(0, CLR_R, CLR_G, CLR_B, 2)<<8)
#define DMA_OUT_SEL_AHB 0
#define DMA_OUT_SEL_MDDI (1<<14)
#define DMA_AHBM_LCD_SEL_PRIMARY 0
#define DMA_AHBM_LCD_SEL_SECONDARY (1<<15)
#define DMA_IBUF_C3ALPHA_EN (1<<16)
#define DMA_DITHER_EN (1<<17)
#define DMA_MDDI_DMAOUT_LCD_SEL_PRIMARY 0
#define DMA_MDDI_DMAOUT_LCD_SEL_SECONDARY (1<<18)
#define DMA_MDDI_DMAOUT_LCD_SEL_EXTERNAL (1<<19)
#define DMA_IBUF_FORMAT_RGB565 (1<<20)
#define DMA_IBUF_FORMAT_RGB888_OR_ARGB8888 0
#define DMA_IBUF_NONCONTIGUOUS (1<<21)
/* MDDI REGISTER ? */
#define MDDI_VDO_PACKET_DESC 0x5666
#define MDDI_VDO_PACKET_PRIM 0xC3
#define MDDI_VDO_PACKET_SECD 0xC0
#endif

750
drivers/video/msm/mdp_ppp.c Normal file
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/* drivers/video/msm/mdp_ppp.c
*
* Copyright (C) 2007 QUALCOMM Incorporated
* Copyright (C) 2007 Google Incorporated
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/fb.h>
#include <linux/file.h>
#include <linux/delay.h>
#include <linux/msm_mdp.h>
#include <linux/android_pmem.h>
#include <mach/msm_fb.h>
#include "mdp_hw.h"
#include "mdp_scale_tables.h"
#define DLOG(x...) do {} while (0)
#define MDP_DOWNSCALE_BLUR (MDP_DOWNSCALE_MAX + 1)
static int downscale_y_table = MDP_DOWNSCALE_MAX;
static int downscale_x_table = MDP_DOWNSCALE_MAX;
struct mdp_regs {
uint32_t src0;
uint32_t src1;
uint32_t dst0;
uint32_t dst1;
uint32_t src_cfg;
uint32_t dst_cfg;
uint32_t src_pack;
uint32_t dst_pack;
uint32_t src_rect;
uint32_t dst_rect;
uint32_t src_ystride;
uint32_t dst_ystride;
uint32_t op;
uint32_t src_bpp;
uint32_t dst_bpp;
uint32_t edge;
uint32_t phasex_init;
uint32_t phasey_init;
uint32_t phasex_step;
uint32_t phasey_step;
};
static uint32_t pack_pattern[] = {
PPP_ARRAY0(PACK_PATTERN)
};
static uint32_t src_img_cfg[] = {
PPP_ARRAY1(CFG, SRC)
};
static uint32_t dst_img_cfg[] = {
PPP_ARRAY1(CFG, DST)
};
static uint32_t bytes_per_pixel[] = {
[MDP_RGB_565] = 2,
[MDP_RGB_888] = 3,
[MDP_XRGB_8888] = 4,
[MDP_ARGB_8888] = 4,
[MDP_RGBA_8888] = 4,
[MDP_BGRA_8888] = 4,
[MDP_Y_CBCR_H2V1] = 1,
[MDP_Y_CBCR_H2V2] = 1,
[MDP_Y_CRCB_H2V1] = 1,
[MDP_Y_CRCB_H2V2] = 1,
[MDP_YCRYCB_H2V1] = 2
};
static uint32_t dst_op_chroma[] = {
PPP_ARRAY1(CHROMA_SAMP, DST)
};
static uint32_t src_op_chroma[] = {
PPP_ARRAY1(CHROMA_SAMP, SRC)
};
static uint32_t bg_op_chroma[] = {
PPP_ARRAY1(CHROMA_SAMP, BG)
};
static void rotate_dst_addr_x(struct mdp_blit_req *req, struct mdp_regs *regs)
{
regs->dst0 += (req->dst_rect.w -
min((uint32_t)16, req->dst_rect.w)) * regs->dst_bpp;
regs->dst1 += (req->dst_rect.w -
min((uint32_t)16, req->dst_rect.w)) * regs->dst_bpp;
}
static void rotate_dst_addr_y(struct mdp_blit_req *req, struct mdp_regs *regs)
{
regs->dst0 += (req->dst_rect.h -
min((uint32_t)16, req->dst_rect.h)) *
regs->dst_ystride;
regs->dst1 += (req->dst_rect.h -
min((uint32_t)16, req->dst_rect.h)) *
regs->dst_ystride;
}
static void blit_rotate(struct mdp_blit_req *req,
struct mdp_regs *regs)
{
if (req->flags == MDP_ROT_NOP)
return;
regs->op |= PPP_OP_ROT_ON;
if ((req->flags & MDP_ROT_90 || req->flags & MDP_FLIP_LR) &&
!(req->flags & MDP_ROT_90 && req->flags & MDP_FLIP_LR))
rotate_dst_addr_x(req, regs);
if (req->flags & MDP_ROT_90)
regs->op |= PPP_OP_ROT_90;
if (req->flags & MDP_FLIP_UD) {
regs->op |= PPP_OP_FLIP_UD;
rotate_dst_addr_y(req, regs);
}
if (req->flags & MDP_FLIP_LR)
regs->op |= PPP_OP_FLIP_LR;
}
static void blit_convert(struct mdp_blit_req *req, struct mdp_regs *regs)
{
if (req->src.format == req->dst.format)
return;
if (IS_RGB(req->src.format) && IS_YCRCB(req->dst.format)) {
regs->op |= PPP_OP_CONVERT_RGB2YCBCR | PPP_OP_CONVERT_ON;
} else if (IS_YCRCB(req->src.format) && IS_RGB(req->dst.format)) {
regs->op |= PPP_OP_CONVERT_YCBCR2RGB | PPP_OP_CONVERT_ON;
if (req->dst.format == MDP_RGB_565)
regs->op |= PPP_OP_CONVERT_MATRIX_SECONDARY;
}
}
#define GET_BIT_RANGE(value, high, low) \
(((1 << (high - low + 1)) - 1) & (value >> low))
static uint32_t transp_convert(struct mdp_blit_req *req)
{
uint32_t transp = 0;
if (req->src.format == MDP_RGB_565) {
/* pad each value to 8 bits by copying the high bits into the
* low end, convert RGB to RBG by switching low 2 components */
transp |= ((GET_BIT_RANGE(req->transp_mask, 15, 11) << 3) |
(GET_BIT_RANGE(req->transp_mask, 15, 13))) << 16;
transp |= ((GET_BIT_RANGE(req->transp_mask, 4, 0) << 3) |
(GET_BIT_RANGE(req->transp_mask, 4, 2))) << 8;
transp |= (GET_BIT_RANGE(req->transp_mask, 10, 5) << 2) |
(GET_BIT_RANGE(req->transp_mask, 10, 9));
} else {
/* convert RGB to RBG */
transp |= (GET_BIT_RANGE(req->transp_mask, 15, 8)) |
(GET_BIT_RANGE(req->transp_mask, 23, 16) << 16) |
(GET_BIT_RANGE(req->transp_mask, 7, 0) << 8);
}
return transp;
}
#undef GET_BIT_RANGE
static void blit_blend(struct mdp_blit_req *req, struct mdp_regs *regs)
{
/* TRANSP BLEND */
if (req->transp_mask != MDP_TRANSP_NOP) {
req->transp_mask = transp_convert(req);
if (req->alpha != MDP_ALPHA_NOP) {
/* use blended transparancy mode
* pixel = (src == transp) ? dst : blend
* blend is combo of blend_eq_sel and
* blend_alpha_sel */
regs->op |= PPP_OP_ROT_ON | PPP_OP_BLEND_ON |
PPP_OP_BLEND_ALPHA_BLEND_NORMAL |
PPP_OP_BLEND_CONSTANT_ALPHA |
PPP_BLEND_ALPHA_TRANSP;
} else {
/* simple transparancy mode
* pixel = (src == transp) ? dst : src */
regs->op |= PPP_OP_ROT_ON | PPP_OP_BLEND_ON |
PPP_OP_BLEND_SRCPIXEL_TRANSP;
}
}
req->alpha &= 0xff;
/* ALPHA BLEND */
if (HAS_ALPHA(req->src.format)) {
regs->op |= PPP_OP_ROT_ON | PPP_OP_BLEND_ON |
PPP_OP_BLEND_SRCPIXEL_ALPHA;
} else if (req->alpha < MDP_ALPHA_NOP) {
/* just blend by alpha */
regs->op |= PPP_OP_ROT_ON | PPP_OP_BLEND_ON |
PPP_OP_BLEND_ALPHA_BLEND_NORMAL |
PPP_OP_BLEND_CONSTANT_ALPHA;
}
regs->op |= bg_op_chroma[req->dst.format];
}
#define ONE_HALF (1LL << 32)
#define ONE (1LL << 33)
#define TWO (2LL << 33)
#define THREE (3LL << 33)
#define FRAC_MASK (ONE - 1)
#define INT_MASK (~FRAC_MASK)
static int scale_params(uint32_t dim_in, uint32_t dim_out, uint32_t origin,
uint32_t *phase_init, uint32_t *phase_step)
{
/* to improve precicsion calculations are done in U31.33 and converted
* to U3.29 at the end */
int64_t k1, k2, k3, k4, tmp;
uint64_t n, d, os, os_p, od, od_p, oreq;
unsigned rpa = 0;
int64_t ip64, delta;
if (dim_out % 3 == 0)
rpa = !(dim_in % (dim_out / 3));
n = ((uint64_t)dim_out) << 34;
d = dim_in;
if (!d)
return -1;
do_div(n, d);
k3 = (n + 1) >> 1;
if ((k3 >> 4) < (1LL << 27) || (k3 >> 4) > (1LL << 31)) {
DLOG("crap bad scale\n");
return -1;
}
n = ((uint64_t)dim_in) << 34;
d = (uint64_t)dim_out;
if (!d)
return -1;
do_div(n, d);
k1 = (n + 1) >> 1;
k2 = (k1 - ONE) >> 1;
*phase_init = (int)(k2 >> 4);
k4 = (k3 - ONE) >> 1;
if (rpa) {
os = ((uint64_t)origin << 33) - ONE_HALF;
tmp = (dim_out * os) + ONE_HALF;
if (!dim_in)
return -1;
do_div(tmp, dim_in);
od = tmp - ONE_HALF;
} else {
os = ((uint64_t)origin << 1) - 1;
od = (((k3 * os) >> 1) + k4);
}
od_p = od & INT_MASK;
if (od_p != od)
od_p += ONE;
if (rpa) {
tmp = (dim_in * od_p) + ONE_HALF;
if (!dim_in)
return -1;
do_div(tmp, dim_in);
os_p = tmp - ONE_HALF;
} else {
os_p = ((k1 * (od_p >> 33)) + k2);
}
oreq = (os_p & INT_MASK) - ONE;
ip64 = os_p - oreq;
delta = ((int64_t)(origin) << 33) - oreq;
ip64 -= delta;
/* limit to valid range before the left shift */
delta = (ip64 & (1LL << 63)) ? 4 : -4;
delta <<= 33;
while (abs((int)(ip64 >> 33)) > 4)
ip64 += delta;
*phase_init = (int)(ip64 >> 4);
*phase_step = (uint32_t)(k1 >> 4);
return 0;
}
static void load_scale_table(const struct mdp_info *mdp,
struct mdp_table_entry *table, int len)
{
int i;
for (i = 0; i < len; i++)
mdp_writel(mdp, table[i].val, table[i].reg);
}
enum {
IMG_LEFT,
IMG_RIGHT,
IMG_TOP,
IMG_BOTTOM,
};
static void get_edge_info(uint32_t src, uint32_t src_coord, uint32_t dst,
uint32_t *interp1, uint32_t *interp2,
uint32_t *repeat1, uint32_t *repeat2) {
if (src > 3 * dst) {
*interp1 = 0;
*interp2 = src - 1;
*repeat1 = 0;
*repeat2 = 0;
} else if (src == 3 * dst) {
*interp1 = 0;
*interp2 = src;
*repeat1 = 0;
*repeat2 = 1;
} else if (src > dst && src < 3 * dst) {
*interp1 = -1;
*interp2 = src;
*repeat1 = 1;
*repeat2 = 1;
} else if (src == dst) {
*interp1 = -1;
*interp2 = src + 1;
*repeat1 = 1;
*repeat2 = 2;
} else {
*interp1 = -2;
*interp2 = src + 1;
*repeat1 = 2;
*repeat2 = 2;
}
*interp1 += src_coord;
*interp2 += src_coord;
}
static int get_edge_cond(struct mdp_blit_req *req, struct mdp_regs *regs)
{
int32_t luma_interp[4];
int32_t luma_repeat[4];
int32_t chroma_interp[4];
int32_t chroma_bound[4];
int32_t chroma_repeat[4];
uint32_t dst_w, dst_h;
memset(&luma_interp, 0, sizeof(int32_t) * 4);
memset(&luma_repeat, 0, sizeof(int32_t) * 4);
memset(&chroma_interp, 0, sizeof(int32_t) * 4);
memset(&chroma_bound, 0, sizeof(int32_t) * 4);
memset(&chroma_repeat, 0, sizeof(int32_t) * 4);
regs->edge = 0;
if (req->flags & MDP_ROT_90) {
dst_w = req->dst_rect.h;
dst_h = req->dst_rect.w;
} else {
dst_w = req->dst_rect.w;
dst_h = req->dst_rect.h;
}
if (regs->op & (PPP_OP_SCALE_Y_ON | PPP_OP_SCALE_X_ON)) {
get_edge_info(req->src_rect.h, req->src_rect.y, dst_h,
&luma_interp[IMG_TOP], &luma_interp[IMG_BOTTOM],
&luma_repeat[IMG_TOP], &luma_repeat[IMG_BOTTOM]);
get_edge_info(req->src_rect.w, req->src_rect.x, dst_w,
&luma_interp[IMG_LEFT], &luma_interp[IMG_RIGHT],
&luma_repeat[IMG_LEFT], &luma_repeat[IMG_RIGHT]);
} else {
luma_interp[IMG_LEFT] = req->src_rect.x;
luma_interp[IMG_RIGHT] = req->src_rect.x + req->src_rect.w - 1;
luma_interp[IMG_TOP] = req->src_rect.y;
luma_interp[IMG_BOTTOM] = req->src_rect.y + req->src_rect.h - 1;
luma_repeat[IMG_LEFT] = 0;
luma_repeat[IMG_TOP] = 0;
luma_repeat[IMG_RIGHT] = 0;
luma_repeat[IMG_BOTTOM] = 0;
}
chroma_interp[IMG_LEFT] = luma_interp[IMG_LEFT];
chroma_interp[IMG_RIGHT] = luma_interp[IMG_RIGHT];
chroma_interp[IMG_TOP] = luma_interp[IMG_TOP];
chroma_interp[IMG_BOTTOM] = luma_interp[IMG_BOTTOM];
chroma_bound[IMG_LEFT] = req->src_rect.x;
chroma_bound[IMG_RIGHT] = req->src_rect.x + req->src_rect.w - 1;
chroma_bound[IMG_TOP] = req->src_rect.y;
chroma_bound[IMG_BOTTOM] = req->src_rect.y + req->src_rect.h - 1;
if (IS_YCRCB(req->src.format)) {
chroma_interp[IMG_LEFT] = chroma_interp[IMG_LEFT] >> 1;
chroma_interp[IMG_RIGHT] = (chroma_interp[IMG_RIGHT] + 1) >> 1;
chroma_bound[IMG_LEFT] = chroma_bound[IMG_LEFT] >> 1;
chroma_bound[IMG_RIGHT] = chroma_bound[IMG_RIGHT] >> 1;
}
if (req->src.format == MDP_Y_CBCR_H2V2 ||
req->src.format == MDP_Y_CRCB_H2V2) {
chroma_interp[IMG_TOP] = (chroma_interp[IMG_TOP] - 1) >> 1;
chroma_interp[IMG_BOTTOM] = (chroma_interp[IMG_BOTTOM] + 1)
>> 1;
chroma_bound[IMG_TOP] = (chroma_bound[IMG_TOP] + 1) >> 1;
chroma_bound[IMG_BOTTOM] = chroma_bound[IMG_BOTTOM] >> 1;
}
chroma_repeat[IMG_LEFT] = chroma_bound[IMG_LEFT] -
chroma_interp[IMG_LEFT];
chroma_repeat[IMG_RIGHT] = chroma_interp[IMG_RIGHT] -
chroma_bound[IMG_RIGHT];
chroma_repeat[IMG_TOP] = chroma_bound[IMG_TOP] -
chroma_interp[IMG_TOP];
chroma_repeat[IMG_BOTTOM] = chroma_interp[IMG_BOTTOM] -
chroma_bound[IMG_BOTTOM];
if (chroma_repeat[IMG_LEFT] < 0 || chroma_repeat[IMG_LEFT] > 3 ||
chroma_repeat[IMG_RIGHT] < 0 || chroma_repeat[IMG_RIGHT] > 3 ||
chroma_repeat[IMG_TOP] < 0 || chroma_repeat[IMG_TOP] > 3 ||
chroma_repeat[IMG_BOTTOM] < 0 || chroma_repeat[IMG_BOTTOM] > 3 ||
luma_repeat[IMG_LEFT] < 0 || luma_repeat[IMG_LEFT] > 3 ||
luma_repeat[IMG_RIGHT] < 0 || luma_repeat[IMG_RIGHT] > 3 ||
luma_repeat[IMG_TOP] < 0 || luma_repeat[IMG_TOP] > 3 ||
luma_repeat[IMG_BOTTOM] < 0 || luma_repeat[IMG_BOTTOM] > 3)
return -1;
regs->edge |= (chroma_repeat[IMG_LEFT] & 3) << MDP_LEFT_CHROMA;
regs->edge |= (chroma_repeat[IMG_RIGHT] & 3) << MDP_RIGHT_CHROMA;
regs->edge |= (chroma_repeat[IMG_TOP] & 3) << MDP_TOP_CHROMA;
regs->edge |= (chroma_repeat[IMG_BOTTOM] & 3) << MDP_BOTTOM_CHROMA;
regs->edge |= (luma_repeat[IMG_LEFT] & 3) << MDP_LEFT_LUMA;
regs->edge |= (luma_repeat[IMG_RIGHT] & 3) << MDP_RIGHT_LUMA;
regs->edge |= (luma_repeat[IMG_TOP] & 3) << MDP_TOP_LUMA;
regs->edge |= (luma_repeat[IMG_BOTTOM] & 3) << MDP_BOTTOM_LUMA;
return 0;
}
static int blit_scale(const struct mdp_info *mdp, struct mdp_blit_req *req,
struct mdp_regs *regs)
{
uint32_t phase_init_x, phase_init_y, phase_step_x, phase_step_y;
uint32_t scale_factor_x, scale_factor_y;
uint32_t downscale;
uint32_t dst_w, dst_h;
if (req->flags & MDP_ROT_90) {
dst_w = req->dst_rect.h;
dst_h = req->dst_rect.w;
} else {
dst_w = req->dst_rect.w;
dst_h = req->dst_rect.h;
}
if ((req->src_rect.w == dst_w) && (req->src_rect.h == dst_h) &&
!(req->flags & MDP_BLUR)) {
regs->phasex_init = 0;
regs->phasey_init = 0;
regs->phasex_step = 0;
regs->phasey_step = 0;
return 0;
}
if (scale_params(req->src_rect.w, dst_w, 1, &phase_init_x,
&phase_step_x) ||
scale_params(req->src_rect.h, dst_h, 1, &phase_init_y,
&phase_step_y))
return -1;
scale_factor_x = (dst_w * 10) / req->src_rect.w;
scale_factor_y = (dst_h * 10) / req->src_rect.h;
if (scale_factor_x > 8)
downscale = MDP_DOWNSCALE_PT8TO1;
else if (scale_factor_x > 6)
downscale = MDP_DOWNSCALE_PT6TOPT8;
else if (scale_factor_x > 4)
downscale = MDP_DOWNSCALE_PT4TOPT6;
else
downscale = MDP_DOWNSCALE_PT2TOPT4;
if (downscale != downscale_x_table) {
load_scale_table(mdp, mdp_downscale_x_table[downscale], 64);
downscale_x_table = downscale;
}
if (scale_factor_y > 8)
downscale = MDP_DOWNSCALE_PT8TO1;
else if (scale_factor_y > 6)
downscale = MDP_DOWNSCALE_PT6TOPT8;
else if (scale_factor_y > 4)
downscale = MDP_DOWNSCALE_PT4TOPT6;
else
downscale = MDP_DOWNSCALE_PT2TOPT4;
if (downscale != downscale_y_table) {
load_scale_table(mdp, mdp_downscale_y_table[downscale], 64);
downscale_y_table = downscale;
}
regs->phasex_init = phase_init_x;
regs->phasey_init = phase_init_y;
regs->phasex_step = phase_step_x;
regs->phasey_step = phase_step_y;
regs->op |= (PPP_OP_SCALE_Y_ON | PPP_OP_SCALE_X_ON);
return 0;
}
static void blit_blur(const struct mdp_info *mdp, struct mdp_blit_req *req,
struct mdp_regs *regs)
{
if (!(req->flags & MDP_BLUR))
return;
if (!(downscale_x_table == MDP_DOWNSCALE_BLUR &&
downscale_y_table == MDP_DOWNSCALE_BLUR)) {
load_scale_table(mdp, mdp_gaussian_blur_table, 128);
downscale_x_table = MDP_DOWNSCALE_BLUR;
downscale_y_table = MDP_DOWNSCALE_BLUR;
}
regs->op |= (PPP_OP_SCALE_Y_ON | PPP_OP_SCALE_X_ON);
}
#define IMG_LEN(rect_h, w, rect_w, bpp) (((rect_h) * w) * bpp)
#define Y_TO_CRCB_RATIO(format) \
((format == MDP_Y_CBCR_H2V2 || format == MDP_Y_CRCB_H2V2) ? 2 :\
(format == MDP_Y_CBCR_H2V1 || format == MDP_Y_CRCB_H2V1) ? 1 : 1)
static void get_len(struct mdp_img *img, struct mdp_rect *rect, uint32_t bpp,
uint32_t *len0, uint32_t *len1)
{
*len0 = IMG_LEN(rect->h, img->width, rect->w, bpp);
if (IS_PSEUDOPLNR(img->format))
*len1 = *len0/Y_TO_CRCB_RATIO(img->format);
else
*len1 = 0;
}
static int valid_src_dst(unsigned long src_start, unsigned long src_len,
unsigned long dst_start, unsigned long dst_len,
struct mdp_blit_req *req, struct mdp_regs *regs)
{
unsigned long src_min_ok = src_start;
unsigned long src_max_ok = src_start + src_len;
unsigned long dst_min_ok = dst_start;
unsigned long dst_max_ok = dst_start + dst_len;
uint32_t src0_len, src1_len, dst0_len, dst1_len;
get_len(&req->src, &req->src_rect, regs->src_bpp, &src0_len,
&src1_len);
get_len(&req->dst, &req->dst_rect, regs->dst_bpp, &dst0_len,
&dst1_len);
if (regs->src0 < src_min_ok || regs->src0 > src_max_ok ||
regs->src0 + src0_len > src_max_ok) {
DLOG("invalid_src %x %x %lx %lx\n", regs->src0,
src0_len, src_min_ok, src_max_ok);
return 0;
}
if (regs->src_cfg & PPP_SRC_PLANE_PSEUDOPLNR) {
if (regs->src1 < src_min_ok || regs->src1 > src_max_ok ||
regs->src1 + src1_len > src_max_ok) {
DLOG("invalid_src1");
return 0;
}
}
if (regs->dst0 < dst_min_ok || regs->dst0 > dst_max_ok ||
regs->dst0 + dst0_len > dst_max_ok) {
DLOG("invalid_dst");
return 0;
}
if (regs->dst_cfg & PPP_SRC_PLANE_PSEUDOPLNR) {
if (regs->dst1 < dst_min_ok || regs->dst1 > dst_max_ok ||
regs->dst1 + dst1_len > dst_max_ok) {
DLOG("invalid_dst1");
return 0;
}
}
return 1;
}
static void flush_imgs(struct mdp_blit_req *req, struct mdp_regs *regs,
struct file *src_file, struct file *dst_file)
{
#ifdef CONFIG_ANDROID_PMEM
uint32_t src0_len, src1_len, dst0_len, dst1_len;
/* flush src images to memory before dma to mdp */
get_len(&req->src, &req->src_rect, regs->src_bpp, &src0_len,
&src1_len);
flush_pmem_file(src_file, req->src.offset, src0_len);
if (IS_PSEUDOPLNR(req->src.format))
flush_pmem_file(src_file, req->src.offset + src0_len,
src1_len);
/* flush dst images */
get_len(&req->dst, &req->dst_rect, regs->dst_bpp, &dst0_len,
&dst1_len);
flush_pmem_file(dst_file, req->dst.offset, dst0_len);
if (IS_PSEUDOPLNR(req->dst.format))
flush_pmem_file(dst_file, req->dst.offset + dst0_len,
dst1_len);
#endif
}
static void get_chroma_addr(struct mdp_img *img, struct mdp_rect *rect,
uint32_t base, uint32_t bpp, uint32_t cfg,
uint32_t *addr, uint32_t *ystride)
{
uint32_t compress_v = Y_TO_CRCB_RATIO(img->format);
uint32_t compress_h = 2;
uint32_t offset;
if (IS_PSEUDOPLNR(img->format)) {
offset = (rect->x / compress_h) * compress_h;
offset += rect->y == 0 ? 0 :
((rect->y + 1) / compress_v) * img->width;
*addr = base + (img->width * img->height * bpp);
*addr += offset * bpp;
*ystride |= *ystride << 16;
} else {
*addr = 0;
}
}
static int send_blit(const struct mdp_info *mdp, struct mdp_blit_req *req,
struct mdp_regs *regs, struct file *src_file,
struct file *dst_file)
{
mdp_writel(mdp, 1, 0x060);
mdp_writel(mdp, regs->src_rect, PPP_ADDR_SRC_ROI);
mdp_writel(mdp, regs->src0, PPP_ADDR_SRC0);
mdp_writel(mdp, regs->src1, PPP_ADDR_SRC1);
mdp_writel(mdp, regs->src_ystride, PPP_ADDR_SRC_YSTRIDE);
mdp_writel(mdp, regs->src_cfg, PPP_ADDR_SRC_CFG);
mdp_writel(mdp, regs->src_pack, PPP_ADDR_SRC_PACK_PATTERN);
mdp_writel(mdp, regs->op, PPP_ADDR_OPERATION);
mdp_writel(mdp, regs->phasex_init, PPP_ADDR_PHASEX_INIT);
mdp_writel(mdp, regs->phasey_init, PPP_ADDR_PHASEY_INIT);
mdp_writel(mdp, regs->phasex_step, PPP_ADDR_PHASEX_STEP);
mdp_writel(mdp, regs->phasey_step, PPP_ADDR_PHASEY_STEP);
mdp_writel(mdp, (req->alpha << 24) | (req->transp_mask & 0xffffff),
PPP_ADDR_ALPHA_TRANSP);
mdp_writel(mdp, regs->dst_cfg, PPP_ADDR_DST_CFG);
mdp_writel(mdp, regs->dst_pack, PPP_ADDR_DST_PACK_PATTERN);
mdp_writel(mdp, regs->dst_rect, PPP_ADDR_DST_ROI);
mdp_writel(mdp, regs->dst0, PPP_ADDR_DST0);
mdp_writel(mdp, regs->dst1, PPP_ADDR_DST1);
mdp_writel(mdp, regs->dst_ystride, PPP_ADDR_DST_YSTRIDE);
mdp_writel(mdp, regs->edge, PPP_ADDR_EDGE);
if (regs->op & PPP_OP_BLEND_ON) {
mdp_writel(mdp, regs->dst0, PPP_ADDR_BG0);
mdp_writel(mdp, regs->dst1, PPP_ADDR_BG1);
mdp_writel(mdp, regs->dst_ystride, PPP_ADDR_BG_YSTRIDE);
mdp_writel(mdp, src_img_cfg[req->dst.format], PPP_ADDR_BG_CFG);
mdp_writel(mdp, pack_pattern[req->dst.format],
PPP_ADDR_BG_PACK_PATTERN);
}
flush_imgs(req, regs, src_file, dst_file);
mdp_writel(mdp, 0x1000, MDP_DISPLAY0_START);
return 0;
}
int mdp_ppp_blit(const struct mdp_info *mdp, struct mdp_blit_req *req,
struct file *src_file, unsigned long src_start, unsigned long src_len,
struct file *dst_file, unsigned long dst_start, unsigned long dst_len)
{
struct mdp_regs regs = {0};
if (unlikely(req->src.format >= MDP_IMGTYPE_LIMIT ||
req->dst.format >= MDP_IMGTYPE_LIMIT)) {
printk(KERN_ERR "mpd_ppp: img is of wrong format\n");
return -EINVAL;
}
if (unlikely(req->src_rect.x > req->src.width ||
req->src_rect.y > req->src.height ||
req->dst_rect.x > req->dst.width ||
req->dst_rect.y > req->dst.height)) {
printk(KERN_ERR "mpd_ppp: img rect is outside of img!\n");
return -EINVAL;
}
/* set the src image configuration */
regs.src_cfg = src_img_cfg[req->src.format];
regs.src_cfg |= (req->src_rect.x & 0x1) ? PPP_SRC_BPP_ROI_ODD_X : 0;
regs.src_cfg |= (req->src_rect.y & 0x1) ? PPP_SRC_BPP_ROI_ODD_Y : 0;
regs.src_rect = (req->src_rect.h << 16) | req->src_rect.w;
regs.src_pack = pack_pattern[req->src.format];
/* set the dest image configuration */
regs.dst_cfg = dst_img_cfg[req->dst.format] | PPP_DST_OUT_SEL_AXI;
regs.dst_rect = (req->dst_rect.h << 16) | req->dst_rect.w;
regs.dst_pack = pack_pattern[req->dst.format];
/* set src, bpp, start pixel and ystride */
regs.src_bpp = bytes_per_pixel[req->src.format];
regs.src0 = src_start + req->src.offset;
regs.src_ystride = req->src.width * regs.src_bpp;
get_chroma_addr(&req->src, &req->src_rect, regs.src0, regs.src_bpp,
regs.src_cfg, &regs.src1, &regs.src_ystride);
regs.src0 += (req->src_rect.x + (req->src_rect.y * req->src.width)) *
regs.src_bpp;
/* set dst, bpp, start pixel and ystride */
regs.dst_bpp = bytes_per_pixel[req->dst.format];
regs.dst0 = dst_start + req->dst.offset;
regs.dst_ystride = req->dst.width * regs.dst_bpp;
get_chroma_addr(&req->dst, &req->dst_rect, regs.dst0, regs.dst_bpp,
regs.dst_cfg, &regs.dst1, &regs.dst_ystride);
regs.dst0 += (req->dst_rect.x + (req->dst_rect.y * req->dst.width)) *
regs.dst_bpp;
if (!valid_src_dst(src_start, src_len, dst_start, dst_len, req,
&regs)) {
printk(KERN_ERR "mpd_ppp: final src or dst location is "
"invalid, are you trying to make an image too large "
"or to place it outside the screen?\n");
return -EINVAL;
}
/* set up operation register */
regs.op = 0;
blit_rotate(req, &regs);
blit_convert(req, &regs);
if (req->flags & MDP_DITHER)
regs.op |= PPP_OP_DITHER_EN;
blit_blend(req, &regs);
if (blit_scale(mdp, req, &regs)) {
printk(KERN_ERR "mpd_ppp: error computing scale for img.\n");
return -EINVAL;
}
blit_blur(mdp, req, &regs);
regs.op |= dst_op_chroma[req->dst.format] |
src_op_chroma[req->src.format];
/* if the image is YCRYCB, the x and w must be even */
if (unlikely(req->src.format == MDP_YCRYCB_H2V1)) {
req->src_rect.x = req->src_rect.x & (~0x1);
req->src_rect.w = req->src_rect.w & (~0x1);
req->dst_rect.x = req->dst_rect.x & (~0x1);
req->dst_rect.w = req->dst_rect.w & (~0x1);
}
if (get_edge_cond(req, &regs))
return -EINVAL;
send_blit(mdp, req, &regs, src_file, dst_file);
return 0;
}

766
drivers/video/msm/mdp_scale_tables.c Normal file
View File

@@ -0,0 +1,766 @@
/* drivers/video/msm_fb/mdp_scale_tables.c
*
* Copyright (C) 2007 QUALCOMM Incorporated
* Copyright (C) 2007 Google Incorporated
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "mdp_scale_tables.h"
#include "mdp_hw.h"
struct mdp_table_entry mdp_upscale_table[] = {
{ 0x5fffc, 0x0 },
{ 0x50200, 0x7fc00000 },
{ 0x5fffc, 0xff80000d },
{ 0x50204, 0x7ec003f9 },
{ 0x5fffc, 0xfec0001c },
{ 0x50208, 0x7d4003f3 },
{ 0x5fffc, 0xfe40002b },
{ 0x5020c, 0x7b8003ed },
{ 0x5fffc, 0xfd80003c },
{ 0x50210, 0x794003e8 },
{ 0x5fffc, 0xfcc0004d },
{ 0x50214, 0x76c003e4 },
{ 0x5fffc, 0xfc40005f },
{ 0x50218, 0x73c003e0 },
{ 0x5fffc, 0xfb800071 },
{ 0x5021c, 0x708003de },
{ 0x5fffc, 0xfac00085 },
{ 0x50220, 0x6d0003db },
{ 0x5fffc, 0xfa000098 },
{ 0x50224, 0x698003d9 },
{ 0x5fffc, 0xf98000ac },
{ 0x50228, 0x654003d8 },
{ 0x5fffc, 0xf8c000c1 },
{ 0x5022c, 0x610003d7 },
{ 0x5fffc, 0xf84000d5 },
{ 0x50230, 0x5c8003d7 },
{ 0x5fffc, 0xf7c000e9 },
{ 0x50234, 0x580003d7 },
{ 0x5fffc, 0xf74000fd },
{ 0x50238, 0x534003d8 },
{ 0x5fffc, 0xf6c00112 },
{ 0x5023c, 0x4e8003d8 },
{ 0x5fffc, 0xf6800126 },
{ 0x50240, 0x494003da },
{ 0x5fffc, 0xf600013a },
{ 0x50244, 0x448003db },
{ 0x5fffc, 0xf600014d },
{ 0x50248, 0x3f4003dd },
{ 0x5fffc, 0xf5c00160 },
{ 0x5024c, 0x3a4003df },
{ 0x5fffc, 0xf5c00172 },
{ 0x50250, 0x354003e1 },
{ 0x5fffc, 0xf5c00184 },
{ 0x50254, 0x304003e3 },
{ 0x5fffc, 0xf6000195 },
{ 0x50258, 0x2b0003e6 },
{ 0x5fffc, 0xf64001a6 },
{ 0x5025c, 0x260003e8 },
{ 0x5fffc, 0xf6c001b4 },
{ 0x50260, 0x214003eb },
{ 0x5fffc, 0xf78001c2 },
{ 0x50264, 0x1c4003ee },
{ 0x5fffc, 0xf80001cf },
{ 0x50268, 0x17c003f1 },
{ 0x5fffc, 0xf90001db },
{ 0x5026c, 0x134003f3 },
{ 0x5fffc, 0xfa0001e5 },
{ 0x50270, 0xf0003f6 },
{ 0x5fffc, 0xfb4001ee },
{ 0x50274, 0xac003f9 },
{ 0x5fffc, 0xfcc001f5 },
{ 0x50278, 0x70003fb },
{ 0x5fffc, 0xfe4001fb },
{ 0x5027c, 0x34003fe },
};
static struct mdp_table_entry mdp_downscale_x_table_PT2TOPT4[] = {
{ 0x5fffc, 0x740008c },
{ 0x50280, 0x33800088 },
{ 0x5fffc, 0x800008e },
{ 0x50284, 0x33400084 },
{ 0x5fffc, 0x8400092 },
{ 0x50288, 0x33000080 },
{ 0x5fffc, 0x9000094 },
{ 0x5028c, 0x3300007b },
{ 0x5fffc, 0x9c00098 },
{ 0x50290, 0x32400077 },
{ 0x5fffc, 0xa40009b },
{ 0x50294, 0x32000073 },
{ 0x5fffc, 0xb00009d },
{ 0x50298, 0x31c0006f },
{ 0x5fffc, 0xbc000a0 },
{ 0x5029c, 0x3140006b },
{ 0x5fffc, 0xc8000a2 },
{ 0x502a0, 0x31000067 },
{ 0x5fffc, 0xd8000a5 },
{ 0x502a4, 0x30800062 },
{ 0x5fffc, 0xe4000a8 },
{ 0x502a8, 0x2fc0005f },
{ 0x5fffc, 0xec000aa },
{ 0x502ac, 0x2fc0005b },
{ 0x5fffc, 0xf8000ad },
{ 0x502b0, 0x2f400057 },
{ 0x5fffc, 0x108000b0 },
{ 0x502b4, 0x2e400054 },
{ 0x5fffc, 0x114000b2 },
{ 0x502b8, 0x2e000050 },
{ 0x5fffc, 0x124000b4 },
{ 0x502bc, 0x2d80004c },
{ 0x5fffc, 0x130000b6 },
{ 0x502c0, 0x2d000049 },
{ 0x5fffc, 0x140000b8 },
{ 0x502c4, 0x2c800045 },
{ 0x5fffc, 0x150000b9 },
{ 0x502c8, 0x2c000042 },
{ 0x5fffc, 0x15c000bd },
{ 0x502cc, 0x2b40003e },
{ 0x5fffc, 0x16c000bf },
{ 0x502d0, 0x2a80003b },
{ 0x5fffc, 0x17c000bf },
{ 0x502d4, 0x2a000039 },
{ 0x5fffc, 0x188000c2 },
{ 0x502d8, 0x29400036 },
{ 0x5fffc, 0x19c000c4 },
{ 0x502dc, 0x28800032 },
{ 0x5fffc, 0x1ac000c5 },
{ 0x502e0, 0x2800002f },
{ 0x5fffc, 0x1bc000c7 },
{ 0x502e4, 0x2740002c },
{ 0x5fffc, 0x1cc000c8 },
{ 0x502e8, 0x26c00029 },
{ 0x5fffc, 0x1dc000c9 },
{ 0x502ec, 0x26000027 },
{ 0x5fffc, 0x1ec000cc },
{ 0x502f0, 0x25000024 },
{ 0x5fffc, 0x200000cc },
{ 0x502f4, 0x24800021 },
{ 0x5fffc, 0x210000cd },
{ 0x502f8, 0x23800020 },
{ 0x5fffc, 0x220000ce },
{ 0x502fc, 0x2300001d },
};
static struct mdp_table_entry mdp_downscale_x_table_PT4TOPT6[] = {
{ 0x5fffc, 0x740008c },
{ 0x50280, 0x33800088 },
{ 0x5fffc, 0x800008e },
{ 0x50284, 0x33400084 },
{ 0x5fffc, 0x8400092 },
{ 0x50288, 0x33000080 },
{ 0x5fffc, 0x9000094 },
{ 0x5028c, 0x3300007b },
{ 0x5fffc, 0x9c00098 },
{ 0x50290, 0x32400077 },
{ 0x5fffc, 0xa40009b },
{ 0x50294, 0x32000073 },
{ 0x5fffc, 0xb00009d },
{ 0x50298, 0x31c0006f },
{ 0x5fffc, 0xbc000a0 },
{ 0x5029c, 0x3140006b },
{ 0x5fffc, 0xc8000a2 },
{ 0x502a0, 0x31000067 },
{ 0x5fffc, 0xd8000a5 },
{ 0x502a4, 0x30800062 },
{ 0x5fffc, 0xe4000a8 },
{ 0x502a8, 0x2fc0005f },
{ 0x5fffc, 0xec000aa },
{ 0x502ac, 0x2fc0005b },
{ 0x5fffc, 0xf8000ad },
{ 0x502b0, 0x2f400057 },
{ 0x5fffc, 0x108000b0 },
{ 0x502b4, 0x2e400054 },
{ 0x5fffc, 0x114000b2 },
{ 0x502b8, 0x2e000050 },
{ 0x5fffc, 0x124000b4 },
{ 0x502bc, 0x2d80004c },
{ 0x5fffc, 0x130000b6 },
{ 0x502c0, 0x2d000049 },
{ 0x5fffc, 0x140000b8 },
{ 0x502c4, 0x2c800045 },
{ 0x5fffc, 0x150000b9 },
{ 0x502c8, 0x2c000042 },
{ 0x5fffc, 0x15c000bd },
{ 0x502cc, 0x2b40003e },
{ 0x5fffc, 0x16c000bf },
{ 0x502d0, 0x2a80003b },
{ 0x5fffc, 0x17c000bf },
{ 0x502d4, 0x2a000039 },
{ 0x5fffc, 0x188000c2 },
{ 0x502d8, 0x29400036 },
{ 0x5fffc, 0x19c000c4 },
{ 0x502dc, 0x28800032 },
{ 0x5fffc, 0x1ac000c5 },
{ 0x502e0, 0x2800002f },
{ 0x5fffc, 0x1bc000c7 },
{ 0x502e4, 0x2740002c },
{ 0x5fffc, 0x1cc000c8 },
{ 0x502e8, 0x26c00029 },
{ 0x5fffc, 0x1dc000c9 },
{ 0x502ec, 0x26000027 },
{ 0x5fffc, 0x1ec000cc },
{ 0x502f0, 0x25000024 },
{ 0x5fffc, 0x200000cc },
{ 0x502f4, 0x24800021 },
{ 0x5fffc, 0x210000cd },
{ 0x502f8, 0x23800020 },
{ 0x5fffc, 0x220000ce },
{ 0x502fc, 0x2300001d },
};
static struct mdp_table_entry mdp_downscale_x_table_PT6TOPT8[] = {
{ 0x5fffc, 0xfe000070 },
{ 0x50280, 0x4bc00068 },
{ 0x5fffc, 0xfe000078 },
{ 0x50284, 0x4bc00060 },
{ 0x5fffc, 0xfe000080 },
{ 0x50288, 0x4b800059 },
{ 0x5fffc, 0xfe000089 },
{ 0x5028c, 0x4b000052 },
{ 0x5fffc, 0xfe400091 },
{ 0x50290, 0x4a80004b },
{ 0x5fffc, 0xfe40009a },
{ 0x50294, 0x4a000044 },
{ 0x5fffc, 0xfe8000a3 },
{ 0x50298, 0x4940003d },
{ 0x5fffc, 0xfec000ac },
{ 0x5029c, 0x48400037 },
{ 0x5fffc, 0xff0000b4 },
{ 0x502a0, 0x47800031 },
{ 0x5fffc, 0xff8000bd },
{ 0x502a4, 0x4640002b },
{ 0x5fffc, 0xc5 },
{ 0x502a8, 0x45000026 },
{ 0x5fffc, 0x8000ce },
{ 0x502ac, 0x43800021 },
{ 0x5fffc, 0x10000d6 },
{ 0x502b0, 0x4240001c },
{ 0x5fffc, 0x18000df },
{ 0x502b4, 0x40800018 },
{ 0x5fffc, 0x24000e6 },
{ 0x502b8, 0x3f000014 },
{ 0x5fffc, 0x30000ee },
{ 0x502bc, 0x3d400010 },
{ 0x5fffc, 0x40000f5 },
{ 0x502c0, 0x3b80000c },
{ 0x5fffc, 0x50000fc },
{ 0x502c4, 0x39800009 },
{ 0x5fffc, 0x6000102 },
{ 0x502c8, 0x37c00006 },
{ 0x5fffc, 0x7000109 },
{ 0x502cc, 0x35800004 },
{ 0x5fffc, 0x840010e },
{ 0x502d0, 0x33800002 },
{ 0x5fffc, 0x9800114 },
{ 0x502d4, 0x31400000 },
{ 0x5fffc, 0xac00119 },
{ 0x502d8, 0x2f4003fe },
{ 0x5fffc, 0xc40011e },
{ 0x502dc, 0x2d0003fc },
{ 0x5fffc, 0xdc00121 },
{ 0x502e0, 0x2b0003fb },
{ 0x5fffc, 0xf400125 },
{ 0x502e4, 0x28c003fa },
{ 0x5fffc, 0x11000128 },
{ 0x502e8, 0x268003f9 },
{ 0x5fffc, 0x12c0012a },
{ 0x502ec, 0x244003f9 },
{ 0x5fffc, 0x1480012c },
{ 0x502f0, 0x224003f8 },
{ 0x5fffc, 0x1640012e },
{ 0x502f4, 0x200003f8 },
{ 0x5fffc, 0x1800012f },
{ 0x502f8, 0x1e0003f8 },
{ 0x5fffc, 0x1a00012f },
{ 0x502fc, 0x1c0003f8 },
};
static struct mdp_table_entry mdp_downscale_x_table_PT8TO1[] = {
{ 0x5fffc, 0x0 },
{ 0x50280, 0x7fc00000 },
{ 0x5fffc, 0xff80000d },
{ 0x50284, 0x7ec003f9 },
{ 0x5fffc, 0xfec0001c },
{ 0x50288, 0x7d4003f3 },
{ 0x5fffc, 0xfe40002b },
{ 0x5028c, 0x7b8003ed },
{ 0x5fffc, 0xfd80003c },
{ 0x50290, 0x794003e8 },
{ 0x5fffc, 0xfcc0004d },
{ 0x50294, 0x76c003e4 },
{ 0x5fffc, 0xfc40005f },
{ 0x50298, 0x73c003e0 },
{ 0x5fffc, 0xfb800071 },
{ 0x5029c, 0x708003de },
{ 0x5fffc, 0xfac00085 },
{ 0x502a0, 0x6d0003db },
{ 0x5fffc, 0xfa000098 },
{ 0x502a4, 0x698003d9 },
{ 0x5fffc, 0xf98000ac },
{ 0x502a8, 0x654003d8 },
{ 0x5fffc, 0xf8c000c1 },
{ 0x502ac, 0x610003d7 },
{ 0x5fffc, 0xf84000d5 },
{ 0x502b0, 0x5c8003d7 },
{ 0x5fffc, 0xf7c000e9 },
{ 0x502b4, 0x580003d7 },
{ 0x5fffc, 0xf74000fd },
{ 0x502b8, 0x534003d8 },
{ 0x5fffc, 0xf6c00112 },
{ 0x502bc, 0x4e8003d8 },
{ 0x5fffc, 0xf6800126 },
{ 0x502c0, 0x494003da },
{ 0x5fffc, 0xf600013a },
{ 0x502c4, 0x448003db },
{ 0x5fffc, 0xf600014d },
{ 0x502c8, 0x3f4003dd },
{ 0x5fffc, 0xf5c00160 },
{ 0x502cc, 0x3a4003df },
{ 0x5fffc, 0xf5c00172 },
{ 0x502d0, 0x354003e1 },
{ 0x5fffc, 0xf5c00184 },
{ 0x502d4, 0x304003e3 },
{ 0x5fffc, 0xf6000195 },
{ 0x502d8, 0x2b0003e6 },
{ 0x5fffc, 0xf64001a6 },
{ 0x502dc, 0x260003e8 },
{ 0x5fffc, 0xf6c001b4 },
{ 0x502e0, 0x214003eb },
{ 0x5fffc, 0xf78001c2 },
{ 0x502e4, 0x1c4003ee },
{ 0x5fffc, 0xf80001cf },
{ 0x502e8, 0x17c003f1 },
{ 0x5fffc, 0xf90001db },
{ 0x502ec, 0x134003f3 },
{ 0x5fffc, 0xfa0001e5 },
{ 0x502f0, 0xf0003f6 },
{ 0x5fffc, 0xfb4001ee },
{ 0x502f4, 0xac003f9 },
{ 0x5fffc, 0xfcc001f5 },
{ 0x502f8, 0x70003fb },
{ 0x5fffc, 0xfe4001fb },
{ 0x502fc, 0x34003fe },
};
struct mdp_table_entry *mdp_downscale_x_table[MDP_DOWNSCALE_MAX] = {
[MDP_DOWNSCALE_PT2TOPT4] = mdp_downscale_x_table_PT2TOPT4,
[MDP_DOWNSCALE_PT4TOPT6] = mdp_downscale_x_table_PT4TOPT6,
[MDP_DOWNSCALE_PT6TOPT8] = mdp_downscale_x_table_PT6TOPT8,
[MDP_DOWNSCALE_PT8TO1] = mdp_downscale_x_table_PT8TO1,
};
static struct mdp_table_entry mdp_downscale_y_table_PT2TOPT4[] = {
{ 0x5fffc, 0x740008c },
{ 0x50300, 0x33800088 },
{ 0x5fffc, 0x800008e },
{ 0x50304, 0x33400084 },
{ 0x5fffc, 0x8400092 },
{ 0x50308, 0x33000080 },
{ 0x5fffc, 0x9000094 },
{ 0x5030c, 0x3300007b },
{ 0x5fffc, 0x9c00098 },
{ 0x50310, 0x32400077 },
{ 0x5fffc, 0xa40009b },
{ 0x50314, 0x32000073 },
{ 0x5fffc, 0xb00009d },
{ 0x50318, 0x31c0006f },
{ 0x5fffc, 0xbc000a0 },
{ 0x5031c, 0x3140006b },
{ 0x5fffc, 0xc8000a2 },
{ 0x50320, 0x31000067 },
{ 0x5fffc, 0xd8000a5 },
{ 0x50324, 0x30800062 },
{ 0x5fffc, 0xe4000a8 },
{ 0x50328, 0x2fc0005f },
{ 0x5fffc, 0xec000aa },
{ 0x5032c, 0x2fc0005b },
{ 0x5fffc, 0xf8000ad },
{ 0x50330, 0x2f400057 },
{ 0x5fffc, 0x108000b0 },
{ 0x50334, 0x2e400054 },
{ 0x5fffc, 0x114000b2 },
{ 0x50338, 0x2e000050 },
{ 0x5fffc, 0x124000b4 },
{ 0x5033c, 0x2d80004c },
{ 0x5fffc, 0x130000b6 },
{ 0x50340, 0x2d000049 },
{ 0x5fffc, 0x140000b8 },
{ 0x50344, 0x2c800045 },
{ 0x5fffc, 0x150000b9 },
{ 0x50348, 0x2c000042 },
{ 0x5fffc, 0x15c000bd },
{ 0x5034c, 0x2b40003e },
{ 0x5fffc, 0x16c000bf },
{ 0x50350, 0x2a80003b },
{ 0x5fffc, 0x17c000bf },
{ 0x50354, 0x2a000039 },
{ 0x5fffc, 0x188000c2 },
{ 0x50358, 0x29400036 },
{ 0x5fffc, 0x19c000c4 },
{ 0x5035c, 0x28800032 },
{ 0x5fffc, 0x1ac000c5 },
{ 0x50360, 0x2800002f },
{ 0x5fffc, 0x1bc000c7 },
{ 0x50364, 0x2740002c },
{ 0x5fffc, 0x1cc000c8 },
{ 0x50368, 0x26c00029 },
{ 0x5fffc, 0x1dc000c9 },
{ 0x5036c, 0x26000027 },
{ 0x5fffc, 0x1ec000cc },
{ 0x50370, 0x25000024 },
{ 0x5fffc, 0x200000cc },
{ 0x50374, 0x24800021 },
{ 0x5fffc, 0x210000cd },
{ 0x50378, 0x23800020 },
{ 0x5fffc, 0x220000ce },
{ 0x5037c, 0x2300001d },
};
static struct mdp_table_entry mdp_downscale_y_table_PT4TOPT6[] = {
{ 0x5fffc, 0x740008c },
{ 0x50300, 0x33800088 },
{ 0x5fffc, 0x800008e },
{ 0x50304, 0x33400084 },
{ 0x5fffc, 0x8400092 },
{ 0x50308, 0x33000080 },
{ 0x5fffc, 0x9000094 },
{ 0x5030c, 0x3300007b },
{ 0x5fffc, 0x9c00098 },
{ 0x50310, 0x32400077 },
{ 0x5fffc, 0xa40009b },
{ 0x50314, 0x32000073 },
{ 0x5fffc, 0xb00009d },
{ 0x50318, 0x31c0006f },
{ 0x5fffc, 0xbc000a0 },
{ 0x5031c, 0x3140006b },
{ 0x5fffc, 0xc8000a2 },
{ 0x50320, 0x31000067 },
{ 0x5fffc, 0xd8000a5 },
{ 0x50324, 0x30800062 },
{ 0x5fffc, 0xe4000a8 },
{ 0x50328, 0x2fc0005f },
{ 0x5fffc, 0xec000aa },
{ 0x5032c, 0x2fc0005b },
{ 0x5fffc, 0xf8000ad },
{ 0x50330, 0x2f400057 },
{ 0x5fffc, 0x108000b0 },
{ 0x50334, 0x2e400054 },
{ 0x5fffc, 0x114000b2 },
{ 0x50338, 0x2e000050 },
{ 0x5fffc, 0x124000b4 },
{ 0x5033c, 0x2d80004c },
{ 0x5fffc, 0x130000b6 },
{ 0x50340, 0x2d000049 },
{ 0x5fffc, 0x140000b8 },
{ 0x50344, 0x2c800045 },
{ 0x5fffc, 0x150000b9 },
{ 0x50348, 0x2c000042 },
{ 0x5fffc, 0x15c000bd },
{ 0x5034c, 0x2b40003e },
{ 0x5fffc, 0x16c000bf },
{ 0x50350, 0x2a80003b },
{ 0x5fffc, 0x17c000bf },
{ 0x50354, 0x2a000039 },
{ 0x5fffc, 0x188000c2 },
{ 0x50358, 0x29400036 },
{ 0x5fffc, 0x19c000c4 },
{ 0x5035c, 0x28800032 },
{ 0x5fffc, 0x1ac000c5 },
{ 0x50360, 0x2800002f },
{ 0x5fffc, 0x1bc000c7 },
{ 0x50364, 0x2740002c },
{ 0x5fffc, 0x1cc000c8 },
{ 0x50368, 0x26c00029 },
{ 0x5fffc, 0x1dc000c9 },
{ 0x5036c, 0x26000027 },
{ 0x5fffc, 0x1ec000cc },
{ 0x50370, 0x25000024 },
{ 0x5fffc, 0x200000cc },
{ 0x50374, 0x24800021 },
{ 0x5fffc, 0x210000cd },
{ 0x50378, 0x23800020 },
{ 0x5fffc, 0x220000ce },
{ 0x5037c, 0x2300001d },
};
static struct mdp_table_entry mdp_downscale_y_table_PT6TOPT8[] = {
{ 0x5fffc, 0xfe000070 },
{ 0x50300, 0x4bc00068 },
{ 0x5fffc, 0xfe000078 },
{ 0x50304, 0x4bc00060 },
{ 0x5fffc, 0xfe000080 },
{ 0x50308, 0x4b800059 },
{ 0x5fffc, 0xfe000089 },
{ 0x5030c, 0x4b000052 },
{ 0x5fffc, 0xfe400091 },
{ 0x50310, 0x4a80004b },
{ 0x5fffc, 0xfe40009a },
{ 0x50314, 0x4a000044 },
{ 0x5fffc, 0xfe8000a3 },
{ 0x50318, 0x4940003d },
{ 0x5fffc, 0xfec000ac },
{ 0x5031c, 0x48400037 },
{ 0x5fffc, 0xff0000b4 },
{ 0x50320, 0x47800031 },
{ 0x5fffc, 0xff8000bd },
{ 0x50324, 0x4640002b },
{ 0x5fffc, 0xc5 },
{ 0x50328, 0x45000026 },
{ 0x5fffc, 0x8000ce },
{ 0x5032c, 0x43800021 },
{ 0x5fffc, 0x10000d6 },
{ 0x50330, 0x4240001c },
{ 0x5fffc, 0x18000df },
{ 0x50334, 0x40800018 },
{ 0x5fffc, 0x24000e6 },
{ 0x50338, 0x3f000014 },
{ 0x5fffc, 0x30000ee },
{ 0x5033c, 0x3d400010 },
{ 0x5fffc, 0x40000f5 },
{ 0x50340, 0x3b80000c },
{ 0x5fffc, 0x50000fc },
{ 0x50344, 0x39800009 },
{ 0x5fffc, 0x6000102 },
{ 0x50348, 0x37c00006 },
{ 0x5fffc, 0x7000109 },
{ 0x5034c, 0x35800004 },
{ 0x5fffc, 0x840010e },
{ 0x50350, 0x33800002 },
{ 0x5fffc, 0x9800114 },
{ 0x50354, 0x31400000 },
{ 0x5fffc, 0xac00119 },
{ 0x50358, 0x2f4003fe },
{ 0x5fffc, 0xc40011e },
{ 0x5035c, 0x2d0003fc },
{ 0x5fffc, 0xdc00121 },
{ 0x50360, 0x2b0003fb },
{ 0x5fffc, 0xf400125 },
{ 0x50364, 0x28c003fa },
{ 0x5fffc, 0x11000128 },
{ 0x50368, 0x268003f9 },
{ 0x5fffc, 0x12c0012a },
{ 0x5036c, 0x244003f9 },
{ 0x5fffc, 0x1480012c },
{ 0x50370, 0x224003f8 },
{ 0x5fffc, 0x1640012e },
{ 0x50374, 0x200003f8 },
{ 0x5fffc, 0x1800012f },
{ 0x50378, 0x1e0003f8 },
{ 0x5fffc, 0x1a00012f },
{ 0x5037c, 0x1c0003f8 },
};
static struct mdp_table_entry mdp_downscale_y_table_PT8TO1[] = {
{ 0x5fffc, 0x0 },
{ 0x50300, 0x7fc00000 },
{ 0x5fffc, 0xff80000d },
{ 0x50304, 0x7ec003f9 },
{ 0x5fffc, 0xfec0001c },
{ 0x50308, 0x7d4003f3 },
{ 0x5fffc, 0xfe40002b },
{ 0x5030c, 0x7b8003ed },
{ 0x5fffc, 0xfd80003c },
{ 0x50310, 0x794003e8 },
{ 0x5fffc, 0xfcc0004d },
{ 0x50314, 0x76c003e4 },
{ 0x5fffc, 0xfc40005f },
{ 0x50318, 0x73c003e0 },
{ 0x5fffc, 0xfb800071 },
{ 0x5031c, 0x708003de },
{ 0x5fffc, 0xfac00085 },
{ 0x50320, 0x6d0003db },
{ 0x5fffc, 0xfa000098 },
{ 0x50324, 0x698003d9 },
{ 0x5fffc, 0xf98000ac },
{ 0x50328, 0x654003d8 },
{ 0x5fffc, 0xf8c000c1 },
{ 0x5032c, 0x610003d7 },
{ 0x5fffc, 0xf84000d5 },
{ 0x50330, 0x5c8003d7 },
{ 0x5fffc, 0xf7c000e9 },
{ 0x50334, 0x580003d7 },
{ 0x5fffc, 0xf74000fd },
{ 0x50338, 0x534003d8 },
{ 0x5fffc, 0xf6c00112 },
{ 0x5033c, 0x4e8003d8 },
{ 0x5fffc, 0xf6800126 },
{ 0x50340, 0x494003da },
{ 0x5fffc, 0xf600013a },
{ 0x50344, 0x448003db },
{ 0x5fffc, 0xf600014d },
{ 0x50348, 0x3f4003dd },
{ 0x5fffc, 0xf5c00160 },
{ 0x5034c, 0x3a4003df },
{ 0x5fffc, 0xf5c00172 },
{ 0x50350, 0x354003e1 },
{ 0x5fffc, 0xf5c00184 },
{ 0x50354, 0x304003e3 },
{ 0x5fffc, 0xf6000195 },
{ 0x50358, 0x2b0003e6 },
{ 0x5fffc, 0xf64001a6 },
{ 0x5035c, 0x260003e8 },
{ 0x5fffc, 0xf6c001b4 },
{ 0x50360, 0x214003eb },
{ 0x5fffc, 0xf78001c2 },
{ 0x50364, 0x1c4003ee },
{ 0x5fffc, 0xf80001cf },
{ 0x50368, 0x17c003f1 },
{ 0x5fffc, 0xf90001db },
{ 0x5036c, 0x134003f3 },
{ 0x5fffc, 0xfa0001e5 },
{ 0x50370, 0xf0003f6 },
{ 0x5fffc, 0xfb4001ee },
{ 0x50374, 0xac003f9 },
{ 0x5fffc, 0xfcc001f5 },
{ 0x50378, 0x70003fb },
{ 0x5fffc, 0xfe4001fb },
{ 0x5037c, 0x34003fe },
};
struct mdp_table_entry *mdp_downscale_y_table[MDP_DOWNSCALE_MAX] = {
[MDP_DOWNSCALE_PT2TOPT4] = mdp_downscale_y_table_PT2TOPT4,
[MDP_DOWNSCALE_PT4TOPT6] = mdp_downscale_y_table_PT4TOPT6,
[MDP_DOWNSCALE_PT6TOPT8] = mdp_downscale_y_table_PT6TOPT8,
[MDP_DOWNSCALE_PT8TO1] = mdp_downscale_y_table_PT8TO1,
};
struct mdp_table_entry mdp_gaussian_blur_table[] = {
/* max variance */
{ 0x5fffc, 0x20000080 },
{ 0x50280, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x50284, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x50288, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x5028c, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x50290, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x50294, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x50298, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x5029c, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x502a0, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x502a4, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x502a8, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x502ac, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x502b0, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x502b4, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x502b8, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x502bc, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x502c0, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x502c4, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x502c8, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x502cc, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x502d0, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x502d4, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x502d8, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x502dc, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x502e0, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x502e4, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x502e8, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x502ec, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x502f0, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x502f4, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x502f8, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x502fc, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x50300, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x50304, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x50308, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x5030c, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x50310, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x50314, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x50318, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x5031c, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x50320, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x50324, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x50328, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x5032c, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x50330, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x50334, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x50338, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x5033c, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x50340, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x50344, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x50348, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x5034c, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x50350, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x50354, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x50358, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x5035c, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x50360, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x50364, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x50368, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x5036c, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x50370, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x50374, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x50378, 0x20000080 },
{ 0x5fffc, 0x20000080 },
{ 0x5037c, 0x20000080 },
};

38
drivers/video/msm/mdp_scale_tables.h Normal file
View File

@@ -0,0 +1,38 @@
/* drivers/video/msm_fb/mdp_scale_tables.h
*
* Copyright (C) 2007 QUALCOMM Incorporated
* Copyright (C) 2007 Google Incorporated
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _MDP_SCALE_TABLES_H_
#define _MDP_SCALE_TABLES_H_
#include <linux/types.h>
struct mdp_table_entry {
uint32_t reg;
uint32_t val;
};
extern struct mdp_table_entry mdp_upscale_table[64];
enum {
MDP_DOWNSCALE_PT2TOPT4,
MDP_DOWNSCALE_PT4TOPT6,
MDP_DOWNSCALE_PT6TOPT8,
MDP_DOWNSCALE_PT8TO1,
MDP_DOWNSCALE_MAX,
};
extern struct mdp_table_entry *mdp_downscale_x_table[MDP_DOWNSCALE_MAX];
extern struct mdp_table_entry *mdp_downscale_y_table[MDP_DOWNSCALE_MAX];
extern struct mdp_table_entry mdp_gaussian_blur_table[];
#endif

636
drivers/video/msm/msm_fb.c Normal file
View File

@@ -0,0 +1,636 @@
/* drivers/video/msm/msm_fb.c
*
* Core MSM framebuffer driver.
*
* Copyright (C) 2007 Google Incorporated
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/fb.h>
#include <linux/delay.h>
#include <linux/freezer.h>
#include <linux/wait.h>
#include <linux/msm_mdp.h>
#include <linux/io.h>
#include <linux/uaccess.h>
#include <mach/msm_fb.h>
#include <mach/board.h>
#include <linux/workqueue.h>
#include <linux/clk.h>
#include <linux/debugfs.h>
#include <linux/dma-mapping.h>
#define PRINT_FPS 0
#define PRINT_BLIT_TIME 0
#define SLEEPING 0x4
#define UPDATING 0x3
#define FULL_UPDATE_DONE 0x2
#define WAKING 0x1
#define AWAKE 0x0
#define NONE 0
#define SUSPEND_RESUME 0x1
#define FPS 0x2
#define BLIT_TIME 0x4
#define SHOW_UPDATES 0x8
#define DLOG(mask, fmt, args...) \
do { \
if (msmfb_debug_mask & mask) \
printk(KERN_INFO "msmfb: "fmt, ##args); \
} while (0)
static int msmfb_debug_mask;
module_param_named(msmfb_debug_mask, msmfb_debug_mask, int,
S_IRUGO | S_IWUSR | S_IWGRP);
struct mdp_device *mdp;
struct msmfb_info {
struct fb_info *fb;
struct msm_panel_data *panel;
int xres;
int yres;
unsigned output_format;
unsigned yoffset;
unsigned frame_requested;
unsigned frame_done;
int sleeping;
unsigned update_frame;
struct {
int left;
int top;
int eright; /* exclusive */
int ebottom; /* exclusive */
} update_info;
char *black;
spinlock_t update_lock;
struct mutex panel_init_lock;
wait_queue_head_t frame_wq;
struct workqueue_struct *resume_workqueue;
struct work_struct resume_work;
struct msmfb_callback dma_callback;
struct msmfb_callback vsync_callback;
struct hrtimer fake_vsync;
ktime_t vsync_request_time;
};
static int msmfb_open(struct fb_info *info, int user)
{
return 0;
}
static int msmfb_release(struct fb_info *info, int user)
{
return 0;
}
/* Called from dma interrupt handler, must not sleep */
static void msmfb_handle_dma_interrupt(struct msmfb_callback *callback)
{
unsigned long irq_flags;
struct msmfb_info *msmfb = container_of(callback, struct msmfb_info,
dma_callback);
spin_lock_irqsave(&msmfb->update_lock, irq_flags);
msmfb->frame_done = msmfb->frame_requested;
if (msmfb->sleeping == UPDATING &&
msmfb->frame_done == msmfb->update_frame) {
DLOG(SUSPEND_RESUME, "full update completed\n");
queue_work(msmfb->resume_workqueue, &msmfb->resume_work);
}
spin_unlock_irqrestore(&msmfb->update_lock, irq_flags);
wake_up(&msmfb->frame_wq);
}
static int msmfb_start_dma(struct msmfb_info *msmfb)
{
uint32_t x, y, w, h;
unsigned addr;
unsigned long irq_flags;
uint32_t yoffset;
s64 time_since_request;
struct msm_panel_data *panel = msmfb->panel;
spin_lock_irqsave(&msmfb->update_lock, irq_flags);
time_since_request = ktime_to_ns(ktime_sub(ktime_get(),
msmfb->vsync_request_time));
if (time_since_request > 20 * NSEC_PER_MSEC) {
uint32_t us;
us = do_div(time_since_request, NSEC_PER_MSEC) / NSEC_PER_USEC;
printk(KERN_WARNING "msmfb_start_dma %lld.%03u ms after vsync "
"request\n", time_since_request, us);
}
if (msmfb->frame_done == msmfb->frame_requested) {
spin_unlock_irqrestore(&msmfb->update_lock, irq_flags);
return -1;
}
if (msmfb->sleeping == SLEEPING) {
DLOG(SUSPEND_RESUME, "tried to start dma while asleep\n");
spin_unlock_irqrestore(&msmfb->update_lock, irq_flags);
return -1;
}
x = msmfb->update_info.left;
y = msmfb->update_info.top;
w = msmfb->update_info.eright - x;
h = msmfb->update_info.ebottom - y;
yoffset = msmfb->yoffset;
msmfb->update_info.left = msmfb->xres + 1;
msmfb->update_info.top = msmfb->yres + 1;
msmfb->update_info.eright = 0;
msmfb->update_info.ebottom = 0;
if (unlikely(w > msmfb->xres || h > msmfb->yres ||
w == 0 || h == 0)) {
printk(KERN_INFO "invalid update: %d %d %d "
"%d\n", x, y, w, h);
msmfb->frame_done = msmfb->frame_requested;
goto error;
}
spin_unlock_irqrestore(&msmfb->update_lock, irq_flags);
addr = ((msmfb->xres * (yoffset + y) + x) * 2);
mdp->dma(mdp, addr + msmfb->fb->fix.smem_start,
msmfb->xres * 2, w, h, x, y, &msmfb->dma_callback,
panel->interface_type);
return 0;
error:
spin_unlock_irqrestore(&msmfb->update_lock, irq_flags);
/* some clients need to clear their vsync interrupt */
if (panel->clear_vsync)
panel->clear_vsync(panel);
wake_up(&msmfb->frame_wq);
return 0;
}
/* Called from esync interrupt handler, must not sleep */
static void msmfb_handle_vsync_interrupt(struct msmfb_callback *callback)
{
struct msmfb_info *msmfb = container_of(callback, struct msmfb_info,
vsync_callback);
msmfb_start_dma(msmfb);
}
static enum hrtimer_restart msmfb_fake_vsync(struct hrtimer *timer)
{
struct msmfb_info *msmfb = container_of(timer, struct msmfb_info,
fake_vsync);
msmfb_start_dma(msmfb);
return HRTIMER_NORESTART;
}
static void msmfb_pan_update(struct fb_info *info, uint32_t left, uint32_t top,
uint32_t eright, uint32_t ebottom,
uint32_t yoffset, int pan_display)
{
struct msmfb_info *msmfb = info->par;
struct msm_panel_data *panel = msmfb->panel;
unsigned long irq_flags;
int sleeping;
int retry = 1;
DLOG(SHOW_UPDATES, "update %d %d %d %d %d %d\n",
left, top, eright, ebottom, yoffset, pan_display);
restart:
spin_lock_irqsave(&msmfb->update_lock, irq_flags);
/* if we are sleeping, on a pan_display wait 10ms (to throttle back
* drawing otherwise return */
if (msmfb->sleeping == SLEEPING) {
DLOG(SUSPEND_RESUME, "drawing while asleep\n");
spin_unlock_irqrestore(&msmfb->update_lock, irq_flags);
if (pan_display)
wait_event_interruptible_timeout(msmfb->frame_wq,
msmfb->sleeping != SLEEPING, HZ/10);
return;
}
sleeping = msmfb->sleeping;
/* on a full update, if the last frame has not completed, wait for it */
if (pan_display && (msmfb->frame_requested != msmfb->frame_done ||
sleeping == UPDATING)) {
int ret;
spin_unlock_irqrestore(&msmfb->update_lock, irq_flags);
ret = wait_event_interruptible_timeout(msmfb->frame_wq,
msmfb->frame_done == msmfb->frame_requested &&
msmfb->sleeping != UPDATING, 5 * HZ);
if (ret <= 0 && (msmfb->frame_requested != msmfb->frame_done ||
msmfb->sleeping == UPDATING)) {
if (retry && panel->request_vsync &&
(sleeping == AWAKE)) {
panel->request_vsync(panel,
&msmfb->vsync_callback);
retry = 0;
printk(KERN_WARNING "msmfb_pan_display timeout "
"rerequest vsync\n");
} else {
printk(KERN_WARNING "msmfb_pan_display timeout "
"waiting for frame start, %d %d\n",
msmfb->frame_requested,
msmfb->frame_done);
return;
}
}
goto restart;
}
msmfb->frame_requested++;
/* if necessary, update the y offset, if this is the
* first full update on resume, set the sleeping state */
if (pan_display) {
msmfb->yoffset = yoffset;
if (left == 0 && top == 0 && eright == info->var.xres &&
ebottom == info->var.yres) {
if (sleeping == WAKING) {
msmfb->update_frame = msmfb->frame_requested;
DLOG(SUSPEND_RESUME, "full update starting\n");
msmfb->sleeping = UPDATING;
}
}
}
/* set the update request */
if (left < msmfb->update_info.left)
msmfb->update_info.left = left;
if (top < msmfb->update_info.top)
msmfb->update_info.top = top;
if (eright > msmfb->update_info.eright)
msmfb->update_info.eright = eright;
if (ebottom > msmfb->update_info.ebottom)
msmfb->update_info.ebottom = ebottom;
DLOG(SHOW_UPDATES, "update queued %d %d %d %d %d\n",
msmfb->update_info.left, msmfb->update_info.top,
msmfb->update_info.eright, msmfb->update_info.ebottom,
msmfb->yoffset);
spin_unlock_irqrestore(&msmfb->update_lock, irq_flags);
/* if the panel is all the way on wait for vsync, otherwise sleep
* for 16 ms (long enough for the dma to panel) and then begin dma */
msmfb->vsync_request_time = ktime_get();
if (panel->request_vsync && (sleeping == AWAKE)) {
panel->request_vsync(panel, &msmfb->vsync_callback);
} else {
if (!hrtimer_active(&msmfb->fake_vsync)) {
hrtimer_start(&msmfb->fake_vsync,
ktime_set(0, NSEC_PER_SEC/60),
HRTIMER_MODE_REL);
}
}
}
static void msmfb_update(struct fb_info *info, uint32_t left, uint32_t top,
uint32_t eright, uint32_t ebottom)
{
msmfb_pan_update(info, left, top, eright, ebottom, 0, 0);
}
static void power_on_panel(struct work_struct *work)
{
struct msmfb_info *msmfb =
container_of(work, struct msmfb_info, resume_work);
struct msm_panel_data *panel = msmfb->panel;
unsigned long irq_flags;
mutex_lock(&msmfb->panel_init_lock);
DLOG(SUSPEND_RESUME, "turning on panel\n");
if (msmfb->sleeping == UPDATING) {
if (panel->unblank(panel)) {
printk(KERN_INFO "msmfb: panel unblank failed,"
"not starting drawing\n");
goto error;
}
spin_lock_irqsave(&msmfb->update_lock, irq_flags);
msmfb->sleeping = AWAKE;
wake_up(&msmfb->frame_wq);
spin_unlock_irqrestore(&msmfb->update_lock, irq_flags);
}
error:
mutex_unlock(&msmfb->panel_init_lock);
}
static int msmfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
if ((var->xres != info->var.xres) ||
(var->yres != info->var.yres) ||
(var->xres_virtual != info->var.xres_virtual) ||
(var->yres_virtual != info->var.yres_virtual) ||
(var->xoffset != info->var.xoffset) ||
(var->bits_per_pixel != info->var.bits_per_pixel) ||
(var->grayscale != info->var.grayscale))
return -EINVAL;
return 0;
}
int msmfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
{
struct msmfb_info *msmfb = info->par;
struct msm_panel_data *panel = msmfb->panel;
/* "UPDT" */
if ((panel->caps & MSMFB_CAP_PARTIAL_UPDATES) &&
(var->reserved[0] == 0x54445055)) {
msmfb_pan_update(info, var->reserved[1] & 0xffff,
var->reserved[1] >> 16,
var->reserved[2] & 0xffff,
var->reserved[2] >> 16, var->yoffset, 1);
} else {
msmfb_pan_update(info, 0, 0, info->var.xres, info->var.yres,
var->yoffset, 1);
}
return 0;
}
static void msmfb_fillrect(struct fb_info *p, const struct fb_fillrect *rect)
{
cfb_fillrect(p, rect);
msmfb_update(p, rect->dx, rect->dy, rect->dx + rect->width,
rect->dy + rect->height);
}
static void msmfb_copyarea(struct fb_info *p, const struct fb_copyarea *area)
{
cfb_copyarea(p, area);
msmfb_update(p, area->dx, area->dy, area->dx + area->width,
area->dy + area->height);
}
static void msmfb_imageblit(struct fb_info *p, const struct fb_image *image)
{
cfb_imageblit(p, image);
msmfb_update(p, image->dx, image->dy, image->dx + image->width,
image->dy + image->height);
}
static int msmfb_blit(struct fb_info *info,
void __user *p)
{
struct mdp_blit_req req;
struct mdp_blit_req_list req_list;
int i;
int ret;
if (copy_from_user(&req_list, p, sizeof(req_list)))
return -EFAULT;
for (i = 0; i < req_list.count; i++) {
struct mdp_blit_req_list *list =
(struct mdp_blit_req_list *)p;
if (copy_from_user(&req, &list->req[i], sizeof(req)))
return -EFAULT;
ret = mdp->blit(mdp, info, &req);
if (ret)
return ret;
}
return 0;
}
DEFINE_MUTEX(mdp_ppp_lock);
static int msmfb_ioctl(struct fb_info *p, unsigned int cmd, unsigned long arg)
{
void __user *argp = (void __user *)arg;
int ret;
switch (cmd) {
case MSMFB_GRP_DISP:
mdp->set_grp_disp(mdp, arg);
break;
case MSMFB_BLIT:
ret = msmfb_blit(p, argp);
if (ret)
return ret;
break;
default:
printk(KERN_INFO "msmfb unknown ioctl: %d\n", cmd);
return -EINVAL;
}
return 0;
}
static struct fb_ops msmfb_ops = {
.owner = THIS_MODULE,
.fb_open = msmfb_open,
.fb_release = msmfb_release,
.fb_check_var = msmfb_check_var,
.fb_pan_display = msmfb_pan_display,
.fb_fillrect = msmfb_fillrect,
.fb_copyarea = msmfb_copyarea,
.fb_imageblit = msmfb_imageblit,
.fb_ioctl = msmfb_ioctl,
};
static unsigned PP[16];
#define BITS_PER_PIXEL 16
static void setup_fb_info(struct msmfb_info *msmfb)
{
struct fb_info *fb_info = msmfb->fb;
int r;
/* finish setting up the fb_info struct */
strncpy(fb_info->fix.id, "msmfb", 16);
fb_info->fix.ypanstep = 1;
fb_info->fbops = &msmfb_ops;
fb_info->flags = FBINFO_DEFAULT;
fb_info->fix.type = FB_TYPE_PACKED_PIXELS;
fb_info->fix.visual = FB_VISUAL_TRUECOLOR;
fb_info->fix.line_length = msmfb->xres * 2;
fb_info->var.xres = msmfb->xres;
fb_info->var.yres = msmfb->yres;
fb_info->var.width = msmfb->panel->fb_data->width;
fb_info->var.height = msmfb->panel->fb_data->height;
fb_info->var.xres_virtual = msmfb->xres;
fb_info->var.yres_virtual = msmfb->yres * 2;
fb_info->var.bits_per_pixel = BITS_PER_PIXEL;
fb_info->var.accel_flags = 0;
fb_info->var.yoffset = 0;
if (msmfb->panel->caps & MSMFB_CAP_PARTIAL_UPDATES) {
fb_info->var.reserved[0] = 0x54445055;
fb_info->var.reserved[1] = 0;
fb_info->var.reserved[2] = (uint16_t)msmfb->xres |
((uint32_t)msmfb->yres << 16);
}
fb_info->var.red.offset = 11;
fb_info->var.red.length = 5;
fb_info->var.red.msb_right = 0;
fb_info->var.green.offset = 5;
fb_info->var.green.length = 6;
fb_info->var.green.msb_right = 0;
fb_info->var.blue.offset = 0;
fb_info->var.blue.length = 5;
fb_info->var.blue.msb_right = 0;
r = fb_alloc_cmap(&fb_info->cmap, 16, 0);
fb_info->pseudo_palette = PP;
PP[0] = 0;
for (r = 1; r < 16; r++)
PP[r] = 0xffffffff;
}
static int setup_fbmem(struct msmfb_info *msmfb, struct platform_device *pdev)
{
struct fb_info *fb = msmfb->fb;
struct resource *resource;
unsigned long size = msmfb->xres * msmfb->yres *
(BITS_PER_PIXEL >> 3) * 2;
unsigned char *fbram;
/* board file might have attached a resource describing an fb */
resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!resource)
return -EINVAL;
/* check the resource is large enough to fit the fb */
if (resource->end - resource->start < size) {
printk(KERN_ERR "allocated resource is too small for "
"fb\n");
return -ENOMEM;
}
fb->fix.smem_start = resource->start;
fb->fix.smem_len = resource->end - resource->start;
fbram = ioremap(resource->start,
resource->end - resource->start);
if (fbram == 0) {
printk(KERN_ERR "msmfb: cannot allocate fbram!\n");
return -ENOMEM;
}
fb->screen_base = fbram;
return 0;
}
static int msmfb_probe(struct platform_device *pdev)
{
struct fb_info *fb;
struct msmfb_info *msmfb;
struct msm_panel_data *panel = pdev->dev.platform_data;
int ret;
if (!panel) {
pr_err("msmfb_probe: no platform data\n");
return -EINVAL;
}
if (!panel->fb_data) {
pr_err("msmfb_probe: no fb_data\n");
return -EINVAL;
}
fb = framebuffer_alloc(sizeof(struct msmfb_info), &pdev->dev);
if (!fb)
return -ENOMEM;
msmfb = fb->par;
msmfb->fb = fb;
msmfb->panel = panel;
msmfb->xres = panel->fb_data->xres;
msmfb->yres = panel->fb_data->yres;
ret = setup_fbmem(msmfb, pdev);
if (ret)
goto error_setup_fbmem;
setup_fb_info(msmfb);
spin_lock_init(&msmfb->update_lock);
mutex_init(&msmfb->panel_init_lock);
init_waitqueue_head(&msmfb->frame_wq);
msmfb->resume_workqueue = create_workqueue("panel_on");
if (msmfb->resume_workqueue == NULL) {
printk(KERN_ERR "failed to create panel_on workqueue\n");
ret = -ENOMEM;
goto error_create_workqueue;
}
INIT_WORK(&msmfb->resume_work, power_on_panel);
msmfb->black = kzalloc(msmfb->fb->var.bits_per_pixel*msmfb->xres,
GFP_KERNEL);
printk(KERN_INFO "msmfb_probe() installing %d x %d panel\n",
msmfb->xres, msmfb->yres);
msmfb->dma_callback.func = msmfb_handle_dma_interrupt;
msmfb->vsync_callback.func = msmfb_handle_vsync_interrupt;
hrtimer_init(&msmfb->fake_vsync, CLOCK_MONOTONIC,
HRTIMER_MODE_REL);
msmfb->fake_vsync.function = msmfb_fake_vsync;
ret = register_framebuffer(fb);
if (ret)
goto error_register_framebuffer;
msmfb->sleeping = WAKING;
return 0;
error_register_framebuffer:
destroy_workqueue(msmfb->resume_workqueue);
error_create_workqueue:
iounmap(fb->screen_base);
error_setup_fbmem:
framebuffer_release(msmfb->fb);
return ret;
}
static struct platform_driver msm_panel_driver = {
/* need to write remove */
.probe = msmfb_probe,
.driver = {.name = "msm_panel"},
};
static int msmfb_add_mdp_device(struct device *dev,
struct class_interface *class_intf)
{
/* might need locking if mulitple mdp devices */
if (mdp)
return 0;
mdp = container_of(dev, struct mdp_device, dev);
return platform_driver_register(&msm_panel_driver);
}
static void msmfb_remove_mdp_device(struct device *dev,
struct class_interface *class_intf)
{
/* might need locking if mulitple mdp devices */
if (dev != &mdp->dev)
return;
platform_driver_unregister(&msm_panel_driver);
mdp = NULL;
}
static struct class_interface msm_fb_interface = {
.add_dev = &msmfb_add_mdp_device,
.remove_dev = &msmfb_remove_mdp_device,
};
static int __init msmfb_init(void)
{
return register_mdp_client(&msm_fb_interface);
}
module_init(msmfb_init);

82
drivers/video/omap/Kconfig
View File

@@ -7,6 +7,69 @@ config FB_OMAP
help
Frame buffer driver for OMAP based boards.
config FB_OMAP_LCD_VGA
bool "Use LCD in VGA mode"
depends on MACH_OMAP_3430SDP || MACH_OMAP_LDP
choice
depends on FB_OMAP && MACH_OVERO
prompt "Screen resolution"
default FB_OMAP_079M3R
help
Selected desired screen resolution
config FB_OMAP_031M3R
boolean "640 x 480 @ 60 Hz Reduced blanking"
config FB_OMAP_048M3R
boolean "800 x 600 @ 60 Hz Reduced blanking"
config FB_OMAP_079M3R
boolean "1024 x 768 @ 60 Hz Reduced blanking"
config FB_OMAP_092M9R
boolean "1280 x 720 @ 60 Hz Reduced blanking"
endchoice
config FB_OMAP_LCDC_EXTERNAL
bool "External LCD controller support"
depends on FB_OMAP
help
Say Y here, if you want to have support for boards with an
external LCD controller connected to the SoSSI/RFBI interface.
config FB_OMAP_LCDC_HWA742
bool "Epson HWA742 LCD controller support"
depends on FB_OMAP && FB_OMAP_LCDC_EXTERNAL
help
Say Y here if you want to have support for the external
Epson HWA742 LCD controller.
config FB_OMAP_LCDC_BLIZZARD
bool "Epson Blizzard LCD controller support"
depends on FB_OMAP && FB_OMAP_LCDC_EXTERNAL
help
Say Y here if you want to have support for the external
Epson Blizzard LCD controller.
config FB_OMAP_MANUAL_UPDATE
bool "Default to manual update mode"
depends on FB_OMAP && FB_OMAP_LCDC_EXTERNAL
help
Say Y here, if your user-space applications are capable of
notifying the frame buffer driver when a change has occured in
the frame buffer content and thus a reload of the image data to
the external frame buffer is required. If unsure, say N.
config FB_OMAP_LCD_MIPID
bool "MIPI DBI-C/DCS compatible LCD support"
depends on FB_OMAP && SPI_MASTER
help
Say Y here if you want to have support for LCDs compatible with
the Mobile Industry Processor Interface DBI-C/DCS
specification. (Supported LCDs: Philips LPH8923, Sharp LS041Y3)
config FB_OMAP_BOOTLOADER_INIT
bool "Check bootloader initialization"
depends on FB_OMAP
@@ -36,23 +99,4 @@ config FB_OMAP_DMA_TUNE
answer yes. Answer no if you have a dedicated video
memory, or don't use any of the accelerated features.
config FB_OMAP_LCDC_EXTERNAL
bool "External LCD controller support"
depends on FB_OMAP
help
Say Y here, if you want to have support for boards with an
external LCD controller connected to the SoSSI/RFBI interface.
config FB_OMAP_LCDC_HWA742
bool "Epson HWA742 LCD controller support"
depends on FB_OMAP && FB_OMAP_LCDC_EXTERNAL
help
Say Y here if you want to have support for the external
Epson HWA742 LCD controller.
config FB_OMAP_LCDC_BLIZZARD
bool "Epson Blizzard LCD controller support"
depends on FB_OMAP && FB_OMAP_LCDC_EXTERNAL
help
Say Y here if you want to have support for the external
Epson Blizzard LCD controller.

12
drivers/video/omap/Makefile
View File

@@ -8,6 +8,7 @@ objs-yy := omapfb_main.o
objs-y$(CONFIG_ARCH_OMAP1) += lcdc.o
objs-y$(CONFIG_ARCH_OMAP2) += dispc.o
objs-y$(CONFIG_ARCH_OMAP3) += dispc.o
objs-$(CONFIG_ARCH_OMAP1)$(CONFIG_FB_OMAP_LCDC_EXTERNAL) += sossi.o
objs-$(CONFIG_ARCH_OMAP2)$(CONFIG_FB_OMAP_LCDC_EXTERNAL) += rfbi.o
@@ -15,6 +16,7 @@ objs-$(CONFIG_ARCH_OMAP2)$(CONFIG_FB_OMAP_LCDC_EXTERNAL) += rfbi.o
objs-y$(CONFIG_FB_OMAP_LCDC_HWA742) += hwa742.o
objs-y$(CONFIG_FB_OMAP_LCDC_BLIZZARD) += blizzard.o
objs-y$(CONFIG_MACH_AMS_DELTA) += lcd_ams_delta.o
objs-y$(CONFIG_MACH_OMAP_H4) += lcd_h4.o
objs-y$(CONFIG_MACH_OMAP_H3) += lcd_h3.o
objs-y$(CONFIG_MACH_OMAP_PALMTE) += lcd_palmte.o
@@ -24,5 +26,15 @@ objs-$(CONFIG_ARCH_OMAP16XX)$(CONFIG_MACH_OMAP_INNOVATOR) += lcd_inn1610.o
objs-$(CONFIG_ARCH_OMAP15XX)$(CONFIG_MACH_OMAP_INNOVATOR) += lcd_inn1510.o
objs-y$(CONFIG_MACH_OMAP_OSK) += lcd_osk.o
objs-y$(CONFIG_MACH_OMAP_APOLLON) += lcd_apollon.o
objs-y$(CONFIG_MACH_OMAP_2430SDP) += lcd_2430sdp.o
objs-y$(CONFIG_MACH_OMAP_3430SDP) += lcd_2430sdp.o
objs-y$(CONFIG_MACH_OMAP_LDP) += lcd_ldp.o
objs-y$(CONFIG_MACH_OMAP2EVM) += lcd_omap2evm.o
objs-y$(CONFIG_MACH_OMAP3EVM) += lcd_omap3evm.o
objs-y$(CONFIG_MACH_OMAP3_BEAGLE) += lcd_omap3beagle.o
objs-y$(CONFIG_FB_OMAP_LCD_MIPID) += lcd_mipid.o
objs-y$(CONFIG_MACH_OVERO) += lcd_overo.o
omapfb-objs := $(objs-yy)

91
drivers/video/omap/blizzard.c
View File

@@ -44,6 +44,7 @@
#define BLIZZARD_CLK_SRC 0x0e
#define BLIZZARD_MEM_BANK0_ACTIVATE 0x10
#define BLIZZARD_MEM_BANK0_STATUS 0x14
#define BLIZZARD_PANEL_CONFIGURATION 0x28
#define BLIZZARD_HDISP 0x2a
#define BLIZZARD_HNDP 0x2c
#define BLIZZARD_VDISP0 0x2e
@@ -162,6 +163,10 @@ struct blizzard_struct {
int vid_scaled;
int last_color_mode;
int zoom_on;
int zoom_area_gx1;
int zoom_area_gx2;
int zoom_area_gy1;
int zoom_area_gy2;
int screen_width;
int screen_height;
unsigned te_connected:1;
@@ -513,6 +518,13 @@ static int do_full_screen_update(struct blizzard_request *req)
return REQ_PENDING;
}
static int check_1d_intersect(int a1, int a2, int b1, int b2)
{
if (a2 <= b1 || b2 <= a1)
return 0;
return 1;
}
/* Setup all planes with an overlapping area with the update window. */
static int do_partial_update(struct blizzard_request *req, int plane,
int x, int y, int w, int h,
@@ -525,6 +537,7 @@ static int do_partial_update(struct blizzard_request *req, int plane,
int color_mode;
int flags;
int zoom_off;
int have_zoom_for_this_update = 0;
/* Global coordinates, relative to pixel 0,0 of the LCD */
gx1 = x + blizzard.plane[plane].pos_x;
@@ -544,10 +557,6 @@ static int do_partial_update(struct blizzard_request *req, int plane,
gx2_out = gx1_out + w_out;
gy2_out = gy1_out + h_out;
}
zoom_off = blizzard.zoom_on && gx1 == 0 && gy1 == 0 &&
w == blizzard.screen_width && h == blizzard.screen_height;
blizzard.zoom_on = (!zoom_off && blizzard.zoom_on) ||
(w < w_out || h < h_out);
for (i = 0; i < OMAPFB_PLANE_NUM; i++) {
struct plane_info *p = &blizzard.plane[i];
@@ -653,8 +662,49 @@ static int do_partial_update(struct blizzard_request *req, int plane,
else
disable_tearsync();
if ((gx2_out - gx1_out) != (gx2 - gx1) ||
(gy2_out - gy1_out) != (gy2 - gy1))
have_zoom_for_this_update = 1;
/* 'background' type of screen update (as opposed to 'destructive')
can be used to disable scaling if scaling is active */
zoom_off = blizzard.zoom_on && !have_zoom_for_this_update &&
(gx1_out == 0) && (gx2_out == blizzard.screen_width) &&
(gy1_out == 0) && (gy2_out == blizzard.screen_height) &&
(gx1 == 0) && (gy1 == 0);
if (blizzard.zoom_on && !have_zoom_for_this_update && !zoom_off &&
check_1d_intersect(blizzard.zoom_area_gx1, blizzard.zoom_area_gx2,
gx1_out, gx2_out) &&
check_1d_intersect(blizzard.zoom_area_gy1, blizzard.zoom_area_gy2,
gy1_out, gy2_out)) {
/* Previous screen update was using scaling, current update
* is not using it. Additionally, current screen update is
* going to overlap with the scaled area. Scaling needs to be
* disabled in order to avoid 'magnifying glass' effect.
* Dummy setup of background window can be used for this.
*/
set_window_regs(0, 0, blizzard.screen_width,
blizzard.screen_height,
0, 0, blizzard.screen_width,
blizzard.screen_height,
BLIZZARD_COLOR_RGB565, 1, flags);
blizzard.zoom_on = 0;
}
/* remember scaling settings if we have scaled update */
if (have_zoom_for_this_update) {
blizzard.zoom_on = 1;
blizzard.zoom_area_gx1 = gx1_out;
blizzard.zoom_area_gx2 = gx2_out;
blizzard.zoom_area_gy1 = gy1_out;
blizzard.zoom_area_gy2 = gy2_out;
}
set_window_regs(gx1, gy1, gx2, gy2, gx1_out, gy1_out, gx2_out, gy2_out,
color_mode, zoom_off, flags);
if (zoom_off)
blizzard.zoom_on = 0;
blizzard.extif->set_bits_per_cycle(16);
/* set_window_regs has left the register index at the right
@@ -908,6 +958,35 @@ static int blizzard_set_scale(int plane, int orig_w, int orig_h,
return 0;
}
static int blizzard_set_rotate(int angle)
{
u32 l;
l = blizzard_read_reg(BLIZZARD_PANEL_CONFIGURATION);
l &= ~0x03;
switch (angle) {
case 0:
l = l | 0x00;
break;
case 90:
l = l | 0x03;
break;
case 180:
l = l | 0x02;
break;
case 270:
l = l | 0x01;
break;
default:
return -EINVAL;
}
blizzard_write_reg(BLIZZARD_PANEL_CONFIGURATION, l);
return 0;
}
static int blizzard_enable_plane(int plane, int enable)
{
if (enable)
@@ -1285,7 +1364,8 @@ static void blizzard_get_caps(int plane, struct omapfb_caps *caps)
caps->ctrl |= OMAPFB_CAPS_MANUAL_UPDATE |
OMAPFB_CAPS_WINDOW_PIXEL_DOUBLE |
OMAPFB_CAPS_WINDOW_SCALE |
OMAPFB_CAPS_WINDOW_OVERLAY;
OMAPFB_CAPS_WINDOW_OVERLAY |
OMAPFB_CAPS_WINDOW_ROTATE;
if (blizzard.te_connected)
caps->ctrl |= OMAPFB_CAPS_TEARSYNC;
caps->wnd_color |= (1 << OMAPFB_COLOR_RGB565) |
@@ -1560,6 +1640,7 @@ struct lcd_ctrl blizzard_ctrl = {
.setup_plane = blizzard_setup_plane,
.set_scale = blizzard_set_scale,
.enable_plane = blizzard_enable_plane,
.set_rotate = blizzard_set_rotate,
.update_window = blizzard_update_window_async,
.sync = blizzard_sync,
.suspend = blizzard_suspend,

142
drivers/video/omap/dispc.c
View File

@@ -155,6 +155,8 @@ struct resmap {
unsigned long *map;
};
#define MAX_IRQ_HANDLERS 4
static struct {
void __iomem *base;
@@ -167,9 +169,11 @@ static struct {
int ext_mode;
unsigned long enabled_irqs;
void (*irq_callback)(void *);
void *irq_callback_data;
struct {
u32 irq_mask;
void (*callback)(void *);
void *data;
} irq_handlers[MAX_IRQ_HANDLERS];
struct completion frame_done;
int fir_hinc[OMAPFB_PLANE_NUM];
@@ -212,9 +216,9 @@ static void enable_rfbi_mode(int enable)
dispc_write_reg(DISPC_CONTROL, l);
/* Set bypass mode in RFBI module */
l = __raw_readl(IO_ADDRESS(RFBI_CONTROL));
l = __raw_readl(OMAP2_IO_ADDRESS(RFBI_CONTROL));
l |= enable ? 0 : (1 << 1);
__raw_writel(l, IO_ADDRESS(RFBI_CONTROL));
__raw_writel(l, OMAP2_IO_ADDRESS(RFBI_CONTROL));
}
static void set_lcd_data_lines(int data_lines)
@@ -286,7 +290,7 @@ static void setup_plane_fifo(int plane, int ext_mode)
BUG_ON(plane > 2);
l = dispc_read_reg(fsz_reg[plane]);
l &= FLD_MASK(0, 9);
l &= FLD_MASK(0, 11);
if (ext_mode) {
low = l * 3 / 4;
high = l;
@@ -294,7 +298,7 @@ static void setup_plane_fifo(int plane, int ext_mode)
low = l / 4;
high = l * 3 / 4;
}
MOD_REG_FLD(ftrs_reg[plane], FLD_MASK(16, 9) | FLD_MASK(0, 9),
MOD_REG_FLD(ftrs_reg[plane], FLD_MASK(16, 12) | FLD_MASK(0, 12),
(high << 16) | low);
}
@@ -809,57 +813,74 @@ static void set_lcd_timings(void)
panel->pixel_clock = fck / lck_div / pck_div / 1000;
}
int omap_dispc_request_irq(void (*callback)(void *data), void *data)
static void recalc_irq_mask(void)
{
int r = 0;
int i;
unsigned long irq_mask = DISPC_IRQ_MASK_ERROR;
for (i = 0; i < MAX_IRQ_HANDLERS; i++) {
if (!dispc.irq_handlers[i].callback)
continue;
irq_mask |= dispc.irq_handlers[i].irq_mask;
}
enable_lcd_clocks(1);
MOD_REG_FLD(DISPC_IRQENABLE, 0x7fff, irq_mask);
enable_lcd_clocks(0);
}
int omap_dispc_request_irq(unsigned long irq_mask, void (*callback)(void *data),
void *data)
{
int i;
BUG_ON(callback == NULL);
if (dispc.irq_callback)
r = -EBUSY;
else {
dispc.irq_callback = callback;
dispc.irq_callback_data = data;
for (i = 0; i < MAX_IRQ_HANDLERS; i++) {
if (dispc.irq_handlers[i].callback)
continue;
dispc.irq_handlers[i].irq_mask = irq_mask;
dispc.irq_handlers[i].callback = callback;
dispc.irq_handlers[i].data = data;
recalc_irq_mask();
return 0;
}
return r;
return -EBUSY;
}
EXPORT_SYMBOL(omap_dispc_request_irq);
void omap_dispc_enable_irqs(int irq_mask)
void omap_dispc_free_irq(unsigned long irq_mask, void (*callback)(void *data),
void *data)
{
enable_lcd_clocks(1);
dispc.enabled_irqs = irq_mask;
irq_mask |= DISPC_IRQ_MASK_ERROR;
MOD_REG_FLD(DISPC_IRQENABLE, 0x7fff, irq_mask);
enable_lcd_clocks(0);
}
EXPORT_SYMBOL(omap_dispc_enable_irqs);
int i;
void omap_dispc_disable_irqs(int irq_mask)
{
enable_lcd_clocks(1);
dispc.enabled_irqs &= ~irq_mask;
irq_mask &= ~DISPC_IRQ_MASK_ERROR;
MOD_REG_FLD(DISPC_IRQENABLE, 0x7fff, irq_mask);
enable_lcd_clocks(0);
}
EXPORT_SYMBOL(omap_dispc_disable_irqs);
for (i = 0; i < MAX_IRQ_HANDLERS; i++) {
if (dispc.irq_handlers[i].callback == callback &&
dispc.irq_handlers[i].data == data) {
dispc.irq_handlers[i].irq_mask = 0;
dispc.irq_handlers[i].callback = NULL;
dispc.irq_handlers[i].data = NULL;
recalc_irq_mask();
return;
}
}
void omap_dispc_free_irq(void)
{
enable_lcd_clocks(1);
omap_dispc_disable_irqs(DISPC_IRQ_MASK_ALL);
dispc.irq_callback = NULL;
dispc.irq_callback_data = NULL;
enable_lcd_clocks(0);
BUG();
}
EXPORT_SYMBOL(omap_dispc_free_irq);
static irqreturn_t omap_dispc_irq_handler(int irq, void *dev)
{
u32 stat = dispc_read_reg(DISPC_IRQSTATUS);
u32 stat;
int i = 0;
enable_lcd_clocks(1);
stat = dispc_read_reg(DISPC_IRQSTATUS);
if (stat & DISPC_IRQ_FRAMEMASK)
complete(&dispc.frame_done);
@@ -870,11 +891,17 @@ static irqreturn_t omap_dispc_irq_handler(int irq, void *dev)
}
}
if ((stat & dispc.enabled_irqs) && dispc.irq_callback)
dispc.irq_callback(dispc.irq_callback_data);
for (i = 0; i < MAX_IRQ_HANDLERS; i++) {
if (unlikely(dispc.irq_handlers[i].callback &&
(stat & dispc.irq_handlers[i].irq_mask)))
dispc.irq_handlers[i].callback(
dispc.irq_handlers[i].data);
}
dispc_write_reg(DISPC_IRQSTATUS, stat);
enable_lcd_clocks(0);
return IRQ_HANDLED;
}
@@ -913,18 +940,13 @@ static void put_dss_clocks(void)
static void enable_lcd_clocks(int enable)
{
if (enable)
clk_enable(dispc.dss1_fck);
else
clk_disable(dispc.dss1_fck);
}
static void enable_interface_clocks(int enable)
{
if (enable)
if (enable) {
clk_enable(dispc.dss_ick);
else
clk_enable(dispc.dss1_fck);
} else {
clk_disable(dispc.dss1_fck);
clk_disable(dispc.dss_ick);
}
}
static void enable_digit_clocks(int enable)
@@ -1365,7 +1387,6 @@ static int omap_dispc_init(struct omapfb_device *fbdev, int ext_mode,
if ((r = get_dss_clocks()) < 0)
goto fail0;
enable_interface_clocks(1);
enable_lcd_clocks(1);
#ifdef CONFIG_FB_OMAP_BOOTLOADER_INIT
@@ -1396,10 +1417,10 @@ static int omap_dispc_init(struct omapfb_device *fbdev, int ext_mode,
enable_digit_clocks(0);
}
/* Enable smart idle and autoidle */
l = dispc_read_reg(DISPC_CONTROL);
/* Enable smart standby/idle, autoidle and wakeup */
l = dispc_read_reg(DISPC_SYSCONFIG);
l &= ~((3 << 12) | (3 << 3));
l |= (2 << 12) | (2 << 3) | (1 << 0);
l |= (2 << 12) | (2 << 3) | (1 << 2) | (1 << 0);
dispc_write_reg(DISPC_SYSCONFIG, l);
omap_writel(1 << 0, DSS_BASE + DSS_SYSCONFIG);
@@ -1409,10 +1430,9 @@ static int omap_dispc_init(struct omapfb_device *fbdev, int ext_mode,
dispc_write_reg(DISPC_CONFIG, l);
l = dispc_read_reg(DISPC_IRQSTATUS);
dispc_write_reg(l, DISPC_IRQSTATUS);
dispc_write_reg(DISPC_IRQSTATUS, l);
/* Enable those that we handle always */
omap_dispc_enable_irqs(DISPC_IRQ_FRAMEMASK);
recalc_irq_mask();
if ((r = request_irq(INT_24XX_DSS_IRQ, omap_dispc_irq_handler,
0, MODULE_NAME, fbdev)) < 0) {
@@ -1421,7 +1441,7 @@ static int omap_dispc_init(struct omapfb_device *fbdev, int ext_mode,
}
/* L3 firewall setting: enable access to OCM RAM */
__raw_writel(0x402000b0, IO_ADDRESS(0x680050a0));
__raw_writel(0x402000b0, OMAP2_IO_ADDRESS(0x680050a0));
if ((r = alloc_palette_ram()) < 0)
goto fail2;
@@ -1469,7 +1489,6 @@ fail2:
free_irq(INT_24XX_DSS_IRQ, fbdev);
fail1:
enable_lcd_clocks(0);
enable_interface_clocks(0);
put_dss_clocks();
fail0:
iounmap(dispc.base);
@@ -1487,7 +1506,6 @@ static void omap_dispc_cleanup(void)
cleanup_fbmem();
free_palette_ram();
free_irq(INT_24XX_DSS_IRQ, dispc.fbdev);
enable_interface_clocks(0);
put_dss_clocks();
iounmap(dispc.base);
}

7
drivers/video/omap/dispc.h
View File

@@ -37,9 +37,10 @@ extern void omap_dispc_set_lcd_size(int width, int height);
extern void omap_dispc_enable_lcd_out(int enable);
extern void omap_dispc_enable_digit_out(int enable);
extern int omap_dispc_request_irq(void (*callback)(void *data), void *data);
extern void omap_dispc_free_irq(void);
extern int omap_dispc_request_irq(unsigned long irq_mask,
void (*callback)(void *data), void *data);
extern void omap_dispc_free_irq(unsigned long irq_mask,
void (*callback)(void *data), void *data);
extern const struct lcd_ctrl omap2_int_ctrl;
#endif

2
drivers/video/omap/hwa742.c
View File

@@ -131,7 +131,7 @@ struct {
struct omapfb_device *fbdev;
struct lcd_ctrl_extif *extif;
struct lcd_ctrl *int_ctrl;
const struct lcd_ctrl *int_ctrl;
struct clk *sys_ck;
} hwa742;

202
drivers/video/omap/lcd_2430sdp.c Normal file
View File

@@ -0,0 +1,202 @@
/*
* LCD panel support for the TI 2430SDP board
*
* Copyright (C) 2007 MontaVista
* Author: Hunyue Yau <hyau@mvista.com>
*
* Derived from drivers/video/omap/lcd-apollon.c
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/i2c/twl4030.h>
#include <mach/mux.h>
#include <mach/omapfb.h>
#include <asm/mach-types.h>
#define SDP2430_LCD_PANEL_BACKLIGHT_GPIO 91
#define SDP2430_LCD_PANEL_ENABLE_GPIO 154
#define SDP3430_LCD_PANEL_BACKLIGHT_GPIO 24
#define SDP3430_LCD_PANEL_ENABLE_GPIO 28
static unsigned backlight_gpio;
static unsigned enable_gpio;
#define LCD_PIXCLOCK_MAX 5400 /* freq 5.4 MHz */
#define PM_RECEIVER TWL4030_MODULE_PM_RECEIVER
#define ENABLE_VAUX2_DEDICATED 0x09
#define ENABLE_VAUX2_DEV_GRP 0x20
#define ENABLE_VAUX3_DEDICATED 0x03
#define ENABLE_VAUX3_DEV_GRP 0x20
#define ENABLE_VPLL2_DEDICATED 0x05
#define ENABLE_VPLL2_DEV_GRP 0xE0
#define TWL4030_VPLL2_DEV_GRP 0x33
#define TWL4030_VPLL2_DEDICATED 0x36
#define t2_out(c, r, v) twl4030_i2c_write_u8(c, r, v)
static int sdp2430_panel_init(struct lcd_panel *panel,
struct omapfb_device *fbdev)
{
if (machine_is_omap_3430sdp()) {
enable_gpio = SDP3430_LCD_PANEL_ENABLE_GPIO;
backlight_gpio = SDP3430_LCD_PANEL_BACKLIGHT_GPIO;
} else {
enable_gpio = SDP2430_LCD_PANEL_ENABLE_GPIO;
backlight_gpio = SDP2430_LCD_PANEL_BACKLIGHT_GPIO;
}
gpio_request(enable_gpio, "LCD enable"); /* LCD panel */
gpio_request(backlight_gpio, "LCD bl"); /* LCD backlight */
gpio_direction_output(enable_gpio, 0);
gpio_direction_output(backlight_gpio, 0);
return 0;
}
static void sdp2430_panel_cleanup(struct lcd_panel *panel)
{
gpio_free(backlight_gpio);
gpio_free(enable_gpio);
}
static int sdp2430_panel_enable(struct lcd_panel *panel)
{
u8 ded_val, ded_reg;
u8 grp_val, grp_reg;
if (machine_is_omap_3430sdp()) {
ded_reg = TWL4030_VAUX3_DEDICATED;
ded_val = ENABLE_VAUX3_DEDICATED;
grp_reg = TWL4030_VAUX3_DEV_GRP;
grp_val = ENABLE_VAUX3_DEV_GRP;
if (omap_rev() > OMAP3430_REV_ES1_0) {
t2_out(PM_RECEIVER, ENABLE_VPLL2_DEDICATED,
TWL4030_VPLL2_DEDICATED);
t2_out(PM_RECEIVER, ENABLE_VPLL2_DEV_GRP,
TWL4030_VPLL2_DEV_GRP);
}
} else {
ded_reg = TWL4030_VAUX2_DEDICATED;
ded_val = ENABLE_VAUX2_DEDICATED;
grp_reg = TWL4030_VAUX2_DEV_GRP;
grp_val = ENABLE_VAUX2_DEV_GRP;
}
gpio_set_value(enable_gpio, 1);
gpio_set_value(backlight_gpio, 1);
if (0 != t2_out(PM_RECEIVER, ded_val, ded_reg))
return -EIO;
if (0 != t2_out(PM_RECEIVER, grp_val, grp_reg))
return -EIO;
return 0;
}
static void sdp2430_panel_disable(struct lcd_panel *panel)
{
gpio_set_value(enable_gpio, 0);
gpio_set_value(backlight_gpio, 0);
if (omap_rev() > OMAP3430_REV_ES1_0) {
t2_out(PM_RECEIVER, 0x0, TWL4030_VPLL2_DEDICATED);
t2_out(PM_RECEIVER, 0x0, TWL4030_VPLL2_DEV_GRP);
msleep(4);
}
}
static unsigned long sdp2430_panel_get_caps(struct lcd_panel *panel)
{
return 0;
}
struct lcd_panel sdp2430_panel = {
.name = "sdp2430",
.config = OMAP_LCDC_PANEL_TFT | OMAP_LCDC_INV_VSYNC |
OMAP_LCDC_INV_HSYNC,
.bpp = 16,
.data_lines = 16,
.x_res = 240,
.y_res = 320,
.hsw = 3, /* hsync_len (4) - 1 */
.hfp = 3, /* right_margin (4) - 1 */
.hbp = 39, /* left_margin (40) - 1 */
.vsw = 1, /* vsync_len (2) - 1 */
.vfp = 2, /* lower_margin */
.vbp = 7, /* upper_margin (8) - 1 */
.pixel_clock = LCD_PIXCLOCK_MAX,
.init = sdp2430_panel_init,
.cleanup = sdp2430_panel_cleanup,
.enable = sdp2430_panel_enable,
.disable = sdp2430_panel_disable,
.get_caps = sdp2430_panel_get_caps,
};
static int sdp2430_panel_probe(struct platform_device *pdev)
{
omapfb_register_panel(&sdp2430_panel);
return 0;
}
static int sdp2430_panel_remove(struct platform_device *pdev)
{
return 0;
}
static int sdp2430_panel_suspend(struct platform_device *pdev,
pm_message_t mesg)
{
return 0;
}
static int sdp2430_panel_resume(struct platform_device *pdev)
{
return 0;
}
struct platform_driver sdp2430_panel_driver = {
.probe = sdp2430_panel_probe,
.remove = sdp2430_panel_remove,
.suspend = sdp2430_panel_suspend,
.resume = sdp2430_panel_resume,
.driver = {
.name = "sdp2430_lcd",
.owner = THIS_MODULE,
},
};
static int __init sdp2430_panel_drv_init(void)
{
return platform_driver_register(&sdp2430_panel_driver);
}
static void __exit sdp2430_panel_drv_exit(void)
{
platform_driver_unregister(&sdp2430_panel_driver);
}
module_init(sdp2430_panel_drv_init);
module_exit(sdp2430_panel_drv_exit);

137
drivers/video/omap/lcd_ams_delta.c Normal file
View File

@@ -0,0 +1,137 @@
/*
* Based on drivers/video/omap/lcd_inn1510.c
*
* LCD panel support for the Amstrad E3 (Delta) videophone.
*
* Copyright (C) 2006 Jonathan McDowell <noodles@earth.li>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <mach/board-ams-delta.h>
#include <mach/hardware.h>
#include <mach/omapfb.h>
#define AMS_DELTA_DEFAULT_CONTRAST 112
static int ams_delta_panel_init(struct lcd_panel *panel,
struct omapfb_device *fbdev)
{
return 0;
}
static void ams_delta_panel_cleanup(struct lcd_panel *panel)
{
}
static int ams_delta_panel_enable(struct lcd_panel *panel)
{
ams_delta_latch2_write(AMS_DELTA_LATCH2_LCD_NDISP,
AMS_DELTA_LATCH2_LCD_NDISP);
ams_delta_latch2_write(AMS_DELTA_LATCH2_LCD_VBLEN,
AMS_DELTA_LATCH2_LCD_VBLEN);
omap_writeb(1, OMAP_PWL_CLK_ENABLE);
omap_writeb(AMS_DELTA_DEFAULT_CONTRAST, OMAP_PWL_ENABLE);
return 0;
}
static void ams_delta_panel_disable(struct lcd_panel *panel)
{
ams_delta_latch2_write(AMS_DELTA_LATCH2_LCD_VBLEN, 0);
ams_delta_latch2_write(AMS_DELTA_LATCH2_LCD_NDISP, 0);
}
static unsigned long ams_delta_panel_get_caps(struct lcd_panel *panel)
{
return 0;
}
static struct lcd_panel ams_delta_panel = {
.name = "ams-delta",
.config = 0,
.bpp = 12,
.data_lines = 16,
.x_res = 480,
.y_res = 320,
.pixel_clock = 4687,
.hsw = 3,
.hfp = 1,
.hbp = 1,
.vsw = 1,
.vfp = 0,
.vbp = 0,
.pcd = 0,
.acb = 37,
.init = ams_delta_panel_init,
.cleanup = ams_delta_panel_cleanup,
.enable = ams_delta_panel_enable,
.disable = ams_delta_panel_disable,
.get_caps = ams_delta_panel_get_caps,
};
static int ams_delta_panel_probe(struct platform_device *pdev)
{
omapfb_register_panel(&ams_delta_panel);
return 0;
}
static int ams_delta_panel_remove(struct platform_device *pdev)
{
return 0;
}
static int ams_delta_panel_suspend(struct platform_device *pdev,
pm_message_t mesg)
{
return 0;
}
static int ams_delta_panel_resume(struct platform_device *pdev)
{
return 0;
}
struct platform_driver ams_delta_panel_driver = {
.probe = ams_delta_panel_probe,
.remove = ams_delta_panel_remove,
.suspend = ams_delta_panel_suspend,
.resume = ams_delta_panel_resume,
.driver = {
.name = "lcd_ams_delta",
.owner = THIS_MODULE,
},
};
static int ams_delta_panel_drv_init(void)
{
return platform_driver_register(&ams_delta_panel_driver);
}
static void ams_delta_panel_drv_cleanup(void)
{
platform_driver_unregister(&ams_delta_panel_driver);
}
module_init(ams_delta_panel_drv_init);
module_exit(ams_delta_panel_drv_cleanup);

138
drivers/video/omap/lcd_apollon.c Normal file
View File

@@ -0,0 +1,138 @@
/*
* LCD panel support for the Samsung OMAP2 Apollon board
*
* Copyright (C) 2005,2006 Samsung Electronics
* Author: Kyungmin Park <kyungmin.park@samsung.com>
*
* Derived from drivers/video/omap/lcd-h4.c
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <mach/gpio.h>
#include <mach/mux.h>
#include <mach/omapfb.h>
/* #define USE_35INCH_LCD 1 */
static int apollon_panel_init(struct lcd_panel *panel,
struct omapfb_device *fbdev)
{
/* configure LCD PWR_EN */
omap_cfg_reg(M21_242X_GPIO11);
return 0;
}
static void apollon_panel_cleanup(struct lcd_panel *panel)
{
}
static int apollon_panel_enable(struct lcd_panel *panel)
{
return 0;
}
static void apollon_panel_disable(struct lcd_panel *panel)
{
}
static unsigned long apollon_panel_get_caps(struct lcd_panel *panel)
{
return 0;
}
struct lcd_panel apollon_panel = {
.name = "apollon",
.config = OMAP_LCDC_PANEL_TFT | OMAP_LCDC_INV_VSYNC |
OMAP_LCDC_INV_HSYNC,
.bpp = 16,
.data_lines = 18,
#ifdef USE_35INCH_LCD
.x_res = 240,
.y_res = 320,
.hsw = 2,
.hfp = 3,
.hbp = 9,
.vsw = 4,
.vfp = 3,
.vbp = 5,
#else
.x_res = 480,
.y_res = 272,
.hsw = 41,
.hfp = 2,
.hbp = 2,
.vsw = 10,
.vfp = 2,
.vbp = 2,
#endif
.pixel_clock = 6250,
.init = apollon_panel_init,
.cleanup = apollon_panel_cleanup,
.enable = apollon_panel_enable,
.disable = apollon_panel_disable,
.get_caps = apollon_panel_get_caps,
};
static int apollon_panel_probe(struct platform_device *pdev)
{
omapfb_register_panel(&apollon_panel);
return 0;
}
static int apollon_panel_remove(struct platform_device *pdev)
{
return 0;
}
static int apollon_panel_suspend(struct platform_device *pdev,
pm_message_t mesg)
{
return 0;
}
static int apollon_panel_resume(struct platform_device *pdev)
{
return 0;
}
struct platform_driver apollon_panel_driver = {
.probe = apollon_panel_probe,
.remove = apollon_panel_remove,
.suspend = apollon_panel_suspend,
.resume = apollon_panel_resume,
.driver = {
.name = "apollon_lcd",
.owner = THIS_MODULE,
},
};
static int __init apollon_panel_drv_init(void)
{
return platform_driver_register(&apollon_panel_driver);
}
static void __exit apollon_panel_drv_exit(void)
{
platform_driver_unregister(&apollon_panel_driver);
}
module_init(apollon_panel_drv_init);
module_exit(apollon_panel_drv_exit);

4
drivers/video/omap/lcd_h3.c
View File

@@ -124,12 +124,12 @@ struct platform_driver h3_panel_driver = {
},
};
static int h3_panel_drv_init(void)
static int __init h3_panel_drv_init(void)
{
return platform_driver_register(&h3_panel_driver);
}
static void h3_panel_drv_cleanup(void)
static void __exit h3_panel_drv_cleanup(void)
{
platform_driver_unregister(&h3_panel_driver);
}

4
drivers/video/omap/lcd_h4.c
View File

@@ -102,12 +102,12 @@ static struct platform_driver h4_panel_driver = {
},
};
static int h4_panel_drv_init(void)
static int __init h4_panel_drv_init(void)
{
return platform_driver_register(&h4_panel_driver);
}
static void h4_panel_drv_cleanup(void)
static void __exit h4_panel_drv_cleanup(void)
{
platform_driver_unregister(&h4_panel_driver);
}

4
drivers/video/omap/lcd_inn1510.c
View File

@@ -109,12 +109,12 @@ struct platform_driver innovator1510_panel_driver = {
},
};
static int innovator1510_panel_drv_init(void)
static int __init innovator1510_panel_drv_init(void)
{
return platform_driver_register(&innovator1510_panel_driver);
}
static void innovator1510_panel_drv_cleanup(void)
static void __exit innovator1510_panel_drv_cleanup(void)
{
platform_driver_unregister(&innovator1510_panel_driver);
}

4
drivers/video/omap/lcd_inn1610.c
View File

@@ -133,12 +133,12 @@ struct platform_driver innovator1610_panel_driver = {
},
};
static int innovator1610_panel_drv_init(void)
static int __init innovator1610_panel_drv_init(void)
{
return platform_driver_register(&innovator1610_panel_driver);
}
static void innovator1610_panel_drv_cleanup(void)
static void __exit innovator1610_panel_drv_cleanup(void)
{
platform_driver_unregister(&innovator1610_panel_driver);
}

200
drivers/video/omap/lcd_ldp.c Normal file
View File

@@ -0,0 +1,200 @@
/*
* LCD panel support for the TI LDP board
*
* Copyright (C) 2007 WindRiver
* Author: Stanley Miao <stanley.miao@windriver.com>
*
* Derived from drivers/video/omap/lcd-2430sdp.c
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/i2c/twl4030.h>
#include <mach/gpio.h>
#include <mach/mux.h>
#include <mach/omapfb.h>
#include <asm/mach-types.h>
#define LCD_PANEL_BACKLIGHT_GPIO (15 + OMAP_MAX_GPIO_LINES)
#define LCD_PANEL_ENABLE_GPIO (7 + OMAP_MAX_GPIO_LINES)
#define LCD_PANEL_RESET_GPIO 55
#define LCD_PANEL_QVGA_GPIO 56
#ifdef CONFIG_FB_OMAP_LCD_VGA
#define LCD_XRES 480
#define LCD_YRES 640
#define LCD_PIXCLOCK_MAX 41700
#else
#define LCD_XRES 240
#define LCD_YRES 320
#define LCD_PIXCLOCK_MAX 185186
#endif
#define PM_RECEIVER TWL4030_MODULE_PM_RECEIVER
#define ENABLE_VAUX2_DEDICATED 0x09
#define ENABLE_VAUX2_DEV_GRP 0x20
#define ENABLE_VAUX3_DEDICATED 0x03
#define ENABLE_VAUX3_DEV_GRP 0x20
#define ENABLE_VPLL2_DEDICATED 0x05
#define ENABLE_VPLL2_DEV_GRP 0xE0
#define TWL4030_VPLL2_DEV_GRP 0x33
#define TWL4030_VPLL2_DEDICATED 0x36
#define t2_out(c, r, v) twl4030_i2c_write_u8(c, r, v)
static int ldp_panel_init(struct lcd_panel *panel,
struct omapfb_device *fbdev)
{
gpio_request(LCD_PANEL_RESET_GPIO, "lcd reset");
gpio_request(LCD_PANEL_QVGA_GPIO, "lcd qvga");
gpio_request(LCD_PANEL_ENABLE_GPIO, "lcd panel");
gpio_request(LCD_PANEL_BACKLIGHT_GPIO, "lcd backlight");
gpio_direction_output(LCD_PANEL_QVGA_GPIO, 0);
gpio_direction_output(LCD_PANEL_RESET_GPIO, 0);
gpio_direction_output(LCD_PANEL_ENABLE_GPIO, 0);
gpio_direction_output(LCD_PANEL_BACKLIGHT_GPIO, 0);
#ifdef CONFIG_FB_OMAP_LCD_VGA
gpio_set_value(LCD_PANEL_QVGA_GPIO, 0);
#else
gpio_set_value(LCD_PANEL_QVGA_GPIO, 1);
#endif
gpio_set_value(LCD_PANEL_RESET_GPIO, 1);
return 0;
}
static void ldp_panel_cleanup(struct lcd_panel *panel)
{
gpio_free(LCD_PANEL_BACKLIGHT_GPIO);
gpio_free(LCD_PANEL_ENABLE_GPIO);
gpio_free(LCD_PANEL_QVGA_GPIO);
gpio_free(LCD_PANEL_RESET_GPIO);
}
static int ldp_panel_enable(struct lcd_panel *panel)
{
if (0 != t2_out(PM_RECEIVER, ENABLE_VPLL2_DEDICATED,
TWL4030_VPLL2_DEDICATED))
return -EIO;
if (0 != t2_out(PM_RECEIVER, ENABLE_VPLL2_DEV_GRP,
TWL4030_VPLL2_DEV_GRP))
return -EIO;
gpio_direction_output(LCD_PANEL_ENABLE_GPIO, 1);
gpio_direction_output(LCD_PANEL_BACKLIGHT_GPIO, 1);
if (0 != t2_out(PM_RECEIVER, ENABLE_VAUX3_DEDICATED,
TWL4030_VAUX3_DEDICATED))
return -EIO;
if (0 != t2_out(PM_RECEIVER, ENABLE_VAUX3_DEV_GRP,
TWL4030_VAUX3_DEV_GRP))
return -EIO;
return 0;
}
static void ldp_panel_disable(struct lcd_panel *panel)
{
gpio_direction_output(LCD_PANEL_ENABLE_GPIO, 0);
gpio_direction_output(LCD_PANEL_BACKLIGHT_GPIO, 0);
t2_out(PM_RECEIVER, 0x0, TWL4030_VPLL2_DEDICATED);
t2_out(PM_RECEIVER, 0x0, TWL4030_VPLL2_DEV_GRP);
msleep(4);
}
static unsigned long ldp_panel_get_caps(struct lcd_panel *panel)
{
return 0;
}
struct lcd_panel ldp_panel = {
.name = "ldp",
.config = OMAP_LCDC_PANEL_TFT | OMAP_LCDC_INV_VSYNC |
OMAP_LCDC_INV_HSYNC,
.bpp = 16,
.data_lines = 18,
.x_res = LCD_XRES,
.y_res = LCD_YRES,
.hsw = 3, /* hsync_len (4) - 1 */
.hfp = 3, /* right_margin (4) - 1 */
.hbp = 39, /* left_margin (40) - 1 */
.vsw = 1, /* vsync_len (2) - 1 */
.vfp = 2, /* lower_margin */
.vbp = 7, /* upper_margin (8) - 1 */
.pixel_clock = LCD_PIXCLOCK_MAX,
.init = ldp_panel_init,
.cleanup = ldp_panel_cleanup,
.enable = ldp_panel_enable,
.disable = ldp_panel_disable,
.get_caps = ldp_panel_get_caps,
};
static int ldp_panel_probe(struct platform_device *pdev)
{
omapfb_register_panel(&ldp_panel);
return 0;
}
static int ldp_panel_remove(struct platform_device *pdev)
{
return 0;
}
static int ldp_panel_suspend(struct platform_device *pdev, pm_message_t mesg)
{
return 0;
}
static int ldp_panel_resume(struct platform_device *pdev)
{
return 0;
}
struct platform_driver ldp_panel_driver = {
.probe = ldp_panel_probe,
.remove = ldp_panel_remove,
.suspend = ldp_panel_suspend,
.resume = ldp_panel_resume,
.driver = {
.name = "ldp_lcd",
.owner = THIS_MODULE,
},
};
static int __init ldp_panel_drv_init(void)
{
return platform_driver_register(&ldp_panel_driver);
}
static void __exit ldp_panel_drv_exit(void)
{
platform_driver_unregister(&ldp_panel_driver);
}
module_init(ldp_panel_drv_init);
module_exit(ldp_panel_drv_exit);

625
drivers/video/omap/lcd_mipid.c Normal file
View File

@@ -0,0 +1,625 @@
/*
* LCD driver for MIPI DBI-C / DCS compatible LCDs
*
* Copyright (C) 2006 Nokia Corporation
* Author: Imre Deak <imre.deak@nokia.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/workqueue.h>
#include <linux/spi/spi.h>
#include <mach/omapfb.h>
#include <mach/lcd_mipid.h>
#define MIPID_MODULE_NAME "lcd_mipid"
#define MIPID_CMD_READ_DISP_ID 0x04
#define MIPID_CMD_READ_RED 0x06
#define MIPID_CMD_READ_GREEN 0x07
#define MIPID_CMD_READ_BLUE 0x08
#define MIPID_CMD_READ_DISP_STATUS 0x09
#define MIPID_CMD_RDDSDR 0x0F
#define MIPID_CMD_SLEEP_IN 0x10
#define MIPID_CMD_SLEEP_OUT 0x11
#define MIPID_CMD_DISP_OFF 0x28
#define MIPID_CMD_DISP_ON 0x29
#define MIPID_ESD_CHECK_PERIOD msecs_to_jiffies(5000)
#define to_mipid_device(p) container_of(p, struct mipid_device, \
panel)
struct mipid_device {
int enabled;
int revision;
unsigned int saved_bklight_level;
unsigned long hw_guard_end; /* next value of jiffies
when we can issue the
next sleep in/out command */
unsigned long hw_guard_wait; /* max guard time in jiffies */
struct omapfb_device *fbdev;
struct spi_device *spi;
struct mutex mutex;
struct lcd_panel panel;
struct workqueue_struct *esd_wq;
struct delayed_work esd_work;
void (*esd_check)(struct mipid_device *m);
};
static void mipid_transfer(struct mipid_device *md, int cmd, const u8 *wbuf,
int wlen, u8 *rbuf, int rlen)
{
struct spi_message m;
struct spi_transfer *x, xfer[4];
u16 w;
int r;
BUG_ON(md->spi == NULL);
spi_message_init(&m);
memset(xfer, 0, sizeof(xfer));
x = &xfer[0];
cmd &= 0xff;
x->tx_buf = &cmd;
x->bits_per_word = 9;
x->len = 2;
spi_message_add_tail(x, &m);
if (wlen) {
x++;
x->tx_buf = wbuf;
x->len = wlen;
x->bits_per_word = 9;
spi_message_add_tail(x, &m);
}
if (rlen) {
x++;
x->rx_buf = &w;
x->len = 1;
spi_message_add_tail(x, &m);
if (rlen > 1) {
/* Arrange for the extra clock before the first
* data bit.
*/
x->bits_per_word = 9;
x->len = 2;
x++;
x->rx_buf = &rbuf[1];
x->len = rlen - 1;
spi_message_add_tail(x, &m);
}
}
r = spi_sync(md->spi, &m);
if (r < 0)
dev_dbg(&md->spi->dev, "spi_sync %d\n", r);
if (rlen)
rbuf[0] = w & 0xff;
}
static inline void mipid_cmd(struct mipid_device *md, int cmd)
{
mipid_transfer(md, cmd, NULL, 0, NULL, 0);
}
static inline void mipid_write(struct mipid_device *md,
int reg, const u8 *buf, int len)
{
mipid_transfer(md, reg, buf, len, NULL, 0);
}
static inline void mipid_read(struct mipid_device *md,
int reg, u8 *buf, int len)
{
mipid_transfer(md, reg, NULL, 0, buf, len);
}
static void set_data_lines(struct mipid_device *md, int data_lines)
{
u16 par;
switch (data_lines) {
case 16:
par = 0x150;
break;
case 18:
par = 0x160;
break;
case 24:
par = 0x170;
break;
}
mipid_write(md, 0x3a, (u8 *)&par, 2);
}
static void send_init_string(struct mipid_device *md)
{
u16 initpar[] = { 0x0102, 0x0100, 0x0100 };
mipid_write(md, 0xc2, (u8 *)initpar, sizeof(initpar));
set_data_lines(md, md->panel.data_lines);
}
static void hw_guard_start(struct mipid_device *md, int guard_msec)
{
md->hw_guard_wait = msecs_to_jiffies(guard_msec);
md->hw_guard_end = jiffies + md->hw_guard_wait;
}
static void hw_guard_wait(struct mipid_device *md)
{
unsigned long wait = md->hw_guard_end - jiffies;
if ((long)wait > 0 && wait <= md->hw_guard_wait) {
set_current_state(TASK_UNINTERRUPTIBLE);
schedule_timeout(wait);
}
}
static void set_sleep_mode(struct mipid_device *md, int on)
{
int cmd, sleep_time = 50;
if (on)
cmd = MIPID_CMD_SLEEP_IN;
else
cmd = MIPID_CMD_SLEEP_OUT;
hw_guard_wait(md);
mipid_cmd(md, cmd);
hw_guard_start(md, 120);
/*
* When we enable the panel, it seems we _have_ to sleep
* 120 ms before sending the init string. When disabling the
* panel we'll sleep for the duration of 2 frames, so that the
* controller can still provide the PCLK,HS,VS signals.
*/
if (!on)
sleep_time = 120;
msleep(sleep_time);
}
static void set_display_state(struct mipid_device *md, int enabled)
{
int cmd = enabled ? MIPID_CMD_DISP_ON : MIPID_CMD_DISP_OFF;
mipid_cmd(md, cmd);
}
static int mipid_set_bklight_level(struct lcd_panel *panel, unsigned int level)
{
struct mipid_device *md = to_mipid_device(panel);
struct mipid_platform_data *pd = md->spi->dev.platform_data;
if (pd->get_bklight_max == NULL || pd->set_bklight_level == NULL)
return -ENODEV;
if (level > pd->get_bklight_max(pd))
return -EINVAL;
if (!md->enabled) {
md->saved_bklight_level = level;
return 0;
}
pd->set_bklight_level(pd, level);
return 0;
}
static unsigned int mipid_get_bklight_level(struct lcd_panel *panel)
{
struct mipid_device *md = to_mipid_device(panel);
struct mipid_platform_data *pd = md->spi->dev.platform_data;
if (pd->get_bklight_level == NULL)
return -ENODEV;
return pd->get_bklight_level(pd);
}
static unsigned int mipid_get_bklight_max(struct lcd_panel *panel)
{
struct mipid_device *md = to_mipid_device(panel);
struct mipid_platform_data *pd = md->spi->dev.platform_data;
if (pd->get_bklight_max == NULL)
return -ENODEV;
return pd->get_bklight_max(pd);
}
static unsigned long mipid_get_caps(struct lcd_panel *panel)
{
return OMAPFB_CAPS_SET_BACKLIGHT;
}
static u16 read_first_pixel(struct mipid_device *md)
{
u16 pixel;
u8 red, green, blue;
mutex_lock(&md->mutex);
mipid_read(md, MIPID_CMD_READ_RED, &red, 1);
mipid_read(md, MIPID_CMD_READ_GREEN, &green, 1);
mipid_read(md, MIPID_CMD_READ_BLUE, &blue, 1);
mutex_unlock(&md->mutex);
switch (md->panel.data_lines) {
case 16:
pixel = ((red >> 1) << 11) | (green << 5) | (blue >> 1);
break;
case 24:
/* 24 bit -> 16 bit */
pixel = ((red >> 3) << 11) | ((green >> 2) << 5) |
(blue >> 3);
break;
default:
pixel = 0;
BUG();
}
return pixel;
}
static int mipid_run_test(struct lcd_panel *panel, int test_num)
{
struct mipid_device *md = to_mipid_device(panel);
static const u16 test_values[4] = {
0x0000, 0xffff, 0xaaaa, 0x5555,
};
int i;
if (test_num != MIPID_TEST_RGB_LINES)
return MIPID_TEST_INVALID;
for (i = 0; i < ARRAY_SIZE(test_values); i++) {
int delay;
unsigned long tmo;
omapfb_write_first_pixel(md->fbdev, test_values[i]);
tmo = jiffies + msecs_to_jiffies(100);
delay = 25;
while (1) {
u16 pixel;
msleep(delay);
pixel = read_first_pixel(md);
if (pixel == test_values[i])
break;
if (time_after(jiffies, tmo)) {
dev_err(&md->spi->dev,
"MIPI LCD RGB I/F test failed: "
"expecting %04x, got %04x\n",
test_values[i], pixel);
return MIPID_TEST_FAILED;
}
delay = 10;
}
}
return 0;
}
static void ls041y3_esd_recover(struct mipid_device *md)
{
dev_err(&md->spi->dev, "performing LCD ESD recovery\n");
set_sleep_mode(md, 1);
set_sleep_mode(md, 0);
}
static void ls041y3_esd_check_mode1(struct mipid_device *md)
{
u8 state1, state2;
mipid_read(md, MIPID_CMD_RDDSDR, &state1, 1);
set_sleep_mode(md, 0);
mipid_read(md, MIPID_CMD_RDDSDR, &state2, 1);
dev_dbg(&md->spi->dev, "ESD mode 1 state1 %02x state2 %02x\n",
state1, state2);
/* Each sleep out command will trigger a self diagnostic and flip
* Bit6 if the test passes.
*/
if (!((state1 ^ state2) & (1 << 6)))
ls041y3_esd_recover(md);
}
static void ls041y3_esd_check_mode2(struct mipid_device *md)
{
int i;
u8 rbuf[2];
static const struct {
int cmd;
int wlen;
u16 wbuf[3];
} *rd, rd_ctrl[7] = {
{ 0xb0, 4, { 0x0101, 0x01fe, } },
{ 0xb1, 4, { 0x01de, 0x0121, } },
{ 0xc2, 4, { 0x0100, 0x0100, } },
{ 0xbd, 2, { 0x0100, } },
{ 0xc2, 4, { 0x01fc, 0x0103, } },
{ 0xb4, 0, },
{ 0x00, 0, },
};
rd = rd_ctrl;
for (i = 0; i < 3; i++, rd++)
mipid_write(md, rd->cmd, (u8 *)rd->wbuf, rd->wlen);
udelay(10);
mipid_read(md, rd->cmd, rbuf, 2);
rd++;
for (i = 0; i < 3; i++, rd++) {
udelay(10);
mipid_write(md, rd->cmd, (u8 *)rd->wbuf, rd->wlen);
}
dev_dbg(&md->spi->dev, "ESD mode 2 state %02x\n", rbuf[1]);
if (rbuf[1] == 0x00)
ls041y3_esd_recover(md);
}
static void ls041y3_esd_check(struct mipid_device *md)
{
ls041y3_esd_check_mode1(md);
if (md->revision >= 0x88)
ls041y3_esd_check_mode2(md);
}
static void mipid_esd_start_check(struct mipid_device *md)
{
if (md->esd_check != NULL)
queue_delayed_work(md->esd_wq, &md->esd_work,
MIPID_ESD_CHECK_PERIOD);
}
static void mipid_esd_stop_check(struct mipid_device *md)
{
if (md->esd_check != NULL)
cancel_rearming_delayed_workqueue(md->esd_wq, &md->esd_work);
}
static void mipid_esd_work(struct work_struct *work)
{
struct mipid_device *md = container_of(work, struct mipid_device,
esd_work.work);
mutex_lock(&md->mutex);
md->esd_check(md);
mutex_unlock(&md->mutex);
mipid_esd_start_check(md);
}
static int mipid_enable(struct lcd_panel *panel)
{
struct mipid_device *md = to_mipid_device(panel);
mutex_lock(&md->mutex);
if (md->enabled) {
mutex_unlock(&md->mutex);
return 0;
}
set_sleep_mode(md, 0);
md->enabled = 1;
send_init_string(md);
set_display_state(md, 1);
mipid_set_bklight_level(panel, md->saved_bklight_level);
mipid_esd_start_check(md);
mutex_unlock(&md->mutex);
return 0;
}
static void mipid_disable(struct lcd_panel *panel)
{
struct mipid_device *md = to_mipid_device(panel);
/*
* A final ESD work might be called before returning,
* so do this without holding the lock.
*/
mipid_esd_stop_check(md);
mutex_lock(&md->mutex);
if (!md->enabled) {
mutex_unlock(&md->mutex);
return;
}
md->saved_bklight_level = mipid_get_bklight_level(panel);
mipid_set_bklight_level(panel, 0);
set_display_state(md, 0);
set_sleep_mode(md, 1);
md->enabled = 0;
mutex_unlock(&md->mutex);
}
static int panel_enabled(struct mipid_device *md)
{
u32 disp_status;
int enabled;
mipid_read(md, MIPID_CMD_READ_DISP_STATUS, (u8 *)&disp_status, 4);
disp_status = __be32_to_cpu(disp_status);
enabled = (disp_status & (1 << 17)) && (disp_status & (1 << 10));
dev_dbg(&md->spi->dev,
"LCD panel %senabled by bootloader (status 0x%04x)\n",
enabled ? "" : "not ", disp_status);
return enabled;
}
static int mipid_init(struct lcd_panel *panel,
struct omapfb_device *fbdev)
{
struct mipid_device *md = to_mipid_device(panel);
md->fbdev = fbdev;
md->esd_wq = create_singlethread_workqueue("mipid_esd");
if (md->esd_wq == NULL) {
dev_err(&md->spi->dev, "can't create ESD workqueue\n");
return -ENOMEM;
}
INIT_DELAYED_WORK(&md->esd_work, mipid_esd_work);
mutex_init(&md->mutex);
md->enabled = panel_enabled(md);
if (md->enabled)
mipid_esd_start_check(md);
else
md->saved_bklight_level = mipid_get_bklight_level(panel);
return 0;
}
static void mipid_cleanup(struct lcd_panel *panel)
{
struct mipid_device *md = to_mipid_device(panel);
if (md->enabled)
mipid_esd_stop_check(md);
destroy_workqueue(md->esd_wq);
}
static struct lcd_panel mipid_panel = {
.config = OMAP_LCDC_PANEL_TFT,
.bpp = 16,
.x_res = 800,
.y_res = 480,
.pixel_clock = 21940,
.hsw = 50,
.hfp = 20,
.hbp = 15,
.vsw = 2,
.vfp = 1,
.vbp = 3,
.init = mipid_init,
.cleanup = mipid_cleanup,
.enable = mipid_enable,
.disable = mipid_disable,
.get_caps = mipid_get_caps,
.set_bklight_level = mipid_set_bklight_level,
.get_bklight_level = mipid_get_bklight_level,
.get_bklight_max = mipid_get_bklight_max,
.run_test = mipid_run_test,
};
static int mipid_detect(struct mipid_device *md)
{
struct mipid_platform_data *pdata;
u8 display_id[3];
pdata = md->spi->dev.platform_data;
if (pdata == NULL) {
dev_err(&md->spi->dev, "missing platform data\n");
return -ENOENT;
}
mipid_read(md, MIPID_CMD_READ_DISP_ID, display_id, 3);
dev_dbg(&md->spi->dev, "MIPI display ID: %02x%02x%02x\n",
display_id[0], display_id[1], display_id[2]);
switch (display_id[0]) {
case 0x45:
md->panel.name = "lph8923";
break;
case 0x83:
md->panel.name = "ls041y3";
md->esd_check = ls041y3_esd_check;
break;
default:
md->panel.name = "unknown";
dev_err(&md->spi->dev, "invalid display ID\n");
return -ENODEV;
}
md->revision = display_id[1];
md->panel.data_lines = pdata->data_lines;
pr_info("omapfb: %s rev %02x LCD detected, %d data lines\n",
md->panel.name, md->revision, md->panel.data_lines);
return 0;
}
static int mipid_spi_probe(struct spi_device *spi)
{
struct mipid_device *md;
int r;
md = kzalloc(sizeof(*md), GFP_KERNEL);
if (md == NULL) {
dev_err(&spi->dev, "out of memory\n");
return -ENOMEM;
}
spi->mode = SPI_MODE_0;
md->spi = spi;
dev_set_drvdata(&spi->dev, md);
md->panel = mipid_panel;
r = mipid_detect(md);
if (r < 0)
return r;
omapfb_register_panel(&md->panel);
return 0;
}
static int mipid_spi_remove(struct spi_device *spi)
{
struct mipid_device *md = dev_get_drvdata(&spi->dev);
mipid_disable(&md->panel);
kfree(md);
return 0;
}
static struct spi_driver mipid_spi_driver = {
.driver = {
.name = MIPID_MODULE_NAME,
.bus = &spi_bus_type,
.owner = THIS_MODULE,
},
.probe = mipid_spi_probe,
.remove = __devexit_p(mipid_spi_remove),
};
static int mipid_drv_init(void)
{
spi_register_driver(&mipid_spi_driver);
return 0;
}
module_init(mipid_drv_init);
static void mipid_drv_cleanup(void)
{
spi_unregister_driver(&mipid_spi_driver);
}
module_exit(mipid_drv_cleanup);
MODULE_DESCRIPTION("MIPI display driver");
MODULE_LICENSE("GPL");

191
drivers/video/omap/lcd_omap2evm.c Normal file
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/*
* LCD panel support for the MISTRAL OMAP2EVM board
*
* Author: Arun C <arunedarath@mistralsolutions.com>
*
* Derived from drivers/video/omap/lcd_omap3evm.c
* Derived from drivers/video/omap/lcd-apollon.c
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/i2c/twl4030.h>
#include <mach/mux.h>
#include <mach/omapfb.h>
#include <asm/mach-types.h>
#define LCD_PANEL_ENABLE_GPIO 154
#define LCD_PANEL_LR 128
#define LCD_PANEL_UD 129
#define LCD_PANEL_INI 152
#define LCD_PANEL_QVGA 148
#define LCD_PANEL_RESB 153
#define TWL_LED_LEDEN 0x00
#define TWL_PWMA_PWMAON 0x00
#define TWL_PWMA_PWMAOFF 0x01
static unsigned int bklight_level;
static int omap2evm_panel_init(struct lcd_panel *panel,
struct omapfb_device *fbdev)
{
gpio_request(LCD_PANEL_ENABLE_GPIO, "LCD enable");
gpio_request(LCD_PANEL_LR, "LCD lr");
gpio_request(LCD_PANEL_UD, "LCD ud");
gpio_request(LCD_PANEL_INI, "LCD ini");
gpio_request(LCD_PANEL_QVGA, "LCD qvga");
gpio_request(LCD_PANEL_RESB, "LCD resb");
gpio_direction_output(LCD_PANEL_ENABLE_GPIO, 1);
gpio_direction_output(LCD_PANEL_RESB, 1);
gpio_direction_output(LCD_PANEL_INI, 1);
gpio_direction_output(LCD_PANEL_QVGA, 0);
gpio_direction_output(LCD_PANEL_LR, 1);
gpio_direction_output(LCD_PANEL_UD, 1);
twl4030_i2c_write_u8(TWL4030_MODULE_LED, 0x11, TWL_LED_LEDEN);
twl4030_i2c_write_u8(TWL4030_MODULE_PWMA, 0x01, TWL_PWMA_PWMAON);
twl4030_i2c_write_u8(TWL4030_MODULE_PWMA, 0x02, TWL_PWMA_PWMAOFF);
bklight_level = 100;
return 0;
}
static void omap2evm_panel_cleanup(struct lcd_panel *panel)
{
gpio_free(LCD_PANEL_RESB);
gpio_free(LCD_PANEL_QVGA);
gpio_free(LCD_PANEL_INI);
gpio_free(LCD_PANEL_UD);
gpio_free(LCD_PANEL_LR);
gpio_free(LCD_PANEL_ENABLE_GPIO);
}
static int omap2evm_panel_enable(struct lcd_panel *panel)
{
gpio_set_value(LCD_PANEL_ENABLE_GPIO, 0);
return 0;
}
static void omap2evm_panel_disable(struct lcd_panel *panel)
{
gpio_set_value(LCD_PANEL_ENABLE_GPIO, 1);
}
static unsigned long omap2evm_panel_get_caps(struct lcd_panel *panel)
{
return 0;
}
static int omap2evm_bklight_setlevel(struct lcd_panel *panel,
unsigned int level)
{
u8 c;
if ((level >= 0) && (level <= 100)) {
c = (125 * (100 - level)) / 100 + 2;
twl4030_i2c_write_u8(TWL4030_MODULE_PWMA, c, TWL_PWMA_PWMAOFF);
bklight_level = level;
}
return 0;
}
static unsigned int omap2evm_bklight_getlevel(struct lcd_panel *panel)
{
return bklight_level;
}
static unsigned int omap2evm_bklight_getmaxlevel(struct lcd_panel *panel)
{
return 100;
}
struct lcd_panel omap2evm_panel = {
.name = "omap2evm",
.config = OMAP_LCDC_PANEL_TFT | OMAP_LCDC_INV_VSYNC |
OMAP_LCDC_INV_HSYNC,
.bpp = 16,
.data_lines = 18,
.x_res = 480,
.y_res = 640,
.hsw = 3,
.hfp = 0,
.hbp = 28,
.vsw = 2,
.vfp = 1,
.vbp = 0,
.pixel_clock = 20000,
.init = omap2evm_panel_init,
.cleanup = omap2evm_panel_cleanup,
.enable = omap2evm_panel_enable,
.disable = omap2evm_panel_disable,
.get_caps = omap2evm_panel_get_caps,
.set_bklight_level = omap2evm_bklight_setlevel,
.get_bklight_level = omap2evm_bklight_getlevel,
.get_bklight_max = omap2evm_bklight_getmaxlevel,
};
static int omap2evm_panel_probe(struct platform_device *pdev)
{
omapfb_register_panel(&omap2evm_panel);
return 0;
}
static int omap2evm_panel_remove(struct platform_device *pdev)
{
return 0;
}
static int omap2evm_panel_suspend(struct platform_device *pdev,
pm_message_t mesg)
{
return 0;
}
static int omap2evm_panel_resume(struct platform_device *pdev)
{
return 0;
}
struct platform_driver omap2evm_panel_driver = {
.probe = omap2evm_panel_probe,
.remove = omap2evm_panel_remove,
.suspend = omap2evm_panel_suspend,
.resume = omap2evm_panel_resume,
.driver = {
.name = "omap2evm_lcd",
.owner = THIS_MODULE,
},
};
static int __init omap2evm_panel_drv_init(void)
{
return platform_driver_register(&omap2evm_panel_driver);
}
static void __exit omap2evm_panel_drv_exit(void)
{
platform_driver_unregister(&omap2evm_panel_driver);
}
module_init(omap2evm_panel_drv_init);
module_exit(omap2evm_panel_drv_exit);

130
drivers/video/omap/lcd_omap3beagle.c Normal file
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/*
* LCD panel support for the TI OMAP3 Beagle board
*
* Author: Koen Kooi <koen@openembedded.org>
*
* Derived from drivers/video/omap/lcd-omap3evm.c
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/i2c/twl4030.h>
#include <mach/mux.h>
#include <mach/omapfb.h>
#include <asm/mach-types.h>
#define LCD_PANEL_ENABLE_GPIO 170
static int omap3beagle_panel_init(struct lcd_panel *panel,
struct omapfb_device *fbdev)
{
gpio_request(LCD_PANEL_ENABLE_GPIO, "LCD enable");
return 0;
}
static void omap3beagle_panel_cleanup(struct lcd_panel *panel)
{
gpio_free(LCD_PANEL_ENABLE_GPIO);
}
static int omap3beagle_panel_enable(struct lcd_panel *panel)
{
gpio_set_value(LCD_PANEL_ENABLE_GPIO, 1);
return 0;
}
static void omap3beagle_panel_disable(struct lcd_panel *panel)
{
gpio_set_value(LCD_PANEL_ENABLE_GPIO, 0);
}
static unsigned long omap3beagle_panel_get_caps(struct lcd_panel *panel)
{
return 0;
}
struct lcd_panel omap3beagle_panel = {
.name = "omap3beagle",
.config = OMAP_LCDC_PANEL_TFT,
.bpp = 16,
.data_lines = 24,
.x_res = 1024,
.y_res = 768,
.hsw = 3, /* hsync_len (4) - 1 */
.hfp = 3, /* right_margin (4) - 1 */
.hbp = 39, /* left_margin (40) - 1 */
.vsw = 1, /* vsync_len (2) - 1 */
.vfp = 2, /* lower_margin */
.vbp = 7, /* upper_margin (8) - 1 */
.pixel_clock = 64000,
.init = omap3beagle_panel_init,
.cleanup = omap3beagle_panel_cleanup,
.enable = omap3beagle_panel_enable,
.disable = omap3beagle_panel_disable,
.get_caps = omap3beagle_panel_get_caps,
};
static int omap3beagle_panel_probe(struct platform_device *pdev)
{
omapfb_register_panel(&omap3beagle_panel);
return 0;
}
static int omap3beagle_panel_remove(struct platform_device *pdev)
{
return 0;
}
static int omap3beagle_panel_suspend(struct platform_device *pdev,
pm_message_t mesg)
{
return 0;
}
static int omap3beagle_panel_resume(struct platform_device *pdev)
{
return 0;
}
struct platform_driver omap3beagle_panel_driver = {
.probe = omap3beagle_panel_probe,
.remove = omap3beagle_panel_remove,
.suspend = omap3beagle_panel_suspend,
.resume = omap3beagle_panel_resume,
.driver = {
.name = "omap3beagle_lcd",
.owner = THIS_MODULE,
},
};
static int __init omap3beagle_panel_drv_init(void)
{
return platform_driver_register(&omap3beagle_panel_driver);
}
static void __exit omap3beagle_panel_drv_exit(void)
{
platform_driver_unregister(&omap3beagle_panel_driver);
}
module_init(omap3beagle_panel_drv_init);
module_exit(omap3beagle_panel_drv_exit);

192
drivers/video/omap/lcd_omap3evm.c Normal file
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/*
* LCD panel support for the TI OMAP3 EVM board
*
* Author: Steve Sakoman <steve@sakoman.com>
*
* Derived from drivers/video/omap/lcd-apollon.c
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/i2c/twl4030.h>
#include <mach/mux.h>
#include <mach/omapfb.h>
#include <asm/mach-types.h>
#define LCD_PANEL_ENABLE_GPIO 153
#define LCD_PANEL_LR 2
#define LCD_PANEL_UD 3
#define LCD_PANEL_INI 152
#define LCD_PANEL_QVGA 154
#define LCD_PANEL_RESB 155
#define ENABLE_VDAC_DEDICATED 0x03
#define ENABLE_VDAC_DEV_GRP 0x20
#define ENABLE_VPLL2_DEDICATED 0x05
#define ENABLE_VPLL2_DEV_GRP 0xE0
#define TWL_LED_LEDEN 0x00
#define TWL_PWMA_PWMAON 0x00
#define TWL_PWMA_PWMAOFF 0x01
static unsigned int bklight_level;
static int omap3evm_panel_init(struct lcd_panel *panel,
struct omapfb_device *fbdev)
{
gpio_request(LCD_PANEL_LR, "LCD lr");
gpio_request(LCD_PANEL_UD, "LCD ud");
gpio_request(LCD_PANEL_INI, "LCD ini");
gpio_request(LCD_PANEL_RESB, "LCD resb");
gpio_request(LCD_PANEL_QVGA, "LCD qvga");
gpio_direction_output(LCD_PANEL_RESB, 1);
gpio_direction_output(LCD_PANEL_INI, 1);
gpio_direction_output(LCD_PANEL_QVGA, 0);
gpio_direction_output(LCD_PANEL_LR, 1);
gpio_direction_output(LCD_PANEL_UD, 1);
twl4030_i2c_write_u8(TWL4030_MODULE_LED, 0x11, TWL_LED_LEDEN);
twl4030_i2c_write_u8(TWL4030_MODULE_PWMA, 0x01, TWL_PWMA_PWMAON);
twl4030_i2c_write_u8(TWL4030_MODULE_PWMA, 0x02, TWL_PWMA_PWMAOFF);
bklight_level = 100;
return 0;
}
static void omap3evm_panel_cleanup(struct lcd_panel *panel)
{
gpio_free(LCD_PANEL_QVGA);
gpio_free(LCD_PANEL_RESB);
gpio_free(LCD_PANEL_INI);
gpio_free(LCD_PANEL_UD);
gpio_free(LCD_PANEL_LR);
}
static int omap3evm_panel_enable(struct lcd_panel *panel)
{
gpio_set_value(LCD_PANEL_ENABLE_GPIO, 0);
return 0;
}
static void omap3evm_panel_disable(struct lcd_panel *panel)
{
gpio_set_value(LCD_PANEL_ENABLE_GPIO, 1);
}
static unsigned long omap3evm_panel_get_caps(struct lcd_panel *panel)
{
return 0;
}
static int omap3evm_bklight_setlevel(struct lcd_panel *panel,
unsigned int level)
{
u8 c;
if ((level >= 0) && (level <= 100)) {
c = (125 * (100 - level)) / 100 + 2;
twl4030_i2c_write_u8(TWL4030_MODULE_PWMA, c, TWL_PWMA_PWMAOFF);
bklight_level = level;
}
return 0;
}
static unsigned int omap3evm_bklight_getlevel(struct lcd_panel *panel)
{
return bklight_level;
}
static unsigned int omap3evm_bklight_getmaxlevel(struct lcd_panel *panel)
{
return 100;
}
struct lcd_panel omap3evm_panel = {
.name = "omap3evm",
.config = OMAP_LCDC_PANEL_TFT | OMAP_LCDC_INV_VSYNC |
OMAP_LCDC_INV_HSYNC,
.bpp = 16,
.data_lines = 18,
.x_res = 480,
.y_res = 640,
.hsw = 3, /* hsync_len (4) - 1 */
.hfp = 3, /* right_margin (4) - 1 */
.hbp = 39, /* left_margin (40) - 1 */
.vsw = 1, /* vsync_len (2) - 1 */
.vfp = 2, /* lower_margin */
.vbp = 7, /* upper_margin (8) - 1 */
.pixel_clock = 26000,
.init = omap3evm_panel_init,
.cleanup = omap3evm_panel_cleanup,
.enable = omap3evm_panel_enable,
.disable = omap3evm_panel_disable,
.get_caps = omap3evm_panel_get_caps,
.set_bklight_level = omap3evm_bklight_setlevel,
.get_bklight_level = omap3evm_bklight_getlevel,
.get_bklight_max = omap3evm_bklight_getmaxlevel,
};
static int omap3evm_panel_probe(struct platform_device *pdev)
{
omapfb_register_panel(&omap3evm_panel);
return 0;
}
static int omap3evm_panel_remove(struct platform_device *pdev)
{
return 0;
}
static int omap3evm_panel_suspend(struct platform_device *pdev,
pm_message_t mesg)
{
return 0;
}
static int omap3evm_panel_resume(struct platform_device *pdev)
{
return 0;
}
struct platform_driver omap3evm_panel_driver = {
.probe = omap3evm_panel_probe,
.remove = omap3evm_panel_remove,
.suspend = omap3evm_panel_suspend,
.resume = omap3evm_panel_resume,
.driver = {
.name = "omap3evm_lcd",
.owner = THIS_MODULE,
},
};
static int __init omap3evm_panel_drv_init(void)
{
return platform_driver_register(&omap3evm_panel_driver);
}
static void __exit omap3evm_panel_drv_exit(void)
{
platform_driver_unregister(&omap3evm_panel_driver);
}
module_init(omap3evm_panel_drv_init);
module_exit(omap3evm_panel_drv_exit);

4
drivers/video/omap/lcd_osk.c
View File

@@ -127,12 +127,12 @@ struct platform_driver osk_panel_driver = {
},
};
static int osk_panel_drv_init(void)
static int __init osk_panel_drv_init(void)
{
return platform_driver_register(&osk_panel_driver);
}
static void osk_panel_drv_cleanup(void)
static void __exit osk_panel_drv_cleanup(void)
{
platform_driver_unregister(&osk_panel_driver);
}

179
drivers/video/omap/lcd_overo.c Normal file
View File

@@ -0,0 +1,179 @@
/*
* LCD panel support for the Gumstix Overo
*
* Author: Steve Sakoman <steve@sakoman.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/i2c/twl4030.h>
#include <mach/gpio.h>
#include <mach/mux.h>
#include <mach/omapfb.h>
#include <asm/mach-types.h>
#define LCD_ENABLE 144
static int overo_panel_init(struct lcd_panel *panel,
struct omapfb_device *fbdev)
{
if ((gpio_request(LCD_ENABLE, "LCD_ENABLE") == 0) &&
(gpio_direction_output(LCD_ENABLE, 1) == 0))
gpio_export(LCD_ENABLE, 0);
else
printk(KERN_ERR "could not obtain gpio for LCD_ENABLE\n");
return 0;
}
static void overo_panel_cleanup(struct lcd_panel *panel)
{
gpio_free(LCD_ENABLE);
}
static int overo_panel_enable(struct lcd_panel *panel)
{
gpio_set_value(LCD_ENABLE, 1);
return 0;
}
static void overo_panel_disable(struct lcd_panel *panel)
{
gpio_set_value(LCD_ENABLE, 0);
}
static unsigned long overo_panel_get_caps(struct lcd_panel *panel)
{
return 0;
}
struct lcd_panel overo_panel = {
.name = "overo",
.config = OMAP_LCDC_PANEL_TFT,
.bpp = 16,
.data_lines = 24,
#if defined CONFIG_FB_OMAP_031M3R
/* 640 x 480 @ 60 Hz Reduced blanking VESA CVT 0.31M3-R */
.x_res = 640,
.y_res = 480,
.hfp = 48,
.hsw = 32,
.hbp = 80,
.vfp = 3,
.vsw = 4,
.vbp = 7,
.pixel_clock = 23500,
#elif defined CONFIG_FB_OMAP_048M3R
/* 800 x 600 @ 60 Hz Reduced blanking VESA CVT 0.48M3-R */
.x_res = 800,
.y_res = 600,
.hfp = 48,
.hsw = 32,
.hbp = 80,
.vfp = 3,
.vsw = 4,
.vbp = 11,
.pixel_clock = 35500,
#elif defined CONFIG_FB_OMAP_079M3R
/* 1024 x 768 @ 60 Hz Reduced blanking VESA CVT 0.79M3-R */
.x_res = 1024,
.y_res = 768,
.hfp = 48,
.hsw = 32,
.hbp = 80,
.vfp = 3,
.vsw = 4,
.vbp = 15,
.pixel_clock = 56000,
#elif defined CONFIG_FB_OMAP_092M9R
/* 1280 x 720 @ 60 Hz Reduced blanking VESA CVT 0.92M9-R */
.x_res = 1280,
.y_res = 720,
.hfp = 48,
.hsw = 32,
.hbp = 80,
.vfp = 3,
.vsw = 5,
.vbp = 13,
.pixel_clock = 64000,
#else
/* use 640 x 480 if no config option */
/* 640 x 480 @ 60 Hz Reduced blanking VESA CVT 0.31M3-R */
.x_res = 640,
.y_res = 480,
.hfp = 48,
.hsw = 32,
.hbp = 80,
.vfp = 3,
.vsw = 4,
.vbp = 7,
.pixel_clock = 23500,
#endif
.init = overo_panel_init,
.cleanup = overo_panel_cleanup,
.enable = overo_panel_enable,
.disable = overo_panel_disable,
.get_caps = overo_panel_get_caps,
};
static int overo_panel_probe(struct platform_device *pdev)
{
omapfb_register_panel(&overo_panel);
return 0;
}
static int overo_panel_remove(struct platform_device *pdev)
{
/* omapfb does not have unregister_panel */
return 0;
}
static struct platform_driver overo_panel_driver = {
.probe = overo_panel_probe,
.remove = overo_panel_remove,
.driver = {
.name = "overo_lcd",
.owner = THIS_MODULE,
},
};
static int __init overo_panel_drv_init(void)
{
return platform_driver_register(&overo_panel_driver);
}
static void __exit overo_panel_drv_exit(void)
{
platform_driver_unregister(&overo_panel_driver);
}
module_init(overo_panel_drv_init);
module_exit(overo_panel_drv_exit);

4
drivers/video/omap/lcd_palmte.c
View File

@@ -108,12 +108,12 @@ struct platform_driver palmte_panel_driver = {
},
};
static int palmte_panel_drv_init(void)
static int __init palmte_panel_drv_init(void)
{
return platform_driver_register(&palmte_panel_driver);
}
static void palmte_panel_drv_cleanup(void)
static void __exit palmte_panel_drv_cleanup(void)
{
platform_driver_unregister(&palmte_panel_driver);
}

4
drivers/video/omap/lcd_palmtt.c
View File

@@ -113,12 +113,12 @@ struct platform_driver palmtt_panel_driver = {
},
};
static int palmtt_panel_drv_init(void)
static int __init palmtt_panel_drv_init(void)
{
return platform_driver_register(&palmtt_panel_driver);
}
static void palmtt_panel_drv_cleanup(void)
static void __exit palmtt_panel_drv_cleanup(void)
{
platform_driver_unregister(&palmtt_panel_driver);
}

4
drivers/video/omap/lcd_palmz71.c
View File

@@ -109,12 +109,12 @@ struct platform_driver palmz71_panel_driver = {
},
};
static int palmz71_panel_drv_init(void)
static int __init palmz71_panel_drv_init(void)
{
return platform_driver_register(&palmz71_panel_driver);
}
static void palmz71_panel_drv_cleanup(void)
static void __exit palmz71_panel_drv_cleanup(void)
{
platform_driver_unregister(&palmz71_panel_driver);
}

64
drivers/video/omap/omapfb_main.c
View File

@@ -67,6 +67,7 @@ static struct caps_table_struct ctrl_caps[] = {
{ OMAPFB_CAPS_WINDOW_PIXEL_DOUBLE, "pixel double window" },
{ OMAPFB_CAPS_WINDOW_SCALE, "scale window" },
{ OMAPFB_CAPS_WINDOW_OVERLAY, "overlay window" },
{ OMAPFB_CAPS_WINDOW_ROTATE, "rotate window" },
{ OMAPFB_CAPS_SET_BACKLIGHT, "backlight setting" },
};
@@ -215,6 +216,15 @@ static int ctrl_change_mode(struct fb_info *fbi)
offset, var->xres_virtual,
plane->info.pos_x, plane->info.pos_y,
var->xres, var->yres, plane->color_mode);
if (r < 0)
return r;
if (fbdev->ctrl->set_rotate != NULL) {
r = fbdev->ctrl->set_rotate(var->rotate);
if (r < 0)
return r;
}
if (fbdev->ctrl->set_scale != NULL)
r = fbdev->ctrl->set_scale(plane->idx,
var->xres, var->yres,
@@ -554,7 +564,6 @@ static int set_fb_var(struct fb_info *fbi,
var->xoffset = var->xres_virtual - var->xres;
if (var->yres + var->yoffset > var->yres_virtual)
var->yoffset = var->yres_virtual - var->yres;
line_size = var->xres * bpp / 8;
if (plane->color_mode == OMAPFB_COLOR_RGB444) {
var->red.offset = 8; var->red.length = 4;
@@ -600,7 +609,7 @@ static void omapfb_rotate(struct fb_info *fbi, int rotate)
struct omapfb_device *fbdev = plane->fbdev;
omapfb_rqueue_lock(fbdev);
if (cpu_is_omap15xx() && rotate != fbi->var.rotate) {
if (rotate != fbi->var.rotate) {
struct fb_var_screeninfo *new_var = &fbdev->new_var;
memcpy(new_var, &fbi->var, sizeof(*new_var));
@@ -707,28 +716,42 @@ int omapfb_update_window_async(struct fb_info *fbi,
void (*callback)(void *),
void *callback_data)
{
int xres, yres;
struct omapfb_plane_struct *plane = fbi->par;
struct omapfb_device *fbdev = plane->fbdev;
struct fb_var_screeninfo *var;
struct fb_var_screeninfo *var = &fbi->var;
var = &fbi->var;
if (win->x >= var->xres || win->y >= var->yres ||
win->out_x > var->xres || win->out_y >= var->yres)
switch (var->rotate) {
case 0:
case 180:
xres = fbdev->panel->x_res;
yres = fbdev->panel->y_res;
break;
case 90:
case 270:
xres = fbdev->panel->y_res;
yres = fbdev->panel->x_res;
break;
default:
return -EINVAL;
}
if (win->x >= xres || win->y >= yres ||
win->out_x > xres || win->out_y > yres)
return -EINVAL;
if (!fbdev->ctrl->update_window ||
fbdev->ctrl->get_update_mode() != OMAPFB_MANUAL_UPDATE)
return -ENODEV;
if (win->x + win->width >= var->xres)
win->width = var->xres - win->x;
if (win->y + win->height >= var->yres)
win->height = var->yres - win->y;
/* The out sizes should be cropped to the LCD size */
if (win->out_x + win->out_width > fbdev->panel->x_res)
win->out_width = fbdev->panel->x_res - win->out_x;
if (win->out_y + win->out_height > fbdev->panel->y_res)
win->out_height = fbdev->panel->y_res - win->out_y;
if (win->x + win->width > xres)
win->width = xres - win->x;
if (win->y + win->height > yres)
win->height = yres - win->y;
if (win->out_x + win->out_width > xres)
win->out_width = xres - win->out_x;
if (win->out_y + win->out_height > yres)
win->out_height = yres - win->out_y;
if (!win->width || !win->height || !win->out_width || !win->out_height)
return 0;
@@ -1699,8 +1722,8 @@ static int omapfb_do_probe(struct platform_device *pdev,
pr_info("omapfb: configured for panel %s\n", fbdev->panel->name);
def_vxres = def_vxres ? : fbdev->panel->x_res;
def_vyres = def_vyres ? : fbdev->panel->y_res;
def_vxres = def_vxres ? def_vxres : fbdev->panel->x_res;
def_vyres = def_vyres ? def_vyres : fbdev->panel->y_res;
init_state++;
@@ -1822,8 +1845,8 @@ static int omapfb_suspend(struct platform_device *pdev, pm_message_t mesg)
{
struct omapfb_device *fbdev = platform_get_drvdata(pdev);
omapfb_blank(FB_BLANK_POWERDOWN, fbdev->fb_info[0]);
if (fbdev != NULL)
omapfb_blank(FB_BLANK_POWERDOWN, fbdev->fb_info[0]);
return 0;
}
@@ -1832,7 +1855,8 @@ static int omapfb_resume(struct platform_device *pdev)
{
struct omapfb_device *fbdev = platform_get_drvdata(pdev);
omapfb_blank(FB_BLANK_UNBLANK, fbdev->fb_info[0]);
if (fbdev != NULL)
omapfb_blank(FB_BLANK_UNBLANK, fbdev->fb_info[0]);
return 0;
}

7
drivers/video/omap/rfbi.c
View File

@@ -57,6 +57,7 @@
#define DISPC_BASE 0x48050400
#define DISPC_CONTROL 0x0040
#define DISPC_IRQ_FRAMEMASK 0x0001
static struct {
void __iomem *base;
@@ -553,7 +554,9 @@ static int rfbi_init(struct omapfb_device *fbdev)
l = (0x01 << 2);
rfbi_write_reg(RFBI_CONTROL, l);
if ((r = omap_dispc_request_irq(rfbi_dma_callback, NULL)) < 0) {
r = omap_dispc_request_irq(DISPC_IRQ_FRAMEMASK, rfbi_dma_callback,
NULL);
if (r < 0) {
dev_err(fbdev->dev, "can't get DISPC irq\n");
rfbi_enable_clocks(0);
return r;
@@ -570,7 +573,7 @@ static int rfbi_init(struct omapfb_device *fbdev)
static void rfbi_cleanup(void)
{
omap_dispc_free_irq();
omap_dispc_free_irq(DISPC_IRQ_FRAMEMASK, rfbi_dma_callback, NULL);
rfbi_put_clocks();
iounmap(rfbi.base);
}

12
drivers/video/platinumfb.c
View File

@@ -223,10 +223,14 @@ static int platinumfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
static inline int platinum_vram_reqd(int video_mode, int color_mode)
{
return vmode_attrs[video_mode-1].vres *
(vmode_attrs[video_mode-1].hres * (1<<color_mode) +
((video_mode == VMODE_832_624_75) &&
(color_mode > CMODE_8)) ? 0x10 : 0x20) + 0x1000;
int baseval = vmode_attrs[video_mode-1].hres * (1<<color_mode);
if ((video_mode == VMODE_832_624_75) && (color_mode > CMODE_8))
baseval += 0x10;
else
baseval += 0x20;
return vmode_attrs[video_mode-1].vres * baseval + 0x1000;
}
#define STORE_D2(a, d) { \

2
drivers/video/s3c-fb.c
View File

@@ -1036,7 +1036,7 @@ static int s3c_fb_resume(struct platform_device *pdev)
static struct platform_driver s3c_fb_driver = {
.probe = s3c_fb_probe,
.remove = s3c_fb_remove,
.remove = __devexit_p(s3c_fb_remove),
.suspend = s3c_fb_suspend,
.resume = s3c_fb_resume,
.driver = {

6
drivers/video/s3c2410fb.c
View File

@@ -369,7 +369,9 @@ static void s3c2410fb_activate_var(struct fb_info *info)
void __iomem *regs = fbi->io;
int type = fbi->regs.lcdcon1 & S3C2410_LCDCON1_TFT;
struct fb_var_screeninfo *var = &info->var;
int clkdiv = s3c2410fb_calc_pixclk(fbi, var->pixclock) / 2;
int clkdiv;
clkdiv = DIV_ROUND_UP(s3c2410fb_calc_pixclk(fbi, var->pixclock), 2);
dprintk("%s: var->xres = %d\n", __func__, var->xres);
dprintk("%s: var->yres = %d\n", __func__, var->yres);
@@ -1119,7 +1121,7 @@ int __init s3c2410fb_init(void)
int ret = platform_driver_register(&s3c2410fb_driver);
if (ret == 0)
ret = platform_driver_register(&s3c2412fb_driver);;
ret = platform_driver_register(&s3c2412fb_driver);
return ret;
}

290
drivers/video/sh_mobile_lcdcfb.c
View File

@@ -14,6 +14,7 @@
#include <linux/mm.h>
#include <linux/fb.h>
#include <linux/clk.h>
#include <linux/pm_runtime.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/interrupt.h>
@@ -22,35 +23,8 @@
#include <asm/atomic.h>
#define PALETTE_NR 16
struct sh_mobile_lcdc_priv;
struct sh_mobile_lcdc_chan {
struct sh_mobile_lcdc_priv *lcdc;
unsigned long *reg_offs;
unsigned long ldmt1r_value;
unsigned long enabled; /* ME and SE in LDCNT2R */
struct sh_mobile_lcdc_chan_cfg cfg;
u32 pseudo_palette[PALETTE_NR];
struct fb_info *info;
dma_addr_t dma_handle;
struct fb_deferred_io defio;
struct scatterlist *sglist;
unsigned long frame_end;
wait_queue_head_t frame_end_wait;
};
struct sh_mobile_lcdc_priv {
void __iomem *base;
int irq;
#ifdef CONFIG_HAVE_CLK
atomic_t clk_usecnt;
struct clk *dot_clk;
struct clk *clk;
#endif
unsigned long lddckr;
struct sh_mobile_lcdc_chan ch[2];
int started;
};
#define SIDE_B_OFFSET 0x1000
#define MIRROR_OFFSET 0x2000
/* shared registers */
#define _LDDCKR 0x410
@@ -59,17 +33,30 @@ struct sh_mobile_lcdc_priv {
#define _LDSR 0x46c
#define _LDCNT1R 0x470
#define _LDCNT2R 0x474
#define _LDRCNTR 0x478
#define _LDDDSR 0x47c
#define _LDDWD0R 0x800
#define _LDDRDR 0x840
#define _LDDWAR 0x900
#define _LDDRAR 0x904
/* shared registers and their order for context save/restore */
static int lcdc_shared_regs[] = {
_LDDCKR,
_LDDCKSTPR,
_LDINTR,
_LDDDSR,
_LDCNT1R,
_LDCNT2R,
};
#define NR_SHARED_REGS ARRAY_SIZE(lcdc_shared_regs)
/* per-channel registers */
enum { LDDCKPAT1R, LDDCKPAT2R, LDMT1R, LDMT2R, LDMT3R, LDDFR, LDSM1R,
LDSM2R, LDSA1R, LDMLSR, LDHCNR, LDHSYNR, LDVLNR, LDVSYNR, LDPMR };
LDSM2R, LDSA1R, LDMLSR, LDHCNR, LDHSYNR, LDVLNR, LDVSYNR, LDPMR,
NR_CH_REGS };
static unsigned long lcdc_offs_mainlcd[] = {
static unsigned long lcdc_offs_mainlcd[NR_CH_REGS] = {
[LDDCKPAT1R] = 0x400,
[LDDCKPAT2R] = 0x404,
[LDMT1R] = 0x418,
@@ -87,7 +74,7 @@ static unsigned long lcdc_offs_mainlcd[] = {
[LDPMR] = 0x460,
};
static unsigned long lcdc_offs_sublcd[] = {
static unsigned long lcdc_offs_sublcd[NR_CH_REGS] = {
[LDDCKPAT1R] = 0x408,
[LDDCKPAT2R] = 0x40c,
[LDMT1R] = 0x600,
@@ -110,12 +97,80 @@ static unsigned long lcdc_offs_sublcd[] = {
#define DISPLAY_BEU 0x00000008
#define LCDC_ENABLE 0x00000001
#define LDINTR_FE 0x00000400
#define LDINTR_VSE 0x00000200
#define LDINTR_VEE 0x00000100
#define LDINTR_FS 0x00000004
#define LDINTR_VSS 0x00000002
#define LDINTR_VES 0x00000001
#define LDRCNTR_SRS 0x00020000
#define LDRCNTR_SRC 0x00010000
#define LDRCNTR_MRS 0x00000002
#define LDRCNTR_MRC 0x00000001
struct sh_mobile_lcdc_priv;
struct sh_mobile_lcdc_chan {
struct sh_mobile_lcdc_priv *lcdc;
unsigned long *reg_offs;
unsigned long ldmt1r_value;
unsigned long enabled; /* ME and SE in LDCNT2R */
struct sh_mobile_lcdc_chan_cfg cfg;
u32 pseudo_palette[PALETTE_NR];
unsigned long saved_ch_regs[NR_CH_REGS];
struct fb_info *info;
dma_addr_t dma_handle;
struct fb_deferred_io defio;
struct scatterlist *sglist;
unsigned long frame_end;
unsigned long pan_offset;
unsigned long new_pan_offset;
wait_queue_head_t frame_end_wait;
};
struct sh_mobile_lcdc_priv {
void __iomem *base;
int irq;
atomic_t hw_usecnt;
struct device *dev;
struct clk *dot_clk;
unsigned long lddckr;
struct sh_mobile_lcdc_chan ch[2];
unsigned long saved_shared_regs[NR_SHARED_REGS];
int started;
};
static bool banked(int reg_nr)
{
switch (reg_nr) {
case LDMT1R:
case LDMT2R:
case LDMT3R:
case LDDFR:
case LDSM1R:
case LDSA1R:
case LDMLSR:
case LDHCNR:
case LDHSYNR:
case LDVLNR:
case LDVSYNR:
return true;
}
return false;
}
static void lcdc_write_chan(struct sh_mobile_lcdc_chan *chan,
int reg_nr, unsigned long data)
{
iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr]);
if (banked(reg_nr))
iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] +
SIDE_B_OFFSET);
}
static void lcdc_write_chan_mirror(struct sh_mobile_lcdc_chan *chan,
int reg_nr, unsigned long data)
{
iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] +
MIRROR_OFFSET);
}
static unsigned long lcdc_read_chan(struct sh_mobile_lcdc_chan *chan,
@@ -156,6 +211,7 @@ static void lcdc_sys_write_index(void *handle, unsigned long data)
lcdc_write(ch->lcdc, _LDDWD0R, data | 0x10000000);
lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
lcdc_write(ch->lcdc, _LDDWAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
}
static void lcdc_sys_write_data(void *handle, unsigned long data)
@@ -165,6 +221,7 @@ static void lcdc_sys_write_data(void *handle, unsigned long data)
lcdc_write(ch->lcdc, _LDDWD0R, data | 0x11000000);
lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
lcdc_write(ch->lcdc, _LDDWAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
}
static unsigned long lcdc_sys_read_data(void *handle)
@@ -175,8 +232,9 @@ static unsigned long lcdc_sys_read_data(void *handle)
lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
lcdc_write(ch->lcdc, _LDDRAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
udelay(1);
lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
return lcdc_read(ch->lcdc, _LDDRDR) & 0xffff;
return lcdc_read(ch->lcdc, _LDDRDR) & 0x3ffff;
}
struct sh_mobile_lcdc_sys_bus_ops sh_mobile_lcdc_sys_bus_ops = {
@@ -185,11 +243,10 @@ struct sh_mobile_lcdc_sys_bus_ops sh_mobile_lcdc_sys_bus_ops = {
lcdc_sys_read_data,
};
#ifdef CONFIG_HAVE_CLK
static void sh_mobile_lcdc_clk_on(struct sh_mobile_lcdc_priv *priv)
{
if (atomic_inc_and_test(&priv->clk_usecnt)) {
clk_enable(priv->clk);
if (atomic_inc_and_test(&priv->hw_usecnt)) {
pm_runtime_get_sync(priv->dev);
if (priv->dot_clk)
clk_enable(priv->dot_clk);
}
@@ -197,16 +254,12 @@ static void sh_mobile_lcdc_clk_on(struct sh_mobile_lcdc_priv *priv)
static void sh_mobile_lcdc_clk_off(struct sh_mobile_lcdc_priv *priv)
{
if (atomic_sub_return(1, &priv->clk_usecnt) == -1) {
if (atomic_sub_return(1, &priv->hw_usecnt) == -1) {
if (priv->dot_clk)
clk_disable(priv->dot_clk);
clk_disable(priv->clk);
pm_runtime_put(priv->dev);
}
}
#else
static void sh_mobile_lcdc_clk_on(struct sh_mobile_lcdc_priv *priv) {}
static void sh_mobile_lcdc_clk_off(struct sh_mobile_lcdc_priv *priv) {}
#endif
static int sh_mobile_lcdc_sginit(struct fb_info *info,
struct list_head *pagelist)
@@ -255,30 +308,52 @@ static irqreturn_t sh_mobile_lcdc_irq(int irq, void *data)
struct sh_mobile_lcdc_priv *priv = data;
struct sh_mobile_lcdc_chan *ch;
unsigned long tmp;
unsigned long ldintr;
int is_sub;
int k;
/* acknowledge interrupt */
tmp = lcdc_read(priv, _LDINTR);
tmp &= 0xffffff00; /* mask in high 24 bits */
tmp |= 0x000000ff ^ LDINTR_FS; /* status in low 8 */
ldintr = tmp = lcdc_read(priv, _LDINTR);
/*
* disable further VSYNC End IRQs, preserve all other enabled IRQs,
* write 0 to bits 0-6 to ack all triggered IRQs.
*/
tmp &= 0xffffff00 & ~LDINTR_VEE;
lcdc_write(priv, _LDINTR, tmp);
/* figure out if this interrupt is for main or sub lcd */
is_sub = (lcdc_read(priv, _LDSR) & (1 << 10)) ? 1 : 0;
/* wake up channel and disable clocks*/
/* wake up channel and disable clocks */
for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
ch = &priv->ch[k];
if (!ch->enabled)
continue;
if (is_sub == lcdc_chan_is_sublcd(ch)) {
ch->frame_end = 1;
wake_up(&ch->frame_end_wait);
/* Frame Start */
if (ldintr & LDINTR_FS) {
if (is_sub == lcdc_chan_is_sublcd(ch)) {
ch->frame_end = 1;
wake_up(&ch->frame_end_wait);
sh_mobile_lcdc_clk_off(priv);
sh_mobile_lcdc_clk_off(priv);
}
}
/* VSYNC End */
if (ldintr & LDINTR_VES) {
unsigned long ldrcntr = lcdc_read(priv, _LDRCNTR);
/* Set the source address for the next refresh */
lcdc_write_chan_mirror(ch, LDSA1R, ch->dma_handle +
ch->new_pan_offset);
if (lcdc_chan_is_sublcd(ch))
lcdc_write(ch->lcdc, _LDRCNTR,
ldrcntr ^ LDRCNTR_SRS);
else
lcdc_write(ch->lcdc, _LDRCNTR,
ldrcntr ^ LDRCNTR_MRS);
ch->pan_offset = ch->new_pan_offset;
}
}
@@ -520,7 +595,6 @@ static void sh_mobile_lcdc_stop(struct sh_mobile_lcdc_priv *priv)
board_cfg = &ch->cfg.board_cfg;
if (board_cfg->display_off)
board_cfg->display_off(board_cfg->board_data);
}
/* stop the lcdc */
@@ -579,9 +653,6 @@ static int sh_mobile_lcdc_setup_clocks(struct platform_device *pdev,
int clock_source,
struct sh_mobile_lcdc_priv *priv)
{
#ifdef CONFIG_HAVE_CLK
char clk_name[8];
#endif
char *str;
int icksel;
@@ -595,25 +666,21 @@ static int sh_mobile_lcdc_setup_clocks(struct platform_device *pdev,
priv->lddckr = icksel << 16;
#ifdef CONFIG_HAVE_CLK
atomic_set(&priv->clk_usecnt, -1);
snprintf(clk_name, sizeof(clk_name), "lcdc%d", pdev->id);
priv->clk = clk_get(&pdev->dev, clk_name);
if (IS_ERR(priv->clk)) {
dev_err(&pdev->dev, "cannot get clock \"%s\"\n", clk_name);
return PTR_ERR(priv->clk);
}
if (str) {
priv->dot_clk = clk_get(&pdev->dev, str);
if (IS_ERR(priv->dot_clk)) {
dev_err(&pdev->dev, "cannot get dot clock %s\n", str);
clk_put(priv->clk);
return PTR_ERR(priv->dot_clk);
}
}
#endif
atomic_set(&priv->hw_usecnt, -1);
/* Runtime PM support involves two step for this driver:
* 1) Enable Runtime PM
* 2) Force Runtime PM Resume since hardware is accessed from probe()
*/
pm_runtime_enable(priv->dev);
pm_runtime_resume(priv->dev);
return 0;
}
@@ -646,6 +713,9 @@ static struct fb_fix_screeninfo sh_mobile_lcdc_fix = {
.type = FB_TYPE_PACKED_PIXELS,
.visual = FB_VISUAL_TRUECOLOR,
.accel = FB_ACCEL_NONE,
.xpanstep = 0,
.ypanstep = 1,
.ywrapstep = 0,
};
static void sh_mobile_lcdc_fillrect(struct fb_info *info,
@@ -669,13 +739,38 @@ static void sh_mobile_lcdc_imageblit(struct fb_info *info,
sh_mobile_lcdc_deferred_io_touch(info);
}
static int sh_mobile_fb_pan_display(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct sh_mobile_lcdc_chan *ch = info->par;
if (info->var.xoffset == var->xoffset &&
info->var.yoffset == var->yoffset)
return 0; /* No change, do nothing */
ch->new_pan_offset = (var->yoffset * info->fix.line_length) +
(var->xoffset * (info->var.bits_per_pixel / 8));
if (ch->new_pan_offset != ch->pan_offset) {
unsigned long ldintr;
ldintr = lcdc_read(ch->lcdc, _LDINTR);
ldintr |= LDINTR_VEE;
lcdc_write(ch->lcdc, _LDINTR, ldintr);
sh_mobile_lcdc_deferred_io_touch(info);
}
return 0;
}
static struct fb_ops sh_mobile_lcdc_ops = {
.owner = THIS_MODULE,
.fb_setcolreg = sh_mobile_lcdc_setcolreg,
.fb_read = fb_sys_read,
.fb_write = fb_sys_write,
.fb_fillrect = sh_mobile_lcdc_fillrect,
.fb_copyarea = sh_mobile_lcdc_copyarea,
.fb_imageblit = sh_mobile_lcdc_imageblit,
.fb_pan_display = sh_mobile_fb_pan_display,
};
static int sh_mobile_lcdc_set_bpp(struct fb_var_screeninfo *var, int bpp)
@@ -731,9 +826,59 @@ static int sh_mobile_lcdc_resume(struct device *dev)
return sh_mobile_lcdc_start(platform_get_drvdata(pdev));
}
static int sh_mobile_lcdc_runtime_suspend(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct sh_mobile_lcdc_priv *p = platform_get_drvdata(pdev);
struct sh_mobile_lcdc_chan *ch;
int k, n;
/* save per-channel registers */
for (k = 0; k < ARRAY_SIZE(p->ch); k++) {
ch = &p->ch[k];
if (!ch->enabled)
continue;
for (n = 0; n < NR_CH_REGS; n++)
ch->saved_ch_regs[n] = lcdc_read_chan(ch, n);
}
/* save shared registers */
for (n = 0; n < NR_SHARED_REGS; n++)
p->saved_shared_regs[n] = lcdc_read(p, lcdc_shared_regs[n]);
/* turn off LCDC hardware */
lcdc_write(p, _LDCNT1R, 0);
return 0;
}
static int sh_mobile_lcdc_runtime_resume(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct sh_mobile_lcdc_priv *p = platform_get_drvdata(pdev);
struct sh_mobile_lcdc_chan *ch;
int k, n;
/* restore per-channel registers */
for (k = 0; k < ARRAY_SIZE(p->ch); k++) {
ch = &p->ch[k];
if (!ch->enabled)
continue;
for (n = 0; n < NR_CH_REGS; n++)
lcdc_write_chan(ch, n, ch->saved_ch_regs[n]);
}
/* restore shared registers */
for (n = 0; n < NR_SHARED_REGS; n++)
lcdc_write(p, lcdc_shared_regs[n], p->saved_shared_regs[n]);
return 0;
}
static struct dev_pm_ops sh_mobile_lcdc_dev_pm_ops = {
.suspend = sh_mobile_lcdc_suspend,
.resume = sh_mobile_lcdc_resume,
.runtime_suspend = sh_mobile_lcdc_runtime_suspend,
.runtime_resume = sh_mobile_lcdc_runtime_resume,
};
static int sh_mobile_lcdc_remove(struct platform_device *pdev);
@@ -778,6 +923,7 @@ static int __init sh_mobile_lcdc_probe(struct platform_device *pdev)
}
priv->irq = i;
priv->dev = &pdev->dev;
platform_set_drvdata(pdev, priv);
pdata = pdev->dev.platform_data;
@@ -792,6 +938,8 @@ static int __init sh_mobile_lcdc_probe(struct platform_device *pdev)
goto err1;
}
init_waitqueue_head(&priv->ch[i].frame_end_wait);
priv->ch[j].pan_offset = 0;
priv->ch[j].new_pan_offset = 0;
switch (pdata->ch[i].chan) {
case LCDC_CHAN_MAINLCD:
@@ -834,7 +982,9 @@ static int __init sh_mobile_lcdc_probe(struct platform_device *pdev)
info = priv->ch[i].info;
info->fbops = &sh_mobile_lcdc_ops;
info->var.xres = info->var.xres_virtual = cfg->lcd_cfg.xres;
info->var.yres = info->var.yres_virtual = cfg->lcd_cfg.yres;
info->var.yres = cfg->lcd_cfg.yres;
/* Default Y virtual resolution is 2x panel size */
info->var.yres_virtual = info->var.yres * 2;
info->var.width = cfg->lcd_size_cfg.width;
info->var.height = cfg->lcd_size_cfg.height;
info->var.activate = FB_ACTIVATE_NOW;
@@ -844,7 +994,8 @@ static int __init sh_mobile_lcdc_probe(struct platform_device *pdev)
info->fix = sh_mobile_lcdc_fix;
info->fix.line_length = cfg->lcd_cfg.xres * (cfg->bpp / 8);
info->fix.smem_len = info->fix.line_length * cfg->lcd_cfg.yres;
info->fix.smem_len = info->fix.line_length *
info->var.yres_virtual;
buf = dma_alloc_coherent(&pdev->dev, info->fix.smem_len,
&priv->ch[i].dma_handle, GFP_KERNEL);
@@ -947,11 +1098,10 @@ static int sh_mobile_lcdc_remove(struct platform_device *pdev)
framebuffer_release(info);
}
#ifdef CONFIG_HAVE_CLK
if (priv->dot_clk)
clk_put(priv->dot_clk);
clk_put(priv->clk);
#endif
pm_runtime_disable(priv->dev);
if (priv->base)
iounmap(priv->base);

4
drivers/video/sis/sis_main.c
View File

@@ -698,8 +698,8 @@ sisfb_search_refresh_rate(struct sis_video_info *ivideo, unsigned int rate, int
rate, sisfb_vrate[i].refresh);
ivideo->rate_idx = sisfb_vrate[i].idx;
ivideo->refresh_rate = sisfb_vrate[i].refresh;
} else if(((rate - sisfb_vrate[i-1].refresh) <= 2)
&& (sisfb_vrate[i].idx != 1)) {
} else if((sisfb_vrate[i].idx != 1) &&
((rate - sisfb_vrate[i-1].refresh) <= 2)) {
DPRINTK("sisfb: Adjusting rate from %d down to %d\n",
rate, sisfb_vrate[i-1].refresh);
ivideo->rate_idx = sisfb_vrate[i-1].idx;

2
drivers/video/sis/vstruct.h
View File

@@ -342,7 +342,7 @@ struct SiS_Private
unsigned short SiS_RY4COE;
unsigned short SiS_LCDHDES;
unsigned short SiS_LCDVDES;
unsigned short SiS_DDC_Port;
SISIOADDRESS SiS_DDC_Port;
unsigned short SiS_DDC_Index;
unsigned short SiS_DDC_Data;
unsigned short SiS_DDC_NData;

2
drivers/video/tmiofb.c
View File

@@ -974,7 +974,7 @@ static int tmiofb_resume(struct platform_device *dev)
{
struct fb_info *info = platform_get_drvdata(dev);
struct mfd_cell *cell = dev->dev.platform_data;
int retval;
int retval = 0;
acquire_console_sem();

611
drivers/video/via/accel.c
View File

@@ -20,229 +20,430 @@
*/
#include "global.h"
void viafb_init_accel(void)
static int hw_bitblt_1(void __iomem *engine, u8 op, u32 width, u32 height,
u8 dst_bpp, u32 dst_addr, u32 dst_pitch, u32 dst_x, u32 dst_y,
u32 *src_mem, u32 src_addr, u32 src_pitch, u32 src_x, u32 src_y,
u32 fg_color, u32 bg_color, u8 fill_rop)
{
viaparinfo->fbmem_free -= CURSOR_SIZE;
viaparinfo->cursor_start = viaparinfo->fbmem_free;
viaparinfo->fbmem_used += CURSOR_SIZE;
u32 ge_cmd = 0, tmp, i;
/* Reverse 8*1024 memory space for cursor image */
viaparinfo->fbmem_free -= (CURSOR_SIZE + VQ_SIZE);
viaparinfo->VQ_start = viaparinfo->fbmem_free;
viaparinfo->VQ_end = viaparinfo->VQ_start + VQ_SIZE - 1;
viaparinfo->fbmem_used += (CURSOR_SIZE + VQ_SIZE); }
void viafb_init_2d_engine(void)
{
u32 dwVQStartAddr, dwVQEndAddr;
u32 dwVQLen, dwVQStartL, dwVQEndL, dwVQStartEndH;
/* init 2D engine regs to reset 2D engine */
writel(0x0, viaparinfo->io_virt + VIA_REG_GEMODE);
writel(0x0, viaparinfo->io_virt + VIA_REG_SRCPOS);
writel(0x0, viaparinfo->io_virt + VIA_REG_DSTPOS);
writel(0x0, viaparinfo->io_virt + VIA_REG_DIMENSION);
writel(0x0, viaparinfo->io_virt + VIA_REG_PATADDR);
writel(0x0, viaparinfo->io_virt + VIA_REG_FGCOLOR);
writel(0x0, viaparinfo->io_virt + VIA_REG_BGCOLOR);
writel(0x0, viaparinfo->io_virt + VIA_REG_CLIPTL);
writel(0x0, viaparinfo->io_virt + VIA_REG_CLIPBR);
writel(0x0, viaparinfo->io_virt + VIA_REG_OFFSET);
writel(0x0, viaparinfo->io_virt + VIA_REG_KEYCONTROL);
writel(0x0, viaparinfo->io_virt + VIA_REG_SRCBASE);
writel(0x0, viaparinfo->io_virt + VIA_REG_DSTBASE);
writel(0x0, viaparinfo->io_virt + VIA_REG_PITCH);
writel(0x0, viaparinfo->io_virt + VIA_REG_MONOPAT1);
/* Init AGP and VQ regs */
switch (viaparinfo->chip_info->gfx_chip_name) {
case UNICHROME_K8M890:
case UNICHROME_P4M900:
writel(0x00100000, viaparinfo->io_virt + VIA_REG_CR_TRANSET);
writel(0x680A0000, viaparinfo->io_virt + VIA_REG_CR_TRANSPACE);
writel(0x02000000, viaparinfo->io_virt + VIA_REG_CR_TRANSPACE);
break;
default:
writel(0x00100000, viaparinfo->io_virt + VIA_REG_TRANSET);
writel(0x00000000, viaparinfo->io_virt + VIA_REG_TRANSPACE);
writel(0x00333004, viaparinfo->io_virt + VIA_REG_TRANSPACE);
writel(0x60000000, viaparinfo->io_virt + VIA_REG_TRANSPACE);
writel(0x61000000, viaparinfo->io_virt + VIA_REG_TRANSPACE);
writel(0x62000000, viaparinfo->io_virt + VIA_REG_TRANSPACE);
writel(0x63000000, viaparinfo->io_virt + VIA_REG_TRANSPACE);
writel(0x64000000, viaparinfo->io_virt + VIA_REG_TRANSPACE);
writel(0x7D000000, viaparinfo->io_virt + VIA_REG_TRANSPACE);
writel(0xFE020000, viaparinfo->io_virt + VIA_REG_TRANSET);
writel(0x00000000, viaparinfo->io_virt + VIA_REG_TRANSPACE);
break;
if (!op || op > 3) {
printk(KERN_WARNING "hw_bitblt_1: Invalid operation: %d\n", op);
return -EINVAL;
}
if (viaparinfo->VQ_start != 0) {
/* Enable VQ */
dwVQStartAddr = viaparinfo->VQ_start;
dwVQEndAddr = viaparinfo->VQ_end;
dwVQStartL = 0x50000000 | (dwVQStartAddr & 0xFFFFFF);
dwVQEndL = 0x51000000 | (dwVQEndAddr & 0xFFFFFF);
dwVQStartEndH = 0x52000000 |
((dwVQStartAddr & 0xFF000000) >> 24) |
((dwVQEndAddr & 0xFF000000) >> 16);
dwVQLen = 0x53000000 | (VQ_SIZE >> 3);
switch (viaparinfo->chip_info->gfx_chip_name) {
case UNICHROME_K8M890:
case UNICHROME_P4M900:
dwVQStartL |= 0x20000000;
dwVQEndL |= 0x20000000;
dwVQStartEndH |= 0x20000000;
dwVQLen |= 0x20000000;
break;
default:
break;
if (op != VIA_BITBLT_FILL && !src_mem && src_addr == dst_addr) {
if (src_x < dst_x) {
ge_cmd |= 0x00008000;
src_x += width - 1;
dst_x += width - 1;
}
switch (viaparinfo->chip_info->gfx_chip_name) {
case UNICHROME_K8M890:
case UNICHROME_P4M900:
writel(0x00100000,
viaparinfo->io_virt + VIA_REG_CR_TRANSET);
writel(dwVQStartEndH,
viaparinfo->io_virt + VIA_REG_CR_TRANSPACE);
writel(dwVQStartL,
viaparinfo->io_virt + VIA_REG_CR_TRANSPACE);
writel(dwVQEndL,
viaparinfo->io_virt + VIA_REG_CR_TRANSPACE);
writel(dwVQLen,
viaparinfo->io_virt + VIA_REG_CR_TRANSPACE);
writel(0x74301001,
viaparinfo->io_virt + VIA_REG_CR_TRANSPACE);
writel(0x00000000,
viaparinfo->io_virt + VIA_REG_CR_TRANSPACE);
break;
default:
writel(0x00FE0000,
viaparinfo->io_virt + VIA_REG_TRANSET);
writel(0x080003FE,
viaparinfo->io_virt + VIA_REG_TRANSPACE);
writel(0x0A00027C,
viaparinfo->io_virt + VIA_REG_TRANSPACE);
writel(0x0B000260,
viaparinfo->io_virt + VIA_REG_TRANSPACE);
writel(0x0C000274,
viaparinfo->io_virt + VIA_REG_TRANSPACE);
writel(0x0D000264,
viaparinfo->io_virt + VIA_REG_TRANSPACE);
writel(0x0E000000,
viaparinfo->io_virt + VIA_REG_TRANSPACE);
writel(0x0F000020,
viaparinfo->io_virt + VIA_REG_TRANSPACE);
writel(0x1000027E,
viaparinfo->io_virt + VIA_REG_TRANSPACE);
writel(0x110002FE,
viaparinfo->io_virt + VIA_REG_TRANSPACE);
writel(0x200F0060,
viaparinfo->io_virt + VIA_REG_TRANSPACE);
writel(0x00000006,
viaparinfo->io_virt + VIA_REG_TRANSPACE);
writel(0x40008C0F,
viaparinfo->io_virt + VIA_REG_TRANSPACE);
writel(0x44000000,
viaparinfo->io_virt + VIA_REG_TRANSPACE);
writel(0x45080C04,
viaparinfo->io_virt + VIA_REG_TRANSPACE);
writel(0x46800408,
viaparinfo->io_virt + VIA_REG_TRANSPACE);
writel(dwVQStartEndH,
viaparinfo->io_virt + VIA_REG_TRANSPACE);
writel(dwVQStartL,
viaparinfo->io_virt + VIA_REG_TRANSPACE);
writel(dwVQEndL,
viaparinfo->io_virt + VIA_REG_TRANSPACE);
writel(dwVQLen,
viaparinfo->io_virt + VIA_REG_TRANSPACE);
break;
}
} else {
/* Disable VQ */
switch (viaparinfo->chip_info->gfx_chip_name) {
case UNICHROME_K8M890:
case UNICHROME_P4M900:
writel(0x00100000,
viaparinfo->io_virt + VIA_REG_CR_TRANSET);
writel(0x74301000,
viaparinfo->io_virt + VIA_REG_CR_TRANSPACE);
break;
default:
writel(0x00FE0000,
viaparinfo->io_virt + VIA_REG_TRANSET);
writel(0x00000004,
viaparinfo->io_virt + VIA_REG_TRANSPACE);
writel(0x40008C0F,
viaparinfo->io_virt + VIA_REG_TRANSPACE);
writel(0x44000000,
viaparinfo->io_virt + VIA_REG_TRANSPACE);
writel(0x45080C04,
viaparinfo->io_virt + VIA_REG_TRANSPACE);
writel(0x46800408,
viaparinfo->io_virt + VIA_REG_TRANSPACE);
break;
if (src_y < dst_y) {
ge_cmd |= 0x00004000;
src_y += height - 1;
dst_y += height - 1;
}
}
viafb_set_2d_color_depth(viaparinfo->bpp);
if (op == VIA_BITBLT_FILL) {
switch (fill_rop) {
case 0x00: /* blackness */
case 0x5A: /* pattern inversion */
case 0xF0: /* pattern copy */
case 0xFF: /* whiteness */
break;
default:
printk(KERN_WARNING "hw_bitblt_1: Invalid fill rop: "
"%u\n", fill_rop);
return -EINVAL;
}
}
writel(0x0, viaparinfo->io_virt + VIA_REG_SRCBASE);
writel(0x0, viaparinfo->io_virt + VIA_REG_DSTBASE);
writel(VIA_PITCH_ENABLE |
(((viaparinfo->hres *
viaparinfo->bpp >> 3) >> 3) | (((viaparinfo->hres *
viaparinfo->
bpp >> 3) >> 3) << 16)),
viaparinfo->io_virt + VIA_REG_PITCH);
}
void viafb_set_2d_color_depth(int bpp)
{
u32 dwGEMode;
dwGEMode = readl(viaparinfo->io_virt + 0x04) & 0xFFFFFCFF;
switch (bpp) {
switch (dst_bpp) {
case 8:
tmp = 0x00000000;
break;
case 16:
dwGEMode |= VIA_GEM_16bpp;
tmp = 0x00000100;
break;
case 32:
dwGEMode |= VIA_GEM_32bpp;
tmp = 0x00000300;
break;
default:
dwGEMode |= VIA_GEM_8bpp;
printk(KERN_WARNING "hw_bitblt_1: Unsupported bpp %d\n",
dst_bpp);
return -EINVAL;
}
writel(tmp, engine + 0x04);
if (op != VIA_BITBLT_FILL) {
if (src_x & (op == VIA_BITBLT_MONO ? 0xFFFF8000 : 0xFFFFF000)
|| src_y & 0xFFFFF000) {
printk(KERN_WARNING "hw_bitblt_1: Unsupported source "
"x/y %d %d\n", src_x, src_y);
return -EINVAL;
}
tmp = src_x | (src_y << 16);
writel(tmp, engine + 0x08);
}
if (dst_x & 0xFFFFF000 || dst_y & 0xFFFFF000) {
printk(KERN_WARNING "hw_bitblt_1: Unsupported destination x/y "
"%d %d\n", dst_x, dst_y);
return -EINVAL;
}
tmp = dst_x | (dst_y << 16);
writel(tmp, engine + 0x0C);
if ((width - 1) & 0xFFFFF000 || (height - 1) & 0xFFFFF000) {
printk(KERN_WARNING "hw_bitblt_1: Unsupported width/height "
"%d %d\n", width, height);
return -EINVAL;
}
tmp = (width - 1) | ((height - 1) << 16);
writel(tmp, engine + 0x10);
if (op != VIA_BITBLT_COLOR)
writel(fg_color, engine + 0x18);
if (op == VIA_BITBLT_MONO)
writel(bg_color, engine + 0x1C);
if (op != VIA_BITBLT_FILL) {
tmp = src_mem ? 0 : src_addr;
if (dst_addr & 0xE0000007) {
printk(KERN_WARNING "hw_bitblt_1: Unsupported source "
"address %X\n", tmp);
return -EINVAL;
}
tmp >>= 3;
writel(tmp, engine + 0x30);
}
if (dst_addr & 0xE0000007) {
printk(KERN_WARNING "hw_bitblt_1: Unsupported destination "
"address %X\n", dst_addr);
return -EINVAL;
}
tmp = dst_addr >> 3;
writel(tmp, engine + 0x34);
if (op == VIA_BITBLT_FILL)
tmp = 0;
else
tmp = src_pitch;
if (tmp & 0xFFFFC007 || dst_pitch & 0xFFFFC007) {
printk(KERN_WARNING "hw_bitblt_1: Unsupported pitch %X %X\n",
tmp, dst_pitch);
return -EINVAL;
}
tmp = (tmp >> 3) | (dst_pitch << (16 - 3));
writel(tmp, engine + 0x38);
if (op == VIA_BITBLT_FILL)
ge_cmd |= fill_rop << 24 | 0x00002000 | 0x00000001;
else {
ge_cmd |= 0xCC000000; /* ROP=SRCCOPY */
if (src_mem)
ge_cmd |= 0x00000040;
if (op == VIA_BITBLT_MONO)
ge_cmd |= 0x00000002 | 0x00000100 | 0x00020000;
else
ge_cmd |= 0x00000001;
}
writel(ge_cmd, engine);
if (op == VIA_BITBLT_FILL || !src_mem)
return 0;
tmp = (width * height * (op == VIA_BITBLT_MONO ? 1 : (dst_bpp >> 3)) +
3) >> 2;
for (i = 0; i < tmp; i++)
writel(src_mem[i], engine + VIA_MMIO_BLTBASE);
return 0;
}
static int hw_bitblt_2(void __iomem *engine, u8 op, u32 width, u32 height,
u8 dst_bpp, u32 dst_addr, u32 dst_pitch, u32 dst_x, u32 dst_y,
u32 *src_mem, u32 src_addr, u32 src_pitch, u32 src_x, u32 src_y,
u32 fg_color, u32 bg_color, u8 fill_rop)
{
u32 ge_cmd = 0, tmp, i;
if (!op || op > 3) {
printk(KERN_WARNING "hw_bitblt_2: Invalid operation: %d\n", op);
return -EINVAL;
}
if (op != VIA_BITBLT_FILL && !src_mem && src_addr == dst_addr) {
if (src_x < dst_x) {
ge_cmd |= 0x00008000;
src_x += width - 1;
dst_x += width - 1;
}
if (src_y < dst_y) {
ge_cmd |= 0x00004000;
src_y += height - 1;
dst_y += height - 1;
}
}
if (op == VIA_BITBLT_FILL) {
switch (fill_rop) {
case 0x00: /* blackness */
case 0x5A: /* pattern inversion */
case 0xF0: /* pattern copy */
case 0xFF: /* whiteness */
break;
default:
printk(KERN_WARNING "hw_bitblt_2: Invalid fill rop: "
"%u\n", fill_rop);
return -EINVAL;
}
}
switch (dst_bpp) {
case 8:
tmp = 0x00000000;
break;
case 16:
tmp = 0x00000100;
break;
case 32:
tmp = 0x00000300;
break;
default:
printk(KERN_WARNING "hw_bitblt_2: Unsupported bpp %d\n",
dst_bpp);
return -EINVAL;
}
writel(tmp, engine + 0x04);
if (op == VIA_BITBLT_FILL)
tmp = 0;
else
tmp = src_pitch;
if (tmp & 0xFFFFC007 || dst_pitch & 0xFFFFC007) {
printk(KERN_WARNING "hw_bitblt_2: Unsupported pitch %X %X\n",
tmp, dst_pitch);
return -EINVAL;
}
tmp = (tmp >> 3) | (dst_pitch << (16 - 3));
writel(tmp, engine + 0x08);
if ((width - 1) & 0xFFFFF000 || (height - 1) & 0xFFFFF000) {
printk(KERN_WARNING "hw_bitblt_2: Unsupported width/height "
"%d %d\n", width, height);
return -EINVAL;
}
tmp = (width - 1) | ((height - 1) << 16);
writel(tmp, engine + 0x0C);
if (dst_x & 0xFFFFF000 || dst_y & 0xFFFFF000) {
printk(KERN_WARNING "hw_bitblt_2: Unsupported destination x/y "
"%d %d\n", dst_x, dst_y);
return -EINVAL;
}
tmp = dst_x | (dst_y << 16);
writel(tmp, engine + 0x10);
if (dst_addr & 0xE0000007) {
printk(KERN_WARNING "hw_bitblt_2: Unsupported destination "
"address %X\n", dst_addr);
return -EINVAL;
}
tmp = dst_addr >> 3;
writel(tmp, engine + 0x14);
if (op != VIA_BITBLT_FILL) {
if (src_x & (op == VIA_BITBLT_MONO ? 0xFFFF8000 : 0xFFFFF000)
|| src_y & 0xFFFFF000) {
printk(KERN_WARNING "hw_bitblt_2: Unsupported source "
"x/y %d %d\n", src_x, src_y);
return -EINVAL;
}
tmp = src_x | (src_y << 16);
writel(tmp, engine + 0x18);
tmp = src_mem ? 0 : src_addr;
if (dst_addr & 0xE0000007) {
printk(KERN_WARNING "hw_bitblt_2: Unsupported source "
"address %X\n", tmp);
return -EINVAL;
}
tmp >>= 3;
writel(tmp, engine + 0x1C);
}
if (op != VIA_BITBLT_COLOR)
writel(fg_color, engine + 0x4C);
if (op == VIA_BITBLT_MONO)
writel(bg_color, engine + 0x50);
if (op == VIA_BITBLT_FILL)
ge_cmd |= fill_rop << 24 | 0x00002000 | 0x00000001;
else {
ge_cmd |= 0xCC000000; /* ROP=SRCCOPY */
if (src_mem)
ge_cmd |= 0x00000040;
if (op == VIA_BITBLT_MONO)
ge_cmd |= 0x00000002 | 0x00000100 | 0x00020000;
else
ge_cmd |= 0x00000001;
}
writel(ge_cmd, engine);
if (op == VIA_BITBLT_FILL || !src_mem)
return 0;
tmp = (width * height * (op == VIA_BITBLT_MONO ? 1 : (dst_bpp >> 3)) +
3) >> 2;
for (i = 0; i < tmp; i++)
writel(src_mem[i], engine + VIA_MMIO_BLTBASE);
return 0;
}
int viafb_init_engine(struct fb_info *info)
{
struct viafb_par *viapar = info->par;
void __iomem *engine;
u32 vq_start_addr, vq_end_addr, vq_start_low, vq_end_low, vq_high,
vq_len, chip_name = viapar->shared->chip_info.gfx_chip_name;
engine = ioremap_nocache(info->fix.mmio_start, info->fix.mmio_len);
viapar->shared->engine_mmio = engine;
if (!engine) {
printk(KERN_WARNING "viafb_init_accel: ioremap failed, "
"hardware acceleration disabled\n");
return -ENOMEM;
}
switch (chip_name) {
case UNICHROME_CLE266:
case UNICHROME_K400:
case UNICHROME_K800:
case UNICHROME_PM800:
case UNICHROME_CN700:
case UNICHROME_CX700:
case UNICHROME_CN750:
case UNICHROME_K8M890:
case UNICHROME_P4M890:
case UNICHROME_P4M900:
viapar->shared->hw_bitblt = hw_bitblt_1;
break;
case UNICHROME_VX800:
case UNICHROME_VX855:
viapar->shared->hw_bitblt = hw_bitblt_2;
break;
default:
viapar->shared->hw_bitblt = NULL;
}
viapar->fbmem_free -= CURSOR_SIZE;
viapar->shared->cursor_vram_addr = viapar->fbmem_free;
viapar->fbmem_used += CURSOR_SIZE;
viapar->fbmem_free -= VQ_SIZE;
viapar->shared->vq_vram_addr = viapar->fbmem_free;
viapar->fbmem_used += VQ_SIZE;
/* Init AGP and VQ regs */
switch (chip_name) {
case UNICHROME_K8M890:
case UNICHROME_P4M900:
writel(0x00100000, engine + VIA_REG_CR_TRANSET);
writel(0x680A0000, engine + VIA_REG_CR_TRANSPACE);
writel(0x02000000, engine + VIA_REG_CR_TRANSPACE);
break;
default:
writel(0x00100000, engine + VIA_REG_TRANSET);
writel(0x00000000, engine + VIA_REG_TRANSPACE);
writel(0x00333004, engine + VIA_REG_TRANSPACE);
writel(0x60000000, engine + VIA_REG_TRANSPACE);
writel(0x61000000, engine + VIA_REG_TRANSPACE);
writel(0x62000000, engine + VIA_REG_TRANSPACE);
writel(0x63000000, engine + VIA_REG_TRANSPACE);
writel(0x64000000, engine + VIA_REG_TRANSPACE);
writel(0x7D000000, engine + VIA_REG_TRANSPACE);
writel(0xFE020000, engine + VIA_REG_TRANSET);
writel(0x00000000, engine + VIA_REG_TRANSPACE);
break;
}
/* Set BPP and Pitch */
writel(dwGEMode, viaparinfo->io_virt + VIA_REG_GEMODE);
}
/* Enable VQ */
vq_start_addr = viapar->shared->vq_vram_addr;
vq_end_addr = viapar->shared->vq_vram_addr + VQ_SIZE - 1;
vq_start_low = 0x50000000 | (vq_start_addr & 0xFFFFFF);
vq_end_low = 0x51000000 | (vq_end_addr & 0xFFFFFF);
vq_high = 0x52000000 | ((vq_start_addr & 0xFF000000) >> 24) |
((vq_end_addr & 0xFF000000) >> 16);
vq_len = 0x53000000 | (VQ_SIZE >> 3);
switch (chip_name) {
case UNICHROME_K8M890:
case UNICHROME_P4M900:
vq_start_low |= 0x20000000;
vq_end_low |= 0x20000000;
vq_high |= 0x20000000;
vq_len |= 0x20000000;
writel(0x00100000, engine + VIA_REG_CR_TRANSET);
writel(vq_high, engine + VIA_REG_CR_TRANSPACE);
writel(vq_start_low, engine + VIA_REG_CR_TRANSPACE);
writel(vq_end_low, engine + VIA_REG_CR_TRANSPACE);
writel(vq_len, engine + VIA_REG_CR_TRANSPACE);
writel(0x74301001, engine + VIA_REG_CR_TRANSPACE);
writel(0x00000000, engine + VIA_REG_CR_TRANSPACE);
break;
default:
writel(0x00FE0000, engine + VIA_REG_TRANSET);
writel(0x080003FE, engine + VIA_REG_TRANSPACE);
writel(0x0A00027C, engine + VIA_REG_TRANSPACE);
writel(0x0B000260, engine + VIA_REG_TRANSPACE);
writel(0x0C000274, engine + VIA_REG_TRANSPACE);
writel(0x0D000264, engine + VIA_REG_TRANSPACE);
writel(0x0E000000, engine + VIA_REG_TRANSPACE);
writel(0x0F000020, engine + VIA_REG_TRANSPACE);
writel(0x1000027E, engine + VIA_REG_TRANSPACE);
writel(0x110002FE, engine + VIA_REG_TRANSPACE);
writel(0x200F0060, engine + VIA_REG_TRANSPACE);
writel(0x00000006, engine + VIA_REG_TRANSPACE);
writel(0x40008C0F, engine + VIA_REG_TRANSPACE);
writel(0x44000000, engine + VIA_REG_TRANSPACE);
writel(0x45080C04, engine + VIA_REG_TRANSPACE);
writel(0x46800408, engine + VIA_REG_TRANSPACE);
writel(vq_high, engine + VIA_REG_TRANSPACE);
writel(vq_start_low, engine + VIA_REG_TRANSPACE);
writel(vq_end_low, engine + VIA_REG_TRANSPACE);
writel(vq_len, engine + VIA_REG_TRANSPACE);
break;
}
void viafb_hw_cursor_init(void)
{
/* Set Cursor Image Base Address */
writel(viaparinfo->cursor_start,
viaparinfo->io_virt + VIA_REG_CURSOR_MODE);
writel(0x0, viaparinfo->io_virt + VIA_REG_CURSOR_POS);
writel(0x0, viaparinfo->io_virt + VIA_REG_CURSOR_ORG);
writel(0x0, viaparinfo->io_virt + VIA_REG_CURSOR_BG);
writel(0x0, viaparinfo->io_virt + VIA_REG_CURSOR_FG);
writel(viapar->shared->cursor_vram_addr, engine + VIA_REG_CURSOR_MODE);
writel(0x0, engine + VIA_REG_CURSOR_POS);
writel(0x0, engine + VIA_REG_CURSOR_ORG);
writel(0x0, engine + VIA_REG_CURSOR_BG);
writel(0x0, engine + VIA_REG_CURSOR_FG);
return 0;
}
void viafb_show_hw_cursor(struct fb_info *info, int Status)
{
u32 temp;
u32 iga_path = ((struct viafb_par *)(info->par))->iga_path;
struct viafb_par *viapar = info->par;
u32 temp, iga_path = viapar->iga_path;
temp = readl(viaparinfo->io_virt + VIA_REG_CURSOR_MODE);
temp = readl(viapar->shared->engine_mmio + VIA_REG_CURSOR_MODE);
switch (Status) {
case HW_Cursor_ON:
temp |= 0x1;
@@ -259,25 +460,27 @@ void viafb_show_hw_cursor(struct fb_info *info, int Status)
default:
temp &= 0x7FFFFFFF;
}
writel(temp, viaparinfo->io_virt + VIA_REG_CURSOR_MODE);
writel(temp, viapar->shared->engine_mmio + VIA_REG_CURSOR_MODE);
}
int viafb_wait_engine_idle(void)
void viafb_wait_engine_idle(struct fb_info *info)
{
struct viafb_par *viapar = info->par;
int loop = 0;
while (!(readl(viaparinfo->io_virt + VIA_REG_STATUS) &
while (!(readl(viapar->shared->engine_mmio + VIA_REG_STATUS) &
VIA_VR_QUEUE_BUSY) && (loop < MAXLOOP)) {
loop++;
cpu_relax();
}
while ((readl(viaparinfo->io_virt + VIA_REG_STATUS) &
while ((readl(viapar->shared->engine_mmio + VIA_REG_STATUS) &
(VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY | VIA_3D_ENG_BUSY)) &&
(loop < MAXLOOP)) {
loop++;
cpu_relax();
}
return loop >= MAXLOOP;
if (loop >= MAXLOOP)
printk(KERN_ERR "viafb_wait_engine_idle: not syncing\n");
}

13
drivers/video/via/accel.h
View File

@@ -159,11 +159,12 @@
#define MAXLOOP 0xFFFFFF
void viafb_init_accel(void);
void viafb_init_2d_engine(void);
void set_2d_color_depth(int);
void viafb_hw_cursor_init(void);
void viafb_show_hw_cursor(struct fb_info *info, int Status); int
viafb_wait_engine_idle(void); void viafb_set_2d_color_depth(int bpp);
#define VIA_BITBLT_COLOR 1
#define VIA_BITBLT_MONO 2
#define VIA_BITBLT_FILL 3
int viafb_init_engine(struct fb_info *info);
void viafb_show_hw_cursor(struct fb_info *info, int Status);
void viafb_wait_engine_idle(struct fb_info *info);
#endif /* __ACCEL_H__ */

4
drivers/video/via/chip.h
View File

@@ -68,6 +68,9 @@
#define UNICHROME_VX800 11
#define UNICHROME_VX800_DID 0x1122
#define UNICHROME_VX855 12
#define UNICHROME_VX855_DID 0x5122
/**************************************************/
/* Definition TMDS Trasmitter Information */
/**************************************************/
@@ -122,7 +125,6 @@ struct lvds_chip_information {
struct chip_information {
int gfx_chip_name;
int gfx_chip_revision;
int chip_on_slot;
struct tmds_chip_information tmds_chip_info;
struct lvds_chip_information lvds_chip_info;
struct lvds_chip_information lvds_chip_info2;

6
drivers/video/via/dvi.c
View File

@@ -160,7 +160,7 @@ int viafb_tmds_trasmitter_identify(void)
static void tmds_register_write(int index, u8 data)
{
viaparinfo->i2c_stuff.i2c_port =
viaparinfo->shared->i2c_stuff.i2c_port =
viaparinfo->chip_info->tmds_chip_info.i2c_port;
viafb_i2c_writebyte(viaparinfo->chip_info->tmds_chip_info.
@@ -172,7 +172,7 @@ static int tmds_register_read(int index)
{
u8 data;
viaparinfo->i2c_stuff.i2c_port =
viaparinfo->shared->i2c_stuff.i2c_port =
viaparinfo->chip_info->tmds_chip_info.i2c_port;
viafb_i2c_readbyte((u8) viaparinfo->chip_info->
tmds_chip_info.tmds_chip_slave_addr,
@@ -182,7 +182,7 @@ static int tmds_register_read(int index)
static int tmds_register_read_bytes(int index, u8 *buff, int buff_len)
{
viaparinfo->i2c_stuff.i2c_port =
viaparinfo->shared->i2c_stuff.i2c_port =
viaparinfo->chip_info->tmds_chip_info.i2c_port;
viafb_i2c_readbytes((u8) viaparinfo->chip_info->tmds_chip_info.
tmds_chip_slave_addr, (u8) index, buff, buff_len);

3
drivers/video/via/global.c
View File

@@ -32,7 +32,6 @@ int viafb_lcd_dsp_method = LCD_EXPANDSION;
int viafb_lcd_mode = LCD_OPENLDI;
int viafb_bpp = 32;
int viafb_bpp1 = 32;
int viafb_accel = 1;
int viafb_CRT_ON = 1;
int viafb_DVI_ON;
int viafb_LCD_ON ;
@@ -46,13 +45,11 @@ int viafb_hotplug_refresh = 60;
unsigned int viafb_second_offset;
int viafb_second_size;
int viafb_primary_dev = None_Device;
void __iomem *viafb_FB_MM;
unsigned int viafb_second_xres = 640;
unsigned int viafb_second_yres = 480;
unsigned int viafb_second_virtual_xres;
unsigned int viafb_second_virtual_yres;
int viafb_lcd_panel_id = LCD_PANEL_ID_MAXIMUM + 1;
struct fb_cursor viacursor;
struct fb_info *viafbinfo;
struct fb_info *viafbinfo1;
struct viafb_par *viaparinfo;

2
drivers/video/via/global.h
View File

@@ -77,8 +77,6 @@ extern int viafb_hotplug_Yres;
extern int viafb_hotplug_bpp;
extern int viafb_hotplug_refresh;
extern int viafb_primary_dev;
extern void __iomem *viafb_FB_MM;
extern struct fb_cursor viacursor;
extern unsigned int viafb_second_xres;
extern unsigned int viafb_second_yres;

474
drivers/video/via/hw.c
View File

@@ -21,125 +21,143 @@
#include "global.h"
static const struct pci_device_id_info pciidlist[] = {
{PCI_VIA_VENDOR_ID, UNICHROME_CLE266_DID, UNICHROME_CLE266},
{PCI_VIA_VENDOR_ID, UNICHROME_PM800_DID, UNICHROME_PM800},
{PCI_VIA_VENDOR_ID, UNICHROME_K400_DID, UNICHROME_K400},
{PCI_VIA_VENDOR_ID, UNICHROME_K800_DID, UNICHROME_K800},
{PCI_VIA_VENDOR_ID, UNICHROME_CN700_DID, UNICHROME_CN700},
{PCI_VIA_VENDOR_ID, UNICHROME_P4M890_DID, UNICHROME_P4M890},
{PCI_VIA_VENDOR_ID, UNICHROME_K8M890_DID, UNICHROME_K8M890},
{PCI_VIA_VENDOR_ID, UNICHROME_CX700_DID, UNICHROME_CX700},
{PCI_VIA_VENDOR_ID, UNICHROME_P4M900_DID, UNICHROME_P4M900},
{PCI_VIA_VENDOR_ID, UNICHROME_CN750_DID, UNICHROME_CN750},
{PCI_VIA_VENDOR_ID, UNICHROME_VX800_DID, UNICHROME_VX800},
{0, 0, 0}
};
struct offset offset_reg = {
/* IGA1 Offset Register */
{IGA1_OFFSET_REG_NUM, {{CR13, 0, 7}, {CR35, 5, 7} } },
/* IGA2 Offset Register */
{IGA2_OFFSET_REG_NUM, {{CR66, 0, 7}, {CR67, 0, 1} } }
};
static struct pll_map pll_value[] = {
{CLK_25_175M, CLE266_PLL_25_175M, K800_PLL_25_175M, CX700_25_175M},
{CLK_29_581M, CLE266_PLL_29_581M, K800_PLL_29_581M, CX700_29_581M},
{CLK_26_880M, CLE266_PLL_26_880M, K800_PLL_26_880M, CX700_26_880M},
{CLK_31_490M, CLE266_PLL_31_490M, K800_PLL_31_490M, CX700_31_490M},
{CLK_31_500M, CLE266_PLL_31_500M, K800_PLL_31_500M, CX700_31_500M},
{CLK_31_728M, CLE266_PLL_31_728M, K800_PLL_31_728M, CX700_31_728M},
{CLK_32_668M, CLE266_PLL_32_668M, K800_PLL_32_668M, CX700_32_668M},
{CLK_36_000M, CLE266_PLL_36_000M, K800_PLL_36_000M, CX700_36_000M},
{CLK_40_000M, CLE266_PLL_40_000M, K800_PLL_40_000M, CX700_40_000M},
{CLK_41_291M, CLE266_PLL_41_291M, K800_PLL_41_291M, CX700_41_291M},
{CLK_43_163M, CLE266_PLL_43_163M, K800_PLL_43_163M, CX700_43_163M},
{CLK_45_250M, CLE266_PLL_45_250M, K800_PLL_45_250M, CX700_45_250M},
{CLK_46_000M, CLE266_PLL_46_000M, K800_PLL_46_000M, CX700_46_000M},
{CLK_46_996M, CLE266_PLL_46_996M, K800_PLL_46_996M, CX700_46_996M},
{CLK_48_000M, CLE266_PLL_48_000M, K800_PLL_48_000M, CX700_48_000M},
{CLK_48_875M, CLE266_PLL_48_875M, K800_PLL_48_875M, CX700_48_875M},
{CLK_49_500M, CLE266_PLL_49_500M, K800_PLL_49_500M, CX700_49_500M},
{CLK_52_406M, CLE266_PLL_52_406M, K800_PLL_52_406M, CX700_52_406M},
{CLK_52_977M, CLE266_PLL_52_977M, K800_PLL_52_977M, CX700_52_977M},
{CLK_56_250M, CLE266_PLL_56_250M, K800_PLL_56_250M, CX700_56_250M},
{CLK_60_466M, CLE266_PLL_60_466M, K800_PLL_60_466M, CX700_60_466M},
{CLK_61_500M, CLE266_PLL_61_500M, K800_PLL_61_500M, CX700_61_500M},
{CLK_65_000M, CLE266_PLL_65_000M, K800_PLL_65_000M, CX700_65_000M},
{CLK_65_178M, CLE266_PLL_65_178M, K800_PLL_65_178M, CX700_65_178M},
{CLK_66_750M, CLE266_PLL_66_750M, K800_PLL_66_750M, CX700_66_750M},
{CLK_68_179M, CLE266_PLL_68_179M, K800_PLL_68_179M, CX700_68_179M},
{CLK_69_924M, CLE266_PLL_69_924M, K800_PLL_69_924M, CX700_69_924M},
{CLK_70_159M, CLE266_PLL_70_159M, K800_PLL_70_159M, CX700_70_159M},
{CLK_72_000M, CLE266_PLL_72_000M, K800_PLL_72_000M, CX700_72_000M},
{CLK_78_750M, CLE266_PLL_78_750M, K800_PLL_78_750M, CX700_78_750M},
{CLK_80_136M, CLE266_PLL_80_136M, K800_PLL_80_136M, CX700_80_136M},
{CLK_83_375M, CLE266_PLL_83_375M, K800_PLL_83_375M, CX700_83_375M},
{CLK_83_950M, CLE266_PLL_83_950M, K800_PLL_83_950M, CX700_83_950M},
{CLK_84_750M, CLE266_PLL_84_750M, K800_PLL_84_750M, CX700_84_750M},
{CLK_85_860M, CLE266_PLL_85_860M, K800_PLL_85_860M, CX700_85_860M},
{CLK_88_750M, CLE266_PLL_88_750M, K800_PLL_88_750M, CX700_88_750M},
{CLK_94_500M, CLE266_PLL_94_500M, K800_PLL_94_500M, CX700_94_500M},
{CLK_97_750M, CLE266_PLL_97_750M, K800_PLL_97_750M, CX700_97_750M},
{CLK_25_175M, CLE266_PLL_25_175M, K800_PLL_25_175M,
CX700_25_175M, VX855_25_175M},
{CLK_29_581M, CLE266_PLL_29_581M, K800_PLL_29_581M,
CX700_29_581M, VX855_29_581M},
{CLK_26_880M, CLE266_PLL_26_880M, K800_PLL_26_880M,
CX700_26_880M, VX855_26_880M},
{CLK_31_490M, CLE266_PLL_31_490M, K800_PLL_31_490M,
CX700_31_490M, VX855_31_490M},
{CLK_31_500M, CLE266_PLL_31_500M, K800_PLL_31_500M,
CX700_31_500M, VX855_31_500M},
{CLK_31_728M, CLE266_PLL_31_728M, K800_PLL_31_728M,
CX700_31_728M, VX855_31_728M},
{CLK_32_668M, CLE266_PLL_32_668M, K800_PLL_32_668M,
CX700_32_668M, VX855_32_668M},
{CLK_36_000M, CLE266_PLL_36_000M, K800_PLL_36_000M,
CX700_36_000M, VX855_36_000M},
{CLK_40_000M, CLE266_PLL_40_000M, K800_PLL_40_000M,
CX700_40_000M, VX855_40_000M},
{CLK_41_291M, CLE266_PLL_41_291M, K800_PLL_41_291M,
CX700_41_291M, VX855_41_291M},
{CLK_43_163M, CLE266_PLL_43_163M, K800_PLL_43_163M,
CX700_43_163M, VX855_43_163M},
{CLK_45_250M, CLE266_PLL_45_250M, K800_PLL_45_250M,
CX700_45_250M, VX855_45_250M},
{CLK_46_000M, CLE266_PLL_46_000M, K800_PLL_46_000M,
CX700_46_000M, VX855_46_000M},
{CLK_46_996M, CLE266_PLL_46_996M, K800_PLL_46_996M,
CX700_46_996M, VX855_46_996M},
{CLK_48_000M, CLE266_PLL_48_000M, K800_PLL_48_000M,
CX700_48_000M, VX855_48_000M},
{CLK_48_875M, CLE266_PLL_48_875M, K800_PLL_48_875M,
CX700_48_875M, VX855_48_875M},
{CLK_49_500M, CLE266_PLL_49_500M, K800_PLL_49_500M,
CX700_49_500M, VX855_49_500M},
{CLK_52_406M, CLE266_PLL_52_406M, K800_PLL_52_406M,
CX700_52_406M, VX855_52_406M},
{CLK_52_977M, CLE266_PLL_52_977M, K800_PLL_52_977M,
CX700_52_977M, VX855_52_977M},
{CLK_56_250M, CLE266_PLL_56_250M, K800_PLL_56_250M,
CX700_56_250M, VX855_56_250M},
{CLK_60_466M, CLE266_PLL_60_466M, K800_PLL_60_466M,
CX700_60_466M, VX855_60_466M},
{CLK_61_500M, CLE266_PLL_61_500M, K800_PLL_61_500M,
CX700_61_500M, VX855_61_500M},
{CLK_65_000M, CLE266_PLL_65_000M, K800_PLL_65_000M,
CX700_65_000M, VX855_65_000M},
{CLK_65_178M, CLE266_PLL_65_178M, K800_PLL_65_178M,
CX700_65_178M, VX855_65_178M},
{CLK_66_750M, CLE266_PLL_66_750M, K800_PLL_66_750M,
CX700_66_750M, VX855_66_750M},
{CLK_68_179M, CLE266_PLL_68_179M, K800_PLL_68_179M,
CX700_68_179M, VX855_68_179M},
{CLK_69_924M, CLE266_PLL_69_924M, K800_PLL_69_924M,
CX700_69_924M, VX855_69_924M},
{CLK_70_159M, CLE266_PLL_70_159M, K800_PLL_70_159M,
CX700_70_159M, VX855_70_159M},
{CLK_72_000M, CLE266_PLL_72_000M, K800_PLL_72_000M,
CX700_72_000M, VX855_72_000M},
{CLK_78_750M, CLE266_PLL_78_750M, K800_PLL_78_750M,
CX700_78_750M, VX855_78_750M},
{CLK_80_136M, CLE266_PLL_80_136M, K800_PLL_80_136M,
CX700_80_136M, VX855_80_136M},
{CLK_83_375M, CLE266_PLL_83_375M, K800_PLL_83_375M,
CX700_83_375M, VX855_83_375M},
{CLK_83_950M, CLE266_PLL_83_950M, K800_PLL_83_950M,
CX700_83_950M, VX855_83_950M},
{CLK_84_750M, CLE266_PLL_84_750M, K800_PLL_84_750M,
CX700_84_750M, VX855_84_750M},
{CLK_85_860M, CLE266_PLL_85_860M, K800_PLL_85_860M,
CX700_85_860M, VX855_85_860M},
{CLK_88_750M, CLE266_PLL_88_750M, K800_PLL_88_750M,
CX700_88_750M, VX855_88_750M},
{CLK_94_500M, CLE266_PLL_94_500M, K800_PLL_94_500M,
CX700_94_500M, VX855_94_500M},
{CLK_97_750M, CLE266_PLL_97_750M, K800_PLL_97_750M,
CX700_97_750M, VX855_97_750M},
{CLK_101_000M, CLE266_PLL_101_000M, K800_PLL_101_000M,
CX700_101_000M},
CX700_101_000M, VX855_101_000M},
{CLK_106_500M, CLE266_PLL_106_500M, K800_PLL_106_500M,
CX700_106_500M},
CX700_106_500M, VX855_106_500M},
{CLK_108_000M, CLE266_PLL_108_000M, K800_PLL_108_000M,
CX700_108_000M},
CX700_108_000M, VX855_108_000M},
{CLK_113_309M, CLE266_PLL_113_309M, K800_PLL_113_309M,
CX700_113_309M},
CX700_113_309M, VX855_113_309M},
{CLK_118_840M, CLE266_PLL_118_840M, K800_PLL_118_840M,
CX700_118_840M},
CX700_118_840M, VX855_118_840M},
{CLK_119_000M, CLE266_PLL_119_000M, K800_PLL_119_000M,
CX700_119_000M},
CX700_119_000M, VX855_119_000M},
{CLK_121_750M, CLE266_PLL_121_750M, K800_PLL_121_750M,
CX700_121_750M},
CX700_121_750M, 0},
{CLK_125_104M, CLE266_PLL_125_104M, K800_PLL_125_104M,
CX700_125_104M},
CX700_125_104M, 0},
{CLK_133_308M, CLE266_PLL_133_308M, K800_PLL_133_308M,
CX700_133_308M},
CX700_133_308M, 0},
{CLK_135_000M, CLE266_PLL_135_000M, K800_PLL_135_000M,
CX700_135_000M},
CX700_135_000M, VX855_135_000M},
{CLK_136_700M, CLE266_PLL_136_700M, K800_PLL_136_700M,
CX700_136_700M},
CX700_136_700M, VX855_136_700M},
{CLK_138_400M, CLE266_PLL_138_400M, K800_PLL_138_400M,
CX700_138_400M},
CX700_138_400M, VX855_138_400M},
{CLK_146_760M, CLE266_PLL_146_760M, K800_PLL_146_760M,
CX700_146_760M},
CX700_146_760M, VX855_146_760M},
{CLK_153_920M, CLE266_PLL_153_920M, K800_PLL_153_920M,
CX700_153_920M},
CX700_153_920M, VX855_153_920M},
{CLK_156_000M, CLE266_PLL_156_000M, K800_PLL_156_000M,
CX700_156_000M},
CX700_156_000M, VX855_156_000M},
{CLK_157_500M, CLE266_PLL_157_500M, K800_PLL_157_500M,
CX700_157_500M},
CX700_157_500M, VX855_157_500M},
{CLK_162_000M, CLE266_PLL_162_000M, K800_PLL_162_000M,
CX700_162_000M},
CX700_162_000M, VX855_162_000M},
{CLK_187_000M, CLE266_PLL_187_000M, K800_PLL_187_000M,
CX700_187_000M},
CX700_187_000M, VX855_187_000M},
{CLK_193_295M, CLE266_PLL_193_295M, K800_PLL_193_295M,
CX700_193_295M},
CX700_193_295M, VX855_193_295M},
{CLK_202_500M, CLE266_PLL_202_500M, K800_PLL_202_500M,
CX700_202_500M},
CX700_202_500M, VX855_202_500M},
{CLK_204_000M, CLE266_PLL_204_000M, K800_PLL_204_000M,
CX700_204_000M},
CX700_204_000M, VX855_204_000M},
{CLK_218_500M, CLE266_PLL_218_500M, K800_PLL_218_500M,
CX700_218_500M},
CX700_218_500M, VX855_218_500M},
{CLK_234_000M, CLE266_PLL_234_000M, K800_PLL_234_000M,
CX700_234_000M},
CX700_234_000M, VX855_234_000M},
{CLK_267_250M, CLE266_PLL_267_250M, K800_PLL_267_250M,
CX700_267_250M},
CX700_267_250M, VX855_267_250M},
{CLK_297_500M, CLE266_PLL_297_500M, K800_PLL_297_500M,
CX700_297_500M},
{CLK_74_481M, CLE266_PLL_74_481M, K800_PLL_74_481M, CX700_74_481M},
CX700_297_500M, VX855_297_500M},
{CLK_74_481M, CLE266_PLL_74_481M, K800_PLL_74_481M,
CX700_74_481M, VX855_74_481M},
{CLK_172_798M, CLE266_PLL_172_798M, K800_PLL_172_798M,
CX700_172_798M},
CX700_172_798M, VX855_172_798M},
{CLK_122_614M, CLE266_PLL_122_614M, K800_PLL_122_614M,
CX700_122_614M},
{CLK_74_270M, CLE266_PLL_74_270M, K800_PLL_74_270M, CX700_74_270M},
CX700_122_614M, VX855_122_614M},
{CLK_74_270M, CLE266_PLL_74_270M, K800_PLL_74_270M,
CX700_74_270M, 0},
{CLK_148_500M, CLE266_PLL_148_500M, K800_PLL_148_500M,
CX700_148_500M}
CX700_148_500M, VX855_148_500M}
};
static struct fifo_depth_select display_fifo_depth_reg = {
@@ -508,7 +526,8 @@ static void set_dvi_output_path(int set_iga, int output_interface);
static void set_lcd_output_path(int set_iga, int output_interface);
static int search_mode_setting(int ModeInfoIndex);
static void load_fix_bit_crtc_reg(void);
static void init_gfx_chip_info(void);
static void init_gfx_chip_info(struct pci_dev *pdev,
const struct pci_device_id *pdi);
static void init_tmds_chip_info(void);
static void init_lvds_chip_info(void);
static void device_screen_off(void);
@@ -518,7 +537,6 @@ static void device_off(void);
static void device_on(void);
static void enable_second_display_channel(void);
static void disable_second_display_channel(void);
static int get_fb_size_from_pci(void);
void viafb_write_reg(u8 index, u16 io_port, u8 data)
{
@@ -629,70 +647,43 @@ void viafb_set_iga_path(void)
}
}
void viafb_set_start_addr(void)
void viafb_set_primary_address(u32 addr)
{
unsigned long offset = 0, tmp = 0, size = 0;
unsigned long length;
DEBUG_MSG(KERN_DEBUG "viafb_set_primary_address(0x%08X)\n", addr);
viafb_write_reg(CR0D, VIACR, addr & 0xFF);
viafb_write_reg(CR0C, VIACR, (addr >> 8) & 0xFF);
viafb_write_reg(CR34, VIACR, (addr >> 16) & 0xFF);
viafb_write_reg_mask(CR48, VIACR, (addr >> 24) & 0x1F, 0x1F);
}
DEBUG_MSG(KERN_INFO "viafb_set_start_addr!\n");
viafb_unlock_crt();
/* update starting address of IGA1 */
viafb_write_reg(CR0C, VIACR, 0x00); /*initial starting address */
viafb_write_reg(CR0D, VIACR, 0x00);
viafb_write_reg(CR34, VIACR, 0x00);
viafb_write_reg_mask(CR48, VIACR, 0x00, 0x1F);
void viafb_set_secondary_address(u32 addr)
{
DEBUG_MSG(KERN_DEBUG "viafb_set_secondary_address(0x%08X)\n", addr);
/* secondary display supports only quadword aligned memory */
viafb_write_reg_mask(CR62, VIACR, (addr >> 2) & 0xFE, 0xFE);
viafb_write_reg(CR63, VIACR, (addr >> 10) & 0xFF);
viafb_write_reg(CR64, VIACR, (addr >> 18) & 0xFF);
viafb_write_reg_mask(CRA3, VIACR, (addr >> 26) & 0x07, 0x07);
}
if (viafb_dual_fb) {
viaparinfo->iga_path = IGA1;
viaparinfo1->iga_path = IGA2;
}
void viafb_set_primary_pitch(u32 pitch)
{
DEBUG_MSG(KERN_DEBUG "viafb_set_primary_pitch(0x%08X)\n", pitch);
/* spec does not say that first adapter skips 3 bits but old
* code did it and seems to be reasonable in analogy to 2nd adapter
*/
pitch = pitch >> 3;
viafb_write_reg(0x13, VIACR, pitch & 0xFF);
viafb_write_reg_mask(0x35, VIACR, (pitch >> (8 - 5)) & 0xE0, 0xE0);
}
if (viafb_SAMM_ON == 1) {
if (!viafb_dual_fb) {
if (viafb_second_size)
size = viafb_second_size * 1024 * 1024;
else
size = 8 * 1024 * 1024;
} else {
size = viaparinfo1->memsize;
}
offset = viafb_second_offset;
DEBUG_MSG(KERN_INFO
"viafb_second_size=%lx, second start_adddress=%lx\n",
size, offset);
}
if (viafb_SAMM_ON == 1) {
offset = offset >> 3;
tmp = viafb_read_reg(VIACR, 0x62) & 0x01;
tmp |= (offset & 0x7F) << 1;
viafb_write_reg(CR62, VIACR, tmp);
viafb_write_reg(CR63, VIACR, ((offset & 0x7F80) >> 7));
viafb_write_reg(CR64, VIACR, ((offset & 0x7F8000) >> 15));
viafb_write_reg(CRA3, VIACR, ((offset & 0x3800000) >> 23));
} else {
/* update starting address */
viafb_write_reg(CR62, VIACR, 0x00);
viafb_write_reg(CR63, VIACR, 0x00);
viafb_write_reg(CR64, VIACR, 0x00);
viafb_write_reg(CRA3, VIACR, 0x00);
}
if (viafb_SAMM_ON == 1) {
if (viafb_accel) {
if (!viafb_dual_fb)
length = size - viaparinfo->fbmem_used;
else
length = size - viaparinfo1->fbmem_used;
} else
length = size;
offset = (unsigned long)(void *)viafb_FB_MM +
viafb_second_offset;
memset((void *)offset, 0, length);
}
viafb_lock_crt();
void viafb_set_secondary_pitch(u32 pitch)
{
DEBUG_MSG(KERN_DEBUG "viafb_set_secondary_pitch(0x%08X)\n", pitch);
pitch = pitch >> 3;
viafb_write_reg(0x66, VIACR, pitch & 0xFF);
viafb_write_reg_mask(0x67, VIACR, (pitch >> 8) & 0x03, 0x03);
viafb_write_reg_mask(0x71, VIACR, (pitch >> (10 - 7)) & 0x80, 0x80);
}
void viafb_set_output_path(int device, int set_iga, int output_interface)
@@ -1123,30 +1114,6 @@ void viafb_write_regx(struct io_reg RegTable[], int ItemNum)
}
}
void viafb_load_offset_reg(int h_addr, int bpp_byte, int set_iga)
{
int reg_value;
int viafb_load_reg_num;
struct io_register *reg;
switch (set_iga) {
case IGA1_IGA2:
case IGA1:
reg_value = IGA1_OFFSET_FORMULA(h_addr, bpp_byte);
viafb_load_reg_num = offset_reg.iga1_offset_reg.reg_num;
reg = offset_reg.iga1_offset_reg.reg;
viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
if (set_iga == IGA1)
break;
case IGA2:
reg_value = IGA2_OFFSET_FORMULA(h_addr, bpp_byte);
viafb_load_reg_num = offset_reg.iga2_offset_reg.reg_num;
reg = offset_reg.iga2_offset_reg.reg;
viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
break;
}
}
void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga)
{
int reg_value;
@@ -1277,6 +1244,15 @@ void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active)
VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
}
if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) {
iga1_fifo_max_depth = VX855_IGA1_FIFO_MAX_DEPTH;
iga1_fifo_threshold = VX855_IGA1_FIFO_THRESHOLD;
iga1_fifo_high_threshold =
VX855_IGA1_FIFO_HIGH_THRESHOLD;
iga1_display_queue_expire_num =
VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
}
/* Set Display FIFO Depath Select */
reg_value = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga1_fifo_max_depth);
viafb_load_reg_num =
@@ -1408,6 +1384,15 @@ void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active)
VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
}
if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) {
iga2_fifo_max_depth = VX855_IGA2_FIFO_MAX_DEPTH;
iga2_fifo_threshold = VX855_IGA2_FIFO_THRESHOLD;
iga2_fifo_high_threshold =
VX855_IGA2_FIFO_HIGH_THRESHOLD;
iga2_display_queue_expire_num =
VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
}
if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
/* Set Display FIFO Depath Select */
reg_value =
@@ -1496,6 +1481,8 @@ u32 viafb_get_clk_value(int clk)
case UNICHROME_P4M900:
case UNICHROME_VX800:
return pll_value[i].cx700_pll;
case UNICHROME_VX855:
return pll_value[i].vx855_pll;
}
}
}
@@ -1529,6 +1516,7 @@ void viafb_set_vclock(u32 CLK, int set_iga)
case UNICHROME_P4M890:
case UNICHROME_P4M900:
case UNICHROME_VX800:
case UNICHROME_VX855:
viafb_write_reg(SR44, VIASR, CLK / 0x10000);
DEBUG_MSG(KERN_INFO "\nSR44=%x", CLK / 0x10000);
viafb_write_reg(SR45, VIASR, (CLK & 0xFFFF) / 0x100);
@@ -1557,6 +1545,7 @@ void viafb_set_vclock(u32 CLK, int set_iga)
case UNICHROME_P4M890:
case UNICHROME_P4M900:
case UNICHROME_VX800:
case UNICHROME_VX855:
viafb_write_reg(SR4A, VIASR, CLK / 0x10000);
viafb_write_reg(SR4B, VIASR, (CLK & 0xFFFF) / 0x100);
viafb_write_reg(SR4C, VIASR, CLK % 0x100);
@@ -1916,7 +1905,6 @@ void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
load_fix_bit_crtc_reg();
viafb_lock_crt();
viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
viafb_load_offset_reg(h_addr, bpp_byte, set_iga);
viafb_load_fetch_count_reg(h_addr, bpp_byte, set_iga);
/* load FIFO */
@@ -1933,9 +1921,10 @@ void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
}
void viafb_init_chip_info(void)
void viafb_init_chip_info(struct pci_dev *pdev,
const struct pci_device_id *pdi)
{
init_gfx_chip_info();
init_gfx_chip_info(pdev, pdi);
init_tmds_chip_info();
init_lvds_chip_info();
@@ -2008,24 +1997,12 @@ void viafb_update_device_setting(int hres, int vres,
}
}
static void init_gfx_chip_info(void)
static void init_gfx_chip_info(struct pci_dev *pdev,
const struct pci_device_id *pdi)
{
struct pci_dev *pdev = NULL;
u32 i;
u8 tmp;
/* Indentify GFX Chip Name */
for (i = 0; pciidlist[i].vendor != 0; i++) {
pdev = pci_get_device(pciidlist[i].vendor,
pciidlist[i].device, 0);
if (pdev)
break;
}
if (!pciidlist[i].vendor)
return ;
viaparinfo->chip_info->gfx_chip_name = pciidlist[i].chip_index;
viaparinfo->chip_info->gfx_chip_name = pdi->driver_data;
/* Check revision of CLE266 Chip */
if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
@@ -2056,8 +2033,6 @@ static void init_gfx_chip_info(void)
CX700_REVISION_700;
}
}
pci_dev_put(pdev);
}
static void init_tmds_chip_info(void)
@@ -2271,11 +2246,12 @@ int viafb_setmode(int vmode_index, int hor_res, int ver_res, int video_bpp,
break;
case UNICHROME_CX700:
viafb_write_regx(CX700_ModeXregs, NUM_TOTAL_CX700_ModeXregs);
case UNICHROME_VX800:
viafb_write_regx(VX800_ModeXregs, NUM_TOTAL_VX800_ModeXregs);
viafb_write_regx(CX700_ModeXregs, NUM_TOTAL_CX700_ModeXregs);
break;
case UNICHROME_VX855:
viafb_write_regx(VX855_ModeXregs, NUM_TOTAL_VX855_ModeXregs);
break;
}
@@ -2291,7 +2267,8 @@ int viafb_setmode(int vmode_index, int hor_res, int ver_res, int video_bpp,
outb(VPIT.SR[i - 1], VIASR + 1);
}
viafb_set_start_addr();
viafb_set_primary_address(0);
viafb_set_secondary_address(viafb_SAMM_ON ? viafb_second_offset : 0);
viafb_set_iga_path();
/* Write CRTC */
@@ -2371,6 +2348,9 @@ int viafb_setmode(int vmode_index, int hor_res, int ver_res, int video_bpp,
}
}
viafb_set_primary_pitch(viafbinfo->fix.line_length);
viafb_set_secondary_pitch(viafb_dual_fb ? viafbinfo1->fix.line_length
: viafbinfo->fix.line_length);
/* Update Refresh Rate Setting */
/* Clear On Screen */
@@ -2545,38 +2525,6 @@ void viafb_crt_enable(void)
viafb_write_reg_mask(CR36, VIACR, 0x0, BIT5 + BIT4);
}
void viafb_get_mmio_info(unsigned long *mmio_base,
unsigned long *mmio_len)
{
struct pci_dev *pdev = NULL;
u32 vendor, device;
u32 i;
for (i = 0; pciidlist[i].vendor != 0; i++)
if (viaparinfo->chip_info->gfx_chip_name ==
pciidlist[i].chip_index)
break;
if (!pciidlist[i].vendor)
return ;
vendor = pciidlist[i].vendor;
device = pciidlist[i].device;
pdev = pci_get_device(vendor, device, NULL);
if (!pdev) {
*mmio_base = 0;
*mmio_len = 0;
return ;
}
*mmio_base = pci_resource_start(pdev, 1);
*mmio_len = pci_resource_len(pdev, 1);
pci_dev_put(pdev);
}
static void enable_second_display_channel(void)
{
/* to enable second display channel. */
@@ -2593,44 +2541,7 @@ static void disable_second_display_channel(void)
viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
}
void viafb_get_fb_info(unsigned int *fb_base, unsigned int *fb_len)
{
struct pci_dev *pdev = NULL;
u32 vendor, device;
u32 i;
for (i = 0; pciidlist[i].vendor != 0; i++)
if (viaparinfo->chip_info->gfx_chip_name ==
pciidlist[i].chip_index)
break;
if (!pciidlist[i].vendor)
return ;
vendor = pciidlist[i].vendor;
device = pciidlist[i].device;
pdev = pci_get_device(vendor, device, NULL);
if (!pdev) {
*fb_base = viafb_read_reg(VIASR, SR30) << 24;
*fb_len = viafb_get_memsize();
DEBUG_MSG(KERN_INFO "Get FB info from SR30!\n");
DEBUG_MSG(KERN_INFO "fb_base = %08x\n", *fb_base);
DEBUG_MSG(KERN_INFO "fb_len = %08x\n", *fb_len);
return ;
}
*fb_base = (unsigned int)pci_resource_start(pdev, 0);
*fb_len = get_fb_size_from_pci();
DEBUG_MSG(KERN_INFO "Get FB info from PCI system!\n");
DEBUG_MSG(KERN_INFO "fb_base = %08x\n", *fb_base);
DEBUG_MSG(KERN_INFO "fb_len = %08x\n", *fb_len);
pci_dev_put(pdev);
}
static int get_fb_size_from_pci(void)
int viafb_get_fb_size_from_pci(void)
{
unsigned long configid, deviceid, FBSize = 0;
int VideoMemSize;
@@ -2656,6 +2567,7 @@ static int get_fb_size_from_pci(void)
case P4M890_FUNCTION3:
case P4M900_FUNCTION3:
case VX800_FUNCTION3:
case VX855_FUNCTION3:
/*case CN750_FUNCTION3: */
outl(configid + 0xA0, (unsigned long)0xCF8);
FBSize = inl((unsigned long)0xCFC);
@@ -2719,6 +2631,10 @@ static int get_fb_size_from_pci(void)
VideoMemSize = (256 << 20); /*256M */
break;
case 0x00007000: /* Only on VX855/875 */
VideoMemSize = (512 << 20); /*512M */
break;
default:
VideoMemSize = (32 << 20); /*32M */
break;
@@ -2788,24 +2704,6 @@ void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\
}
}
void viafb_memory_pitch_patch(struct fb_info *info)
{
if (info->var.xres != info->var.xres_virtual) {
viafb_load_offset_reg(info->var.xres_virtual,
info->var.bits_per_pixel >> 3, IGA1);
if (viafb_SAMM_ON) {
viafb_load_offset_reg(viafb_second_virtual_xres,
viafb_bpp1 >> 3,
IGA2);
} else {
viafb_load_offset_reg(info->var.xres_virtual,
info->var.bits_per_pixel >> 3, IGA2);
}
}
}
/*According var's xres, yres fill var's other timing information*/
void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh,
int mode_index)

57
drivers/video/via/hw.h
View File

@@ -147,14 +147,8 @@ is reserved, so it may have problem to set 1600x1200 on IGA2. */
/* location: {CR5F,0,4} */
#define IGA2_VER_SYNC_END_REG_NUM 1
/* Define Offset and Fetch Count Register*/
/* Define Fetch Count Register*/
/* location: {CR13,0,7},{CR35,5,7} */
#define IGA1_OFFSET_REG_NUM 2
/* 8 bytes alignment. */
#define IGA1_OFFSER_ALIGN_BYTE 8
/* x: H resolution, y: color depth */
#define IGA1_OFFSET_FORMULA(x, y) ((x*y)/IGA1_OFFSER_ALIGN_BYTE)
/* location: {SR1C,0,7},{SR1D,0,1} */
#define IGA1_FETCH_COUNT_REG_NUM 2
/* 16 bytes alignment. */
@@ -164,11 +158,6 @@ is reserved, so it may have problem to set 1600x1200 on IGA2. */
#define IGA1_FETCH_COUNT_FORMULA(x, y) \
(((x*y)/IGA1_FETCH_COUNT_ALIGN_BYTE) + IGA1_FETCH_COUNT_PATCH_VALUE)
/* location: {CR66,0,7},{CR67,0,1} */
#define IGA2_OFFSET_REG_NUM 2
#define IGA2_OFFSET_ALIGN_BYTE 8
/* x: H resolution, y: color depth */
#define IGA2_OFFSET_FORMULA(x, y) ((x*y)/IGA2_OFFSET_ALIGN_BYTE)
/* location: {CR65,0,7},{CR67,2,3} */
#define IGA2_FETCH_COUNT_REG_NUM 2
#define IGA2_FETCH_COUNT_ALIGN_BYTE 16
@@ -335,6 +324,17 @@ is reserved, so it may have problem to set 1600x1200 on IGA2. */
/* location: {CR94,0,6} */
#define VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128
/* For VT3409 */
#define VX855_IGA1_FIFO_MAX_DEPTH 400
#define VX855_IGA1_FIFO_THRESHOLD 320
#define VX855_IGA1_FIFO_HIGH_THRESHOLD 320
#define VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 160
#define VX855_IGA2_FIFO_MAX_DEPTH 200
#define VX855_IGA2_FIFO_THRESHOLD 160
#define VX855_IGA2_FIFO_HIGH_THRESHOLD 160
#define VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 320
#define IGA1_FIFO_DEPTH_SELECT_REG_NUM 1
#define IGA1_FIFO_THRESHOLD_REG_NUM 2
#define IGA1_FIFO_HIGH_THRESHOLD_REG_NUM 2
@@ -617,23 +617,6 @@ struct iga2_ver_sync_end {
struct io_register reg[IGA2_VER_SYNC_END_REG_NUM];
};
/* IGA1 Offset Register */
struct iga1_offset {
int reg_num;
struct io_register reg[IGA1_OFFSET_REG_NUM];
};
/* IGA2 Offset Register */
struct iga2_offset {
int reg_num;
struct io_register reg[IGA2_OFFSET_REG_NUM];
};
struct offset {
struct iga1_offset iga1_offset_reg;
struct iga2_offset iga2_offset_reg;
};
/* IGA1 Fetch Count Register */
struct iga1_fetch_count {
int reg_num;
@@ -716,6 +699,7 @@ struct pll_map {
u32 cle266_pll;
u32 k800_pll;
u32 cx700_pll;
u32 vx855_pll;
};
struct rgbLUT {
@@ -860,6 +844,8 @@ struct iga2_crtc_timing {
#define P4M900_FUNCTION3 0x3364
/* VT3353 chipset*/
#define VX800_FUNCTION3 0x3353
/* VT3409 chipset*/
#define VX855_FUNCTION3 0x3409
#define NUM_TOTAL_PLL_TABLE ARRAY_SIZE(pll_value)
@@ -883,7 +869,6 @@ extern int viafb_dual_fb;
extern int viafb_LCD2_ON;
extern int viafb_LCD_ON;
extern int viafb_DVI_ON;
extern int viafb_accel;
extern int viafb_hotplug;
void viafb_write_reg_mask(u8 index, int io_port, u8 data, u8 mask);
@@ -904,7 +889,6 @@ void viafb_write_reg(u8 index, u16 io_port, u8 data);
u8 viafb_read_reg(int io_port, u8 index);
void viafb_lock_crt(void);
void viafb_unlock_crt(void);
void viafb_load_offset_reg(int h_addr, int bpp_byte, int set_iga);
void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga);
void viafb_write_regx(struct io_reg RegTable[], int ItemNum);
struct VideoModeTable *viafb_get_modetbl_pointer(int Index);
@@ -917,17 +901,20 @@ void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\
int viafb_setmode(int vmode_index, int hor_res, int ver_res,
int video_bpp, int vmode_index1, int hor_res1,
int ver_res1, int video_bpp1);
void viafb_init_chip_info(void);
void viafb_init_chip_info(struct pci_dev *pdev,
const struct pci_device_id *pdi);
void viafb_init_dac(int set_iga);
int viafb_get_pixclock(int hres, int vres, int vmode_refresh);
int viafb_get_refresh(int hres, int vres, u32 float_refresh);
void viafb_update_device_setting(int hres, int vres, int bpp,
int vmode_refresh, int flag);
void viafb_get_mmio_info(unsigned long *mmio_base,
unsigned long *mmio_len);
int viafb_get_fb_size_from_pci(void);
void viafb_set_iga_path(void);
void viafb_set_start_addr(void);
void viafb_set_primary_address(u32 addr);
void viafb_set_secondary_address(u32 addr);
void viafb_set_primary_pitch(u32 pitch);
void viafb_set_secondary_pitch(u32 pitch);
void viafb_get_fb_info(unsigned int *fb_base, unsigned int *fb_len);
#endif /* __HW_H__ */

6
drivers/video/via/ioctl.h
View File

@@ -50,8 +50,6 @@
#define VIAFB_GET_GAMMA_LUT 0x56494124
#define VIAFB_SET_GAMMA_LUT 0x56494125
#define VIAFB_GET_GAMMA_SUPPORT_STATE 0x56494126
#define VIAFB_SET_VIDEO_DEVICE 0x56494127
#define VIAFB_GET_VIDEO_DEVICE 0x56494128
#define VIAFB_SET_SECOND_MODE 0x56494129
#define VIAFB_SYNC_SURFACE 0x56494130
#define VIAFB_GET_DRIVER_CAPS 0x56494131
@@ -179,9 +177,7 @@ struct viafb_ioctl_setting {
unsigned short second_dev_bpp;
/* Indicate which device are primary display device. */
unsigned int primary_device;
/* Indicate which device will show video. only valid in duoview mode */
unsigned int video_device_status;
unsigned int struct_reserved[34];
unsigned int struct_reserved[35];
struct viafb_ioctl_lcd_attribute lcd_attributes;
};

16
drivers/video/via/lcd.c
View File

@@ -207,13 +207,13 @@ static bool lvds_identify_integratedlvds(void)
int viafb_lvds_trasmitter_identify(void)
{
viaparinfo->i2c_stuff.i2c_port = I2CPORTINDEX;
viaparinfo->shared->i2c_stuff.i2c_port = I2CPORTINDEX;
if (viafb_lvds_identify_vt1636()) {
viaparinfo->chip_info->lvds_chip_info.i2c_port = I2CPORTINDEX;
DEBUG_MSG(KERN_INFO
"Found VIA VT1636 LVDS on port i2c 0x31 \n");
} else {
viaparinfo->i2c_stuff.i2c_port = GPIOPORTINDEX;
viaparinfo->shared->i2c_stuff.i2c_port = GPIOPORTINDEX;
if (viafb_lvds_identify_vt1636()) {
viaparinfo->chip_info->lvds_chip_info.i2c_port =
GPIOPORTINDEX;
@@ -470,7 +470,7 @@ static int lvds_register_read(int index)
{
u8 data;
viaparinfo->i2c_stuff.i2c_port = GPIOPORTINDEX;
viaparinfo->shared->i2c_stuff.i2c_port = GPIOPORTINDEX;
viafb_i2c_readbyte((u8) viaparinfo->chip_info->
lvds_chip_info.lvds_chip_slave_addr,
(u8) index, &data);
@@ -952,13 +952,10 @@ void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table,
int video_index = plvds_setting_info->lcd_panel_size;
int set_iga = plvds_setting_info->iga_path;
int mode_bpp = plvds_setting_info->bpp;
int viafb_load_reg_num = 0;
int reg_value = 0;
int set_hres, set_vres;
int panel_hres, panel_vres;
u32 pll_D_N;
int offset;
struct io_register *reg = NULL;
struct display_timing mode_crt_reg, panel_crt_reg;
struct crt_mode_table *panel_crt_table = NULL;
struct VideoModeTable *vmode_tbl = NULL;
@@ -1038,16 +1035,11 @@ void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table,
}
/* Offset for simultaneous */
reg_value = offset;
viafb_load_reg_num = offset_reg.iga2_offset_reg.reg_num;
reg = offset_reg.iga2_offset_reg.reg;
viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
viafb_set_secondary_pitch(offset << 3);
DEBUG_MSG(KERN_INFO "viafb_load_reg!!\n");
viafb_load_fetch_count_reg(set_hres, 4, IGA2);
/* Fetch count for simultaneous */
} else { /* SAMM */
/* Offset for IGA2 only */
viafb_load_offset_reg(set_hres, mode_bpp / 8, set_iga);
/* Fetch count for IGA2 only */
viafb_load_fetch_count_reg(set_hres, mode_bpp / 8, set_iga);

98
drivers/video/via/share.h
View File

@@ -167,6 +167,10 @@
#define SR4B 0x4B
#define SR4C 0x4C
#define SR52 0x52
#define SR57 0x57
#define SR58 0x58
#define SR59 0x59
#define SR5D 0x5D
#define SR5E 0x5E
#define SR65 0x65
@@ -966,6 +970,100 @@
#define CX700_297_500M 0x00CE0403
#define CX700_122_614M 0x00870802
/* PLL for VX855 */
#define VX855_22_000M 0x007B1005
#define VX855_25_175M 0x008D1005
#define VX855_26_719M 0x00961005
#define VX855_26_880M 0x00961005
#define VX855_27_000M 0x00971005
#define VX855_29_581M 0x00A51005
#define VX855_29_829M 0x00641003
#define VX855_31_490M 0x00B01005
#define VX855_31_500M 0x00B01005
#define VX855_31_728M 0x008E1004
#define VX855_32_668M 0x00921004
#define VX855_36_000M 0x00A11004
#define VX855_40_000M 0x00700C05
#define VX855_41_291M 0x00730C05
#define VX855_43_163M 0x00790C05
#define VX855_45_250M 0x007F0C05 /* 45.46MHz */
#define VX855_46_000M 0x00670C04
#define VX855_46_996M 0x00690C04
#define VX855_48_000M 0x00860C05
#define VX855_48_875M 0x00890C05
#define VX855_49_500M 0x00530C03
#define VX855_52_406M 0x00580C03
#define VX855_52_977M 0x00940C05
#define VX855_56_250M 0x009D0C05
#define VX855_60_466M 0x00A90C05
#define VX855_61_500M 0x00AC0C05
#define VX855_65_000M 0x006D0C03
#define VX855_65_178M 0x00B60C05
#define VX855_66_750M 0x00700C03 /*67.116MHz */
#define VX855_67_295M 0x00BC0C05
#define VX855_68_179M 0x00BF0C05
#define VX855_68_369M 0x00BF0C05
#define VX855_69_924M 0x00C30C05
#define VX855_70_159M 0x00C30C05
#define VX855_72_000M 0x00A10C04
#define VX855_73_023M 0x00CC0C05
#define VX855_74_481M 0x00D10C05
#define VX855_78_750M 0x006E0805
#define VX855_79_466M 0x006F0805
#define VX855_80_136M 0x00700805
#define VX855_81_627M 0x00720805
#define VX855_83_375M 0x00750805
#define VX855_83_527M 0x00750805
#define VX855_83_950M 0x00750805
#define VX855_84_537M 0x00760805
#define VX855_84_750M 0x00760805 /* 84.537Mhz */
#define VX855_85_500M 0x00760805 /* 85.909080 MHz*/
#define VX855_85_860M 0x00760805
#define VX855_85_909M 0x00760805
#define VX855_88_750M 0x007C0805
#define VX855_89_489M 0x007D0805
#define VX855_94_500M 0x00840805
#define VX855_96_648M 0x00870805
#define VX855_97_750M 0x00890805
#define VX855_101_000M 0x008D0805
#define VX855_106_500M 0x00950805
#define VX855_108_000M 0x00970805
#define VX855_110_125M 0x00990805
#define VX855_112_000M 0x009D0805
#define VX855_113_309M 0x009F0805
#define VX855_115_000M 0x00A10805
#define VX855_118_840M 0x00A60805
#define VX855_119_000M 0x00A70805
#define VX855_121_750M 0x00AA0805 /* 121.704MHz */
#define VX855_122_614M 0x00AC0805
#define VX855_126_266M 0x00B10805
#define VX855_130_250M 0x00B60805 /* 130.250 */
#define VX855_135_000M 0x00BD0805
#define VX855_136_700M 0x00BF0805
#define VX855_137_750M 0x00C10805
#define VX855_138_400M 0x00C20805
#define VX855_144_300M 0x00CA0805
#define VX855_146_760M 0x00CE0805
#define VX855_148_500M 0x00D00805
#define VX855_153_920M 0x00540402
#define VX855_156_000M 0x006C0405
#define VX855_156_867M 0x006E0405
#define VX855_157_500M 0x006E0405
#define VX855_162_000M 0x00710405
#define VX855_172_798M 0x00790405
#define VX855_187_000M 0x00830405
#define VX855_193_295M 0x00870405
#define VX855_202_500M 0x008E0405
#define VX855_204_000M 0x008F0405
#define VX855_218_500M 0x00990405
#define VX855_229_500M 0x00A10405
#define VX855_234_000M 0x00A40405
#define VX855_267_250M 0x00BB0405
#define VX855_297_500M 0x00D00405
#define VX855_339_500M 0x00770005
#define VX855_340_772M 0x00770005
/* Definition CRTC Timing Index */
#define H_TOTAL_INDEX 0
#define H_ADDR_INDEX 1

60
drivers/video/via/via_i2c.c
View File

@@ -97,7 +97,7 @@ int viafb_i2c_readbyte(u8 slave_addr, u8 index, u8 *pdata)
mm1[0] = index;
msgs[0].len = 1; msgs[1].len = 1;
msgs[0].buf = mm1; msgs[1].buf = pdata;
i2c_transfer(&viaparinfo->i2c_stuff.adapter, msgs, 2);
i2c_transfer(&viaparinfo->shared->i2c_stuff.adapter, msgs, 2);
return 0;
}
@@ -111,7 +111,7 @@ int viafb_i2c_writebyte(u8 slave_addr, u8 index, u8 data)
msgs.addr = slave_addr / 2;
msgs.len = 2;
msgs.buf = msg;
return i2c_transfer(&viaparinfo->i2c_stuff.adapter, &msgs, 1);
return i2c_transfer(&viaparinfo->shared->i2c_stuff.adapter, &msgs, 1);
}
int viafb_i2c_readbytes(u8 slave_addr, u8 index, u8 *buff, int buff_len)
@@ -125,53 +125,53 @@ int viafb_i2c_readbytes(u8 slave_addr, u8 index, u8 *buff, int buff_len)
mm1[0] = index;
msgs[0].len = 1; msgs[1].len = buff_len;
msgs[0].buf = mm1; msgs[1].buf = buff;
i2c_transfer(&viaparinfo->i2c_stuff.adapter, msgs, 2);
i2c_transfer(&viaparinfo->shared->i2c_stuff.adapter, msgs, 2);
return 0;
}
int viafb_create_i2c_bus(void *viapar)
{
int ret;
struct viafb_par *par = (struct viafb_par *)viapar;
struct via_i2c_stuff *i2c_stuff =
&((struct viafb_par *)viapar)->shared->i2c_stuff;
strcpy(par->i2c_stuff.adapter.name, "via_i2c");
par->i2c_stuff.i2c_port = 0x0;
par->i2c_stuff.adapter.owner = THIS_MODULE;
par->i2c_stuff.adapter.id = 0x01FFFF;
par->i2c_stuff.adapter.class = 0;
par->i2c_stuff.adapter.algo_data = &par->i2c_stuff.algo;
par->i2c_stuff.adapter.dev.parent = NULL;
par->i2c_stuff.algo.setsda = via_i2c_setsda;
par->i2c_stuff.algo.setscl = via_i2c_setscl;
par->i2c_stuff.algo.getsda = via_i2c_getsda;
par->i2c_stuff.algo.getscl = via_i2c_getscl;
par->i2c_stuff.algo.udelay = 40;
par->i2c_stuff.algo.timeout = 20;
par->i2c_stuff.algo.data = &par->i2c_stuff;
strcpy(i2c_stuff->adapter.name, "via_i2c");
i2c_stuff->i2c_port = 0x0;
i2c_stuff->adapter.owner = THIS_MODULE;
i2c_stuff->adapter.id = 0x01FFFF;
i2c_stuff->adapter.class = 0;
i2c_stuff->adapter.algo_data = &i2c_stuff->algo;
i2c_stuff->adapter.dev.parent = NULL;
i2c_stuff->algo.setsda = via_i2c_setsda;
i2c_stuff->algo.setscl = via_i2c_setscl;
i2c_stuff->algo.getsda = via_i2c_getsda;
i2c_stuff->algo.getscl = via_i2c_getscl;
i2c_stuff->algo.udelay = 40;
i2c_stuff->algo.timeout = 20;
i2c_stuff->algo.data = i2c_stuff;
i2c_set_adapdata(&par->i2c_stuff.adapter, &par->i2c_stuff);
i2c_set_adapdata(&i2c_stuff->adapter, i2c_stuff);
/* Raise SCL and SDA */
par->i2c_stuff.i2c_port = I2CPORTINDEX;
via_i2c_setsda(&par->i2c_stuff, 1);
via_i2c_setscl(&par->i2c_stuff, 1);
i2c_stuff->i2c_port = I2CPORTINDEX;
via_i2c_setsda(i2c_stuff, 1);
via_i2c_setscl(i2c_stuff, 1);
par->i2c_stuff.i2c_port = GPIOPORTINDEX;
via_i2c_setsda(&par->i2c_stuff, 1);
via_i2c_setscl(&par->i2c_stuff, 1);
i2c_stuff->i2c_port = GPIOPORTINDEX;
via_i2c_setsda(i2c_stuff, 1);
via_i2c_setscl(i2c_stuff, 1);
udelay(20);
ret = i2c_bit_add_bus(&par->i2c_stuff.adapter);
ret = i2c_bit_add_bus(&i2c_stuff->adapter);
if (ret == 0)
DEBUG_MSG("I2C bus %s registered.\n",
par->i2c_stuff.adapter.name);
DEBUG_MSG("I2C bus %s registered.\n", i2c_stuff->adapter.name);
else
DEBUG_MSG("Failed to register I2C bus %s.\n",
par->i2c_stuff.adapter.name);
i2c_stuff->adapter.name);
return ret;
}
void viafb_delete_i2c_buss(void *par)
{
i2c_del_adapter(&((struct viafb_par *)par)->i2c_stuff.adapter);
i2c_del_adapter(&((struct viafb_par *)par)->shared->i2c_stuff.adapter);
}

1049
drivers/video/via/viafbdev.c
View File

File diff suppressed because it is too large Load Diff

67
drivers/video/via/viafbdev.h
View File

@@ -37,51 +37,50 @@
#define VERSION_OS 0 /* 0: for 32 bits OS, 1: for 64 bits OS */
#define VERSION_MINOR 4
struct viafb_par {
int bpp;
int hres;
int vres;
int linelength;
u32 xoffset;
u32 yoffset;
void __iomem *fbmem_virt; /*framebuffer virtual memory address */
void __iomem *io_virt; /*iospace virtual memory address */
unsigned int fbmem; /*framebuffer physical memory address */
unsigned int memsize; /*size of fbmem */
unsigned int io; /*io space address */
unsigned long mmio_base; /*mmio base address */
unsigned long mmio_len; /*mmio base length */
u32 fbmem_free; /* Free FB memory */
u32 fbmem_used; /* Use FB memory size */
u32 cursor_start; /* Cursor Start Address */
u32 VQ_start; /* Virtual Queue Start Address */
u32 VQ_end; /* Virtual Queue End Address */
u32 iga_path;
struct viafb_shared {
struct proc_dir_entry *proc_entry; /*viafb proc entry */
u8 duoview; /*Is working in duoview mode? */
/* I2C stuff */
struct via_i2c_stuff i2c_stuff;
/* All the information will be needed to set engine */
struct tmds_setting_information tmds_setting_info;
struct crt_setting_information crt_setting_info;
struct lvds_setting_information lvds_setting_info;
struct lvds_setting_information lvds_setting_info2;
struct chip_information chip_info;
/* hardware acceleration stuff */
void __iomem *engine_mmio;
u32 cursor_vram_addr;
u32 vq_vram_addr; /* virtual queue address in video ram */
int (*hw_bitblt)(void __iomem *engine, u8 op, u32 width, u32 height,
u8 dst_bpp, u32 dst_addr, u32 dst_pitch, u32 dst_x, u32 dst_y,
u32 *src_mem, u32 src_addr, u32 src_pitch, u32 src_x, u32 src_y,
u32 fg_color, u32 bg_color, u8 fill_rop);
};
struct viafb_par {
u8 depth;
u32 vram_addr;
unsigned int fbmem; /*framebuffer physical memory address */
unsigned int memsize; /*size of fbmem */
u32 fbmem_free; /* Free FB memory */
u32 fbmem_used; /* Use FB memory size */
u32 iga_path;
struct viafb_shared *shared;
/* All the information will be needed to set engine */
/* depreciated, use the ones in shared directly */
struct tmds_setting_information *tmds_setting_info;
struct crt_setting_information *crt_setting_info;
struct lvds_setting_information *lvds_setting_info;
struct lvds_setting_information *lvds_setting_info2;
struct chip_information *chip_info;
/* some information related to video playing */
int video_on_crt;
int video_on_dvi;
int video_on_lcd;
};
struct viafb_modeinfo {
u32 xres;
u32 yres;
int mode_index;
};
extern unsigned int viafb_second_virtual_yres;
extern unsigned int viafb_second_virtual_xres;
extern unsigned int viafb_second_offset;
@@ -91,14 +90,12 @@ extern int viafb_dual_fb;
extern int viafb_LCD2_ON;
extern int viafb_LCD_ON;
extern int viafb_DVI_ON;
extern int viafb_accel;
extern int viafb_hotplug;
extern int viafb_memsize;
extern int strict_strtoul(const char *cp, unsigned int base,
unsigned long *res);
void viafb_memory_pitch_patch(struct fb_info *info);
void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh,
int mode_index);
int viafb_get_mode_index(int hres, int vres);

100
drivers/video/via/viamode.c
View File

@@ -100,12 +100,8 @@ struct io_reg CN400_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
{VIACR, CR0F, 0xFF, 0x00}, /* Cursor Localtion Low */
{VIACR, CR32, 0xFF, 0x00},
{VIACR, CR33, 0xFF, 0x00},
{VIACR, CR34, 0xFF, 0x00},
{VIACR, CR35, 0xFF, 0x00},
{VIACR, CR36, 0x08, 0x00},
{VIACR, CR62, 0xFF, 0x00}, /* Secondary Display Starting Address */
{VIACR, CR63, 0xFF, 0x00}, /* Secondary Display Starting Address */
{VIACR, CR64, 0xFF, 0x00}, /* Secondary Display Starting Address */
{VIACR, CR69, 0xFF, 0x00},
{VIACR, CR6A, 0xFF, 0x40},
{VIACR, CR6B, 0xFF, 0x00},
@@ -159,16 +155,12 @@ struct io_reg CN700_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
{VIASR, CR30, 0xFF, 0x04},
{VIACR, CR32, 0xFF, 0x00},
{VIACR, CR33, 0x7F, 0x00},
{VIACR, CR34, 0xFF, 0x00},
{VIACR, CR35, 0xFF, 0x00},
{VIACR, CR36, 0xFF, 0x31},
{VIACR, CR41, 0xFF, 0x80},
{VIACR, CR42, 0xFF, 0x00},
{VIACR, CR55, 0x80, 0x00},
{VIACR, CR5D, 0x80, 0x00}, /*Horizontal Retrace Start bit[11] should be 0*/
{VIACR, CR62, 0xFF, 0x00}, /* Secondary Display Starting Address */
{VIACR, CR63, 0xFF, 0x00}, /* Secondary Display Starting Address */
{VIACR, CR64, 0xFF, 0x00}, /* Secondary Display Starting Address */
{VIACR, CR68, 0xFF, 0x67}, /* Default FIFO For IGA2 */
{VIACR, CR69, 0xFF, 0x00},
{VIACR, CR6A, 0xFD, 0x40},
@@ -233,9 +225,6 @@ struct io_reg KM400_ModeXregs[] = {
{VIACR, CR55, 0x80, 0x00},
{VIACR, CR5D, 0x80, 0x00},
{VIACR, CR36, 0xFF, 0x01}, /* Power Mangement 3 */
{VIACR, CR62, 0xFF, 0x00}, /* Secondary Display Starting Address */
{VIACR, CR63, 0xFF, 0x00}, /* Secondary Display Starting Address */
{VIACR, CR64, 0xFF, 0x00}, /* Secondary Display Starting Address */
{VIACR, CR68, 0xFF, 0x67}, /* Default FIFO For IGA2 */
{VIACR, CR6A, 0x20, 0x20}, /* Extended FIFO On */
{VIACR, CR7A, 0xFF, 0x01}, /* LCD Scaling Parameter 1 */
@@ -285,14 +274,9 @@ struct io_reg CX700_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
{VIACR, CR0F, 0xFF, 0x00}, /* Cursor Localtion Low */
{VIACR, CR32, 0xFF, 0x00},
{VIACR, CR33, 0xFF, 0x00},
{VIACR, CR34, 0xFF, 0x00},
{VIACR, CR35, 0xFF, 0x00},
{VIACR, CR36, 0x08, 0x00},
{VIACR, CR47, 0xC8, 0x00}, /* Clear VCK Plus. */
{VIACR, CR62, 0xFF, 0x00}, /* Secondary Display Starting Address */
{VIACR, CR63, 0xFF, 0x00}, /* Secondary Display Starting Address */
{VIACR, CR64, 0xFF, 0x00}, /* Secondary Display Starting Address */
{VIACR, CRA3, 0xFF, 0x00}, /* Secondary Display Starting Address */
{VIACR, CR69, 0xFF, 0x00},
{VIACR, CR6A, 0xFF, 0x40},
{VIACR, CR6B, 0xFF, 0x00},
@@ -325,69 +309,61 @@ struct io_reg CX700_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
{VIACR, CR96, 0xFF, 0x00},
{VIACR, CR97, 0xFF, 0x00},
{VIACR, CR99, 0xFF, 0x00},
{VIACR, CR9B, 0xFF, 0x00},
{VIACR, CRD2, 0xFF, 0xFF} /* TMDS/LVDS control register. */
{VIACR, CR9B, 0xFF, 0x00}
};
/* For VT3353: Common Setting for Video Mode */
struct io_reg VX800_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
struct io_reg VX855_ModeXregs[] = {
{VIASR, SR10, 0xFF, 0x01},
{VIASR, SR15, 0x02, 0x02},
{VIASR, SR16, 0xBF, 0x08},
{VIASR, SR17, 0xFF, 0x1F},
{VIASR, SR18, 0xFF, 0x4E},
{VIASR, SR1A, 0xFB, 0x08},
{VIASR, SR1B, 0xFF, 0xF0},
{VIASR, SR1E, 0xFF, 0x01},
{VIASR, SR2A, 0xFF, 0x00},
{VIASR, SR1E, 0x07, 0x01},
{VIASR, SR2A, 0xF0, 0x00},
{VIASR, SR58, 0xFF, 0x00},
{VIASR, SR59, 0xFF, 0x00},
{VIASR, SR2D, 0xFF, 0xFF}, /* VCK and LCK PLL power on. */
{VIACR, CR09, 0xFF, 0x00}, /* Initial CR09=0*/
{VIACR, CR11, 0x8F, 0x00}, /* IGA1 initial Vertical end */
{VIACR, CR17, 0x7F, 0x00}, /* IGA1 CRT Mode control init */
{VIACR, CR0A, 0xFF, 0x1E}, /* Cursor Start */
{VIACR, CR0B, 0xFF, 0x00}, /* Cursor End */
{VIACR, CR0E, 0xFF, 0x00}, /* Cursor Location High */
{VIACR, CR0F, 0xFF, 0x00}, /* Cursor Localtion Low */
{VIACR, CR32, 0xFF, 0x00},
{VIACR, CR33, 0xFF, 0x00},
{VIACR, CR34, 0xFF, 0x00},
{VIACR, CR33, 0x7F, 0x00},
{VIACR, CR35, 0xFF, 0x00},
{VIACR, CR36, 0x08, 0x00},
{VIACR, CR47, 0xC8, 0x00}, /* Clear VCK Plus. */
{VIACR, CR62, 0xFF, 0x00}, /* Secondary Display Starting Address */
{VIACR, CR63, 0xFF, 0x00}, /* Secondary Display Starting Address */
{VIACR, CR64, 0xFF, 0x00}, /* Secondary Display Starting Address */
{VIACR, CRA3, 0xFF, 0x00}, /* Secondary Display Starting Address */
{VIACR, CR69, 0xFF, 0x00},
{VIACR, CR6A, 0xFF, 0x40},
{VIACR, CR6A, 0xFD, 0x60},
{VIACR, CR6B, 0xFF, 0x00},
{VIACR, CR6C, 0xFF, 0x00},
{VIACR, CR7A, 0xFF, 0x01}, /* LCD Scaling Parameter 1 */
{VIACR, CR7B, 0xFF, 0x02}, /* LCD Scaling Parameter 2 */
{VIACR, CR7C, 0xFF, 0x03}, /* LCD Scaling Parameter 3 */
{VIACR, CR7D, 0xFF, 0x04}, /* LCD Scaling Parameter 4 */
{VIACR, CR7E, 0xFF, 0x07}, /* LCD Scaling Parameter 5 */
{VIACR, CR7F, 0xFF, 0x0A}, /* LCD Scaling Parameter 6 */
{VIACR, CR80, 0xFF, 0x0D}, /* LCD Scaling Parameter 7 */
{VIACR, CR81, 0xFF, 0x13}, /* LCD Scaling Parameter 8 */
{VIACR, CR82, 0xFF, 0x16}, /* LCD Scaling Parameter 9 */
{VIACR, CR83, 0xFF, 0x19}, /* LCD Scaling Parameter 10 */
{VIACR, CR84, 0xFF, 0x1C}, /* LCD Scaling Parameter 11 */
{VIACR, CR85, 0xFF, 0x1D}, /* LCD Scaling Parameter 12 */
{VIACR, CR86, 0xFF, 0x1E}, /* LCD Scaling Parameter 13 */
{VIACR, CR87, 0xFF, 0x1F}, /* LCD Scaling Parameter 14 */
{VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */
{VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */
{VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */
{VIACR, CRD4, 0xFF, 0x81}, /* Second power sequence control */
{VIACR, CR8B, 0xFF, 0x5D}, /* LCD Power Sequence Control 0 */
{VIACR, CR8C, 0xFF, 0x2B}, /* LCD Power Sequence Control 1 */
{VIACR, CR8D, 0xFF, 0x6F}, /* LCD Power Sequence Control 2 */
{VIACR, CR8E, 0xFF, 0x2B}, /* LCD Power Sequence Control 3 */
{VIACR, CR8F, 0xFF, 0x01}, /* LCD Power Sequence Control 4 */
{VIACR, CR90, 0xFF, 0x01}, /* LCD Power Sequence Control 5 */
{VIACR, CR91, 0xFF, 0x80}, /* 24/12 bit LVDS Data off */
{VIACR, CR7A, 0xFF, 0x01}, /* LCD Scaling Parameter 1 */
{VIACR, CR7B, 0xFF, 0x02}, /* LCD Scaling Parameter 2 */
{VIACR, CR7C, 0xFF, 0x03}, /* LCD Scaling Parameter 3 */
{VIACR, CR7D, 0xFF, 0x04}, /* LCD Scaling Parameter 4 */
{VIACR, CR7E, 0xFF, 0x07}, /* LCD Scaling Parameter 5 */
{VIACR, CR7F, 0xFF, 0x0A}, /* LCD Scaling Parameter 6 */
{VIACR, CR80, 0xFF, 0x0D}, /* LCD Scaling Parameter 7 */
{VIACR, CR81, 0xFF, 0x13}, /* LCD Scaling Parameter 8 */
{VIACR, CR82, 0xFF, 0x16}, /* LCD Scaling Parameter 9 */
{VIACR, CR83, 0xFF, 0x19}, /* LCD Scaling Parameter 10 */
{VIACR, CR84, 0xFF, 0x1C}, /* LCD Scaling Parameter 11 */
{VIACR, CR85, 0xFF, 0x1D}, /* LCD Scaling Parameter 12 */
{VIACR, CR86, 0xFF, 0x1E}, /* LCD Scaling Parameter 13 */
{VIACR, CR87, 0xFF, 0x1F}, /* LCD Scaling Parameter 14 */
{VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */
{VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */
{VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */
{VIACR, CRD4, 0xFF, 0x81}, /* Second power sequence control */
{VIACR, CR91, 0xFF, 0x80}, /* 24/12 bit LVDS Data off */
{VIACR, CR96, 0xFF, 0x00},
{VIACR, CR97, 0xFF, 0x00},
{VIACR, CR99, 0xFF, 0x00},
{VIACR, CR9B, 0xFF, 0x00},
{VIACR, CRD2, 0xFF, 0xFF} /* TMDS/LVDS control register. */
{VIACR, CRD2, 0xFF, 0xFF} /* TMDS/LVDS control register. */
};
/* Video Mode Table */
@@ -401,7 +377,6 @@ struct io_reg CLE266_ModeXregs[] = { {VIASR, SR1E, 0xF0, 0x00},
{VIASR, SR1A, 0xFB, 0x08},
{VIACR, CR32, 0xFF, 0x00},
{VIACR, CR34, 0xFF, 0x00},
{VIACR, CR35, 0xFF, 0x00},
{VIACR, CR36, 0x08, 0x00},
{VIACR, CR6A, 0xFF, 0x80},
@@ -1084,3 +1059,14 @@ struct VideoModeTable CEA_HDMI_Modes[] = {
{VIA_RES_1280X720, CEAM1280x720, ARRAY_SIZE(CEAM1280x720)},
{VIA_RES_1920X1080, CEAM1920x1080, ARRAY_SIZE(CEAM1920x1080)}
};
int NUM_TOTAL_RES_MAP_REFRESH = ARRAY_SIZE(res_map_refresh_tbl);
int NUM_TOTAL_CEA_MODES = ARRAY_SIZE(CEA_HDMI_Modes);
int NUM_TOTAL_CN400_ModeXregs = ARRAY_SIZE(CN400_ModeXregs);
int NUM_TOTAL_CN700_ModeXregs = ARRAY_SIZE(CN700_ModeXregs);
int NUM_TOTAL_KM400_ModeXregs = ARRAY_SIZE(KM400_ModeXregs);
int NUM_TOTAL_CX700_ModeXregs = ARRAY_SIZE(CX700_ModeXregs);
int NUM_TOTAL_VX855_ModeXregs = ARRAY_SIZE(VX855_ModeXregs);
int NUM_TOTAL_CLE266_ModeXregs = ARRAY_SIZE(CLE266_ModeXregs);
int NUM_TOTAL_PATCH_MODE = ARRAY_SIZE(res_patch_table);
int NUM_TOTAL_MODETABLE = ARRAY_SIZE(CLE266Modes);

141
drivers/video/via/viamode.h
View File

@@ -50,128 +50,35 @@ struct res_map_refresh {
int vmode_refresh;
};
#define NUM_TOTAL_RES_MAP_REFRESH ARRAY_SIZE(res_map_refresh_tbl)
#define NUM_TOTAL_CEA_MODES ARRAY_SIZE(CEA_HDMI_Modes)
#define NUM_TOTAL_CN400_ModeXregs ARRAY_SIZE(CN400_ModeXregs)
#define NUM_TOTAL_CN700_ModeXregs ARRAY_SIZE(CN700_ModeXregs)
#define NUM_TOTAL_KM400_ModeXregs ARRAY_SIZE(KM400_ModeXregs)
#define NUM_TOTAL_CX700_ModeXregs ARRAY_SIZE(CX700_ModeXregs)
#define NUM_TOTAL_VX800_ModeXregs ARRAY_SIZE(VX800_ModeXregs)
#define NUM_TOTAL_CLE266_ModeXregs ARRAY_SIZE(CLE266_ModeXregs)
#define NUM_TOTAL_PATCH_MODE ARRAY_SIZE(res_patch_table)
#define NUM_TOTAL_MODETABLE ARRAY_SIZE(CLE266Modes)
extern int NUM_TOTAL_RES_MAP_REFRESH;
extern int NUM_TOTAL_CEA_MODES;
extern int NUM_TOTAL_CN400_ModeXregs;
extern int NUM_TOTAL_CN700_ModeXregs;
extern int NUM_TOTAL_KM400_ModeXregs;
extern int NUM_TOTAL_CX700_ModeXregs;
extern int NUM_TOTAL_VX855_ModeXregs;
extern int NUM_TOTAL_CLE266_ModeXregs;
extern int NUM_TOTAL_PATCH_MODE;
extern int NUM_TOTAL_MODETABLE;
/********************/
/* Mode Table */
/********************/
/* 480x640 */
extern struct crt_mode_table CRTM480x640[1];
/* 640x480*/
extern struct crt_mode_table CRTM640x480[5];
/*720x480 (GTF)*/
extern struct crt_mode_table CRTM720x480[1];
/*720x576 (GTF)*/
extern struct crt_mode_table CRTM720x576[1];
/* 800x480 (CVT) */
extern struct crt_mode_table CRTM800x480[1];
/* 800x600*/
extern struct crt_mode_table CRTM800x600[5];
/* 848x480 (CVT) */
extern struct crt_mode_table CRTM848x480[1];
/*856x480 (GTF) convert to 852x480*/
extern struct crt_mode_table CRTM852x480[1];
/*1024x512 (GTF)*/
extern struct crt_mode_table CRTM1024x512[1];
/* 1024x600*/
extern struct crt_mode_table CRTM1024x600[1];
/* 1024x768*/
extern struct crt_mode_table CRTM1024x768[4];
/* 1152x864*/
extern struct crt_mode_table CRTM1152x864[1];
/* 1280x720 (HDMI 720P)*/
extern struct crt_mode_table CRTM1280x720[2];
/*1280x768 (GTF)*/
extern struct crt_mode_table CRTM1280x768[2];
/* 1280x800 (CVT) */
extern struct crt_mode_table CRTM1280x800[1];
/*1280x960*/
extern struct crt_mode_table CRTM1280x960[1];
/* 1280x1024*/
extern struct crt_mode_table CRTM1280x1024[3];
/* 1368x768 (GTF) */
extern struct crt_mode_table CRTM1368x768[1];
/*1440x1050 (GTF)*/
extern struct crt_mode_table CRTM1440x1050[1];
/* 1600x1200*/
extern struct crt_mode_table CRTM1600x1200[2];
/* 1680x1050 (CVT) */
extern struct crt_mode_table CRTM1680x1050[2];
/* 1680x1050 (CVT Reduce Blanking) */
extern struct crt_mode_table CRTM1680x1050_RB[1];
/* 1920x1080 (CVT)*/
extern struct crt_mode_table CRTM1920x1080[1];
/* 1920x1080 (CVT with Reduce Blanking) */
extern struct crt_mode_table CRTM1920x1080_RB[1];
/* 1920x1440*/
extern struct crt_mode_table CRTM1920x1440[2];
/* 1400x1050 (CVT) */
extern struct crt_mode_table CRTM1400x1050[2];
/* 1400x1050 (CVT Reduce Blanking) */
extern struct crt_mode_table CRTM1400x1050_RB[1];
/* 960x600 (CVT) */
extern struct crt_mode_table CRTM960x600[1];
/* 1000x600 (GTF) */
extern struct crt_mode_table CRTM1000x600[1];
/* 1024x576 (GTF) */
extern struct crt_mode_table CRTM1024x576[1];
/* 1088x612 (CVT) */
extern struct crt_mode_table CRTM1088x612[1];
/* 1152x720 (CVT) */
extern struct crt_mode_table CRTM1152x720[1];
/* 1200x720 (GTF) */
extern struct crt_mode_table CRTM1200x720[1];
/* 1280x600 (GTF) */
extern struct crt_mode_table CRTM1280x600[1];
/* 1360x768 (CVT) */
extern struct crt_mode_table CRTM1360x768[1];
/* 1360x768 (CVT Reduce Blanking) */
extern struct crt_mode_table CRTM1360x768_RB[1];
/* 1366x768 (GTF) */
extern struct crt_mode_table CRTM1366x768[2];
/* 1440x900 (CVT) */
extern struct crt_mode_table CRTM1440x900[2];
/* 1440x900 (CVT Reduce Blanking) */
extern struct crt_mode_table CRTM1440x900_RB[1];
/* 1600x900 (CVT) */
extern struct crt_mode_table CRTM1600x900[1];
/* 1600x900 (CVT Reduce Blanking) */
extern struct crt_mode_table CRTM1600x900_RB[1];
/* 1600x1024 (GTF) */
extern struct crt_mode_table CRTM1600x1024[1];
/* 1792x1344 (DMT) */
extern struct crt_mode_table CRTM1792x1344[1];
/* 1856x1392 (DMT) */
extern struct crt_mode_table CRTM1856x1392[1];
/* 1920x1200 (CVT) */
extern struct crt_mode_table CRTM1920x1200[1];
/* 1920x1200 (CVT with Reduce Blanking) */
extern struct crt_mode_table CRTM1920x1200_RB[1];
/* 2048x1536 (CVT) */
extern struct crt_mode_table CRTM2048x1536[1];
extern struct VideoModeTable CLE266Modes[47];
extern struct crt_mode_table CEAM1280x720[1];
extern struct crt_mode_table CEAM1920x1080[1];
extern struct VideoModeTable CEA_HDMI_Modes[2];
extern struct VideoModeTable CLE266Modes[];
extern struct crt_mode_table CEAM1280x720[];
extern struct crt_mode_table CEAM1920x1080[];
extern struct VideoModeTable CEA_HDMI_Modes[];
extern struct res_map_refresh res_map_refresh_tbl[61];
extern struct io_reg CN400_ModeXregs[52];
extern struct io_reg CN700_ModeXregs[66];
extern struct io_reg KM400_ModeXregs[55];
extern struct io_reg CX700_ModeXregs[58];
extern struct io_reg VX800_ModeXregs[58];
extern struct io_reg CLE266_ModeXregs[32];
extern struct io_reg PM1024x768[2];
extern struct patch_table res_patch_table[1];
extern struct res_map_refresh res_map_refresh_tbl[];
extern struct io_reg CN400_ModeXregs[];
extern struct io_reg CN700_ModeXregs[];
extern struct io_reg KM400_ModeXregs[];
extern struct io_reg CX700_ModeXregs[];
extern struct io_reg VX800_ModeXregs[];
extern struct io_reg VX855_ModeXregs[];
extern struct io_reg CLE266_ModeXregs[];
extern struct io_reg PM1024x768[];
extern struct patch_table res_patch_table[];
extern struct VPITTable VPIT;
#endif /* __VIAMODE_H__ */

4
drivers/video/via/vt1636.c
View File

@@ -27,7 +27,7 @@ u8 viafb_gpio_i2c_read_lvds(struct lvds_setting_information
{
u8 data;
viaparinfo->i2c_stuff.i2c_port = plvds_chip_info->i2c_port;
viaparinfo->shared->i2c_stuff.i2c_port = plvds_chip_info->i2c_port;
viafb_i2c_readbyte(plvds_chip_info->lvds_chip_slave_addr, index, &data);
return data;
@@ -39,7 +39,7 @@ void viafb_gpio_i2c_write_mask_lvds(struct lvds_setting_information
{
int index, data;
viaparinfo->i2c_stuff.i2c_port = plvds_chip_info->i2c_port;
viaparinfo->shared->i2c_stuff.i2c_port = plvds_chip_info->i2c_port;
index = io_data.Index;
data = viafb_gpio_i2c_read_lvds(plvds_setting_info, plvds_chip_info,