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MIPS: Rearrange ENTRYLO field definitions

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The generic field definitions (i.e. present before MIPS32/MIPS64) in
mipsregs.h are conventionally not prefixed with MIPS_, so rename the
recently added MIPS_ENTRYLO_* definitions for the G, V, D, and C fields
to ENTRYLO_*. Also rearrange to put the EntryLo and EntryHi definitions
in the right place in the file.

Fixes: 8ab6abcb6a ("MIPS: mipsregs.h: Add EntryLo bit definitions")
Reported-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10725/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
James Hogan
2015-07-15 16:17:47 +01:00
committed by Ralf Baechle
parent 9bd860cae3
commit bae637a214
2 changed files with 36 additions and 34 deletions
Download Patch File Download Diff File Expand all files Collapse all files

52
arch/mips/include/asm/mipsregs.h
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@@ -112,6 +112,30 @@
#define CP0_TX39_CACHE $7
/* Generic EntryLo bit definitions */
#define ENTRYLO_G (_ULCAST_(1) << 0)
#define ENTRYLO_V (_ULCAST_(1) << 1)
#define ENTRYLO_D (_ULCAST_(1) << 2)
#define ENTRYLO_C_SHIFT 3
#define ENTRYLO_C (_ULCAST_(7) << ENTRYLO_C_SHIFT)
/* R3000 EntryLo bit definitions */
#define R3K_ENTRYLO_G (_ULCAST_(1) << 8)
#define R3K_ENTRYLO_V (_ULCAST_(1) << 9)
#define R3K_ENTRYLO_D (_ULCAST_(1) << 10)
#define R3K_ENTRYLO_N (_ULCAST_(1) << 11)
/* MIPS32/64 EntryLo bit definitions */
#ifdef CONFIG_64BIT
/* as read by dmfc0 */
#define MIPS_ENTRYLO_XI (_ULCAST_(1) << 62)
#define MIPS_ENTRYLO_RI (_ULCAST_(1) << 63)
#else
/* as read by mfc0 */
#define MIPS_ENTRYLO_XI (_ULCAST_(1) << 30)
#define MIPS_ENTRYLO_RI (_ULCAST_(1) << 31)
#endif
/*
* Values for PageMask register
*/
@@ -203,6 +227,9 @@
#define PG_ESP (_ULCAST_(1) << 28)
#define PG_IEC (_ULCAST_(1) << 27)
/* MIPS32/64 EntryHI bit definitions */
#define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10)
/*
* R4x00 interrupt enable / cause bits
*/
@@ -588,31 +615,6 @@
#define MIPS_MAAR_S (_ULCAST_(1) << 1)
#define MIPS_MAAR_V (_ULCAST_(1) << 0)
/* EntryHI bit definition */
#define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10)
/* R3000 EntryLo bit definitions */
#define R3K_ENTRYLO_G (_ULCAST_(1) << 8)
#define R3K_ENTRYLO_V (_ULCAST_(1) << 9)
#define R3K_ENTRYLO_D (_ULCAST_(1) << 10)
#define R3K_ENTRYLO_N (_ULCAST_(1) << 11)
/* R4000 compatible EntryLo bit definitions */
#define MIPS_ENTRYLO_G (_ULCAST_(1) << 0)
#define MIPS_ENTRYLO_V (_ULCAST_(1) << 1)
#define MIPS_ENTRYLO_D (_ULCAST_(1) << 2)
#define MIPS_ENTRYLO_C_SHIFT 3
#define MIPS_ENTRYLO_C (_ULCAST_(7) << MIPS_ENTRYLO_C_SHIFT)
#ifdef CONFIG_64BIT
/* as read by dmfc0 */
#define MIPS_ENTRYLO_XI (_ULCAST_(1) << 62)
#define MIPS_ENTRYLO_RI (_ULCAST_(1) << 63)
#else
/* as read by mfc0 */
#define MIPS_ENTRYLO_XI (_ULCAST_(1) << 30)
#define MIPS_ENTRYLO_RI (_ULCAST_(1) << 31)
#endif
/* CMGCRBase bit definitions */
#define MIPS_CMGCRB_BASE 11
#define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))