Merge tag 'powerpc-4.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux
Pull powerpc updates from Michael Ellerman:
"Highlights:
- PowerNV PCI hotplug support.
- Lots more Power9 support.
- eBPF JIT support on ppc64le.
- Lots of cxl updates.
- Boot code consolidation.
Bug fixes:
- Fix spin_unlock_wait() from Boqun Feng
- Fix stack pointer corruption in __tm_recheckpoint() from Michael
Neuling
- Fix multiple bugs in memory_hotplug_max() from Bharata B Rao
- mm: Ensure "special" zones are empty from Oliver O'Halloran
- ftrace: Separate the heuristics for checking call sites from
Michael Ellerman
- modules: Never restore r2 for a mprofile-kernel style mcount() call
from Michael Ellerman
- Fix endianness when reading TCEs from Alexey Kardashevskiy
- start rtasd before PCI probing from Greg Kurz
- PCI: rpaphp: Fix slot registration for multiple slots under a PHB
from Tyrel Datwyler
- powerpc/mm: Add memory barrier in __hugepte_alloc() from Sukadev
Bhattiprolu
Cleanups & fixes:
- Drop support for MPIC in pseries from Rashmica Gupta
- Define and use PPC64_ELF_ABI_v2/v1 from Michael Ellerman
- Remove unused symbols in asm-offsets.c from Rashmica Gupta
- Fix SRIOV not building without EEH enabled from Russell Currey
- Remove kretprobe_trampoline_holder from Thiago Jung Bauermann
- Reduce log level of PCI I/O space warning from Benjamin
Herrenschmidt
- Add array bounds checking to crash_shutdown_handlers from Suraj
Jitindar Singh
- Avoid -maltivec when using clang integrated assembler from Anton
Blanchard
- Fix array overrun in ppc_rtas() syscall from Andrew Donnellan
- Fix error return value in cmm_mem_going_offline() from Rasmus
Villemoes
- export cpu_to_core_id() from Mauricio Faria de Oliveira
- Remove old symbols from defconfigs from Andrew Donnellan
- Update obsolete comments in setup_32.c about entry conditions from
Benjamin Herrenschmidt
- Add comment explaining the purpose of setup_kdump_trampoline() from
Benjamin Herrenschmidt
- Merge the RELOCATABLE config entries for ppc32 and ppc64 from Kevin
Hao
- Remove RELOCATABLE_PPC32 from Kevin Hao
- Fix .long's in tlb-radix.c to more meaningful from Balbir Singh
Minor cleanups & fixes:
- Andrew Donnellan, Anna-Maria Gleixner, Anton Blanchard, Benjamin
Herrenschmidt, Bharata B Rao, Christophe Leroy, Colin Ian King,
Geliang Tang, Greg Kurz, Madhavan Srinivasan, Michael Ellerman,
Michael Ellerman, Stephen Rothwell, Stewart Smith.
Freescale updates from Scott:
- "Highlights include more 8xx optimizations, device tree updates,
and MVME7100 support."
PowerNV PCI hotplug from Gavin Shan:
- PCI: Add pcibios_setup_bridge()
- Override pcibios_setup_bridge()
- Remove PCI_RESET_DELAY_US
- Move pnv_pci_ioda_setup_opal_tce_kill() around
- Increase PE# capacity
- Allocate PE# in reverse order
- Create PEs in pcibios_setup_bridge()
- Setup PE for root bus
- Extend PCI bridge resources
- Make pnv_ioda_deconfigure_pe() visible
- Dynamically release PE
- Update bridge windows on PCI plug
- Delay populating pdn
- Support PCI slot ID
- Use PCI slot reset infrastructure
- Introduce pnv_pci_get_slot_id()
- Functions to get/set PCI slot state
- PCI/hotplug: PowerPC PowerNV PCI hotplug driver
- Print correct PHB type names
Power9 idle support from Shreyas B. Prabhu:
- set power_save func after the idle states are initialized
- Use PNV_THREAD_WINKLE macro while requesting for winkle
- make hypervisor state restore a function
- Rename idle_power7.S to idle_book3s.S
- Rename reusable idle functions to hardware agnostic names
- Make pnv_powersave_common more generic
- abstraction for saving SPRs before entering deep idle states
- Add platform support for stop instruction
- cpuidle/powernv: Use CPUIDLE_STATE_MAX instead of MAX_POWERNV_IDLE_STATES
- cpuidle/powernv: cleanup cpuidle-powernv.c
- cpuidle/powernv: Add support for POWER ISA v3 idle states
- Use deepest stop state when cpu is offlined
Power9 PMU from Madhavan Srinivasan:
- factor out power8 pmu macros and defines
- factor out power8 pmu functions
- factor out power8 __init_pmu code
- Add power9 event list macros for generic and cache events
- Power9 PMU support
- Export Power9 generic and cache events to sysfs
Power9 preliminary interrupt & PCI support from Benjamin Herrenschmidt:
- Add XICS emulation APIs
- Move a few exception common handlers to make room
- Add support for HV virtualization interrupts
- Add mechanism to force a replay of interrupts
- Add ICP OPAL backend
- Discover IODA3 PHBs
- pci: Remove obsolete SW invalidate
- opal: Add real mode call wrappers
- Rename TCE invalidation calls
- Remove SWINV constants and obsolete TCE code
- Rework accessing the TCE invalidate register
- Fallback to OPAL for TCE invalidations
- Use the device-tree to get available range of M64's
- Check status of a PHB before using it
- pci: Don't try to allocate resources that will be reassigned
Other Power9:
- Send SIGBUS on unaligned copy and paste from Chris Smart
- Large Decrementer support from Oliver O'Halloran
- Load Monitor Register Support from Jack Miller
Performance improvements from Anton Blanchard:
- Avoid load hit store in __giveup_fpu() and __giveup_altivec()
- Avoid load hit store in setup_sigcontext()
- Remove assembly versions of strcpy, strcat, strlen and strcmp
- Align hot loops of some string functions
eBPF JIT from Naveen N. Rao:
- Fix/enhance 32-bit Load Immediate implementation
- Optimize 64-bit Immediate loads
- Introduce rotate immediate instructions
- A few cleanups
- Isolate classic BPF JIT specifics into a separate header
- Implement JIT compiler for extended BPF
Operator Panel driver from Suraj Jitindar Singh:
- devicetree/bindings: Add binding for operator panel on FSP machines
- Add inline function to get rc from an ASYNC_COMP opal_msg
- Add driver for operator panel on FSP machines
Sparse fixes from Daniel Axtens:
- make some things static
- Introduce asm-prototypes.h
- Include headers containing prototypes
- Use #ifdef __BIG_ENDIAN__ #else for REG_BYTE
- kvm: Clarify __user annotations
- Pass endianness to sparse
- Make ppc_md.{halt, restart} __noreturn
MM fixes & cleanups from Aneesh Kumar K.V:
- radix: Update LPCR HR bit as per ISA
- use _raw variant of page table accessors
- Compile out radix related functions if RADIX_MMU is disabled
- Clear top 16 bits of va only on older cpus
- Print formation regarding the the MMU mode
- hash: Update SDR1 size encoding as documented in ISA 3.0
- radix: Update PID switch sequence
- radix: Update machine call back to support new HCALL.
- radix: Add LPID based tlb flush helpers
- radix: Add a kernel command line to disable radix
- Cleanup LPCR defines
Boot code consolidation from Benjamin Herrenschmidt:
- Move epapr_paravirt_early_init() to early_init_devtree()
- cell: Don't use flat device-tree after boot
- ge_imp3a: Don't use the flat device-tree after boot
- mpc85xx_ds: Don't use the flat device-tree after boot
- mpc85xx_rdb: Don't use the flat device-tree after boot
- Don't test for machine type in rtas_initialize()
- Don't test for machine type in smp_setup_cpu_maps()
- dt: Add of_device_compatible_match()
- Factor do_feature_fixup calls
- Move 64-bit feature fixup earlier
- Move 64-bit memory reserves to setup_arch()
- Use a cachable DART
- Move FW feature probing out of pseries probe()
- Put exception configuration in a common place
- Remove early allocation of the SMU command buffer
- Move MMU backend selection out of platform code
- pasemi: Remove IOBMAP allocation from platform probe()
- mm/hash: Don't use machine_is() early during boot
- Don't test for machine type to detect HEA special case
- pmac: Remove spurrious machine type test
- Move hash table ops to a separate structure
- Ensure that ppc_md is empty before probing for machine type
- Move 64-bit probe_machine() to later in the boot process
- Move 32-bit probe() machine to later in the boot process
- Get rid of ppc_md.init_early()
- Move the boot time info banner to a separate function
- Move setting of {i,d}cache_bsize to initialize_cache_info()
- Move the content of setup_system() to setup_arch()
- Move cache info inits to a separate function
- Re-order the call to smp_setup_cpu_maps()
- Re-order setup_panic()
- Make a few boot functions __init
- Merge 32-bit and 64-bit setup_arch()
Other new features:
- tty/hvc: Use IRQF_SHARED for OPAL hvc consoles from Sam Mendoza-Jonas
- tty/hvc: Use opal irqchip interface if available from Sam Mendoza-Jonas
- powerpc: Add module autoloading based on CPU features from Alastair D'Silva
- crypto: vmx - Convert to CPU feature based module autoloading from Alastair D'Silva
- Wake up kopald polling thread before waiting for events from Benjamin Herrenschmidt
- xmon: Dump ISA 2.06 SPRs from Michael Ellerman
- xmon: Dump ISA 2.07 SPRs from Michael Ellerman
- Add a parameter to disable 1TB segs from Oliver O'Halloran
- powerpc/boot: Add OPAL console to epapr wrappers from Oliver O'Halloran
- Assign fixed PHB number based on device-tree properties from Guilherme G. Piccoli
- pseries: Add pseries hotplug workqueue from John Allen
- pseries: Add support for hotplug interrupt source from John Allen
- pseries: Use kernel hotplug queue for PowerVM hotplug events from John Allen
- pseries: Move property cloning into its own routine from Nathan Fontenot
- pseries: Dynamic add entires to associativity lookup array from Nathan Fontenot
- pseries: Auto-online hotplugged memory from Nathan Fontenot
- pseries: Remove call to memblock_add() from Nathan Fontenot
cxl:
- Add set and get private data to context struct from Michael Neuling
- make base more explicitly non-modular from Paul Gortmaker
- Use for_each_compatible_node() macro from Wei Yongjun
- Frederic Barrat
- Abstract the differences between the PSL and XSL
- Make vPHB device node match adapter's
- Philippe Bergheaud
- Add mechanism for delivering AFU driver specific events
- Ignore CAPI adapters misplaced in switched slots
- Refine slice error debug messages
- Andrew Donnellan
- static-ify variables to fix sparse warnings
- PCI/hotplug: pnv_php: export symbols and move struct types needed by cxl
- PCI/hotplug: pnv_php: handle OPAL_PCI_SLOT_OFFLINE power state
- Add cxl_check_and_switch_mode() API to switch bi-modal cards
- remove dead Kconfig options
- fix potential NULL dereference in free_adapter()
- Ian Munsie
- Update process element after allocating interrupts
- Add support for CAPP DMA mode
- Fix allowing bogus AFU descriptors with 0 maximum processes
- Fix allocating a minimum of 2 pages for the SPA
- Fix bug where AFU disable operation had no effect
- Workaround XSL bug that does not clear the RA bit after a reset
- Fix NULL pointer dereference on kernel contexts with no AFU interrupts
- powerpc/powernv: Split cxl code out into a separate file
- Add cxl_slot_is_supported API
- Enable bus mastering for devices using CAPP DMA mode
- Move cxl_afu_get / cxl_afu_put to base
- Allow a default context to be associated with an external pci_dev
- Do not create vPHB if there are no AFU configuration records
- powerpc/powernv: Add support for the cxl kernel api on the real phb
- Add support for using the kernel API with a real PHB
- Add kernel APIs to get & set the max irqs per context
- Add preliminary workaround for CX4 interrupt limitation
- Add support for interrupts on the Mellanox CX4
- Workaround PE=0 hardware limitation in Mellanox CX4
- powerpc/powernv: Fix pci-cxl.c build when CONFIG_MODULES=n
selftests:
- Test unaligned copy and paste from Chris Smart
- Load Monitor Register Tests from Jack Miller
- Cyril Bur
- exec() with suspended transaction
- Use signed long to read perf_event_paranoid
- Fix usage message in context_switch
- Fix generation of vector instructions/types in context_switch
- Michael Ellerman
- Use "Delta" rather than "Error" in normal output
- Import Anton's mmap & futex micro benchmarks
- Add a test for PROT_SAO"
* tag 'powerpc-4.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: (263 commits)
powerpc/mm: Parenthesise IS_ENABLED() in if condition
tty/hvc: Use opal irqchip interface if available
tty/hvc: Use IRQF_SHARED for OPAL hvc consoles
selftests/powerpc: exec() with suspended transaction
powerpc: Improve comment explaining why we modify VRSAVE
powerpc/mm: Drop unused externs for hpte_init_beat[_v3]()
powerpc/mm: Rename hpte_init_lpar() and move the fallback to a header
powerpc/mm: Fix build break when PPC_NATIVE=n
crypto: vmx - Convert to CPU feature based module autoloading
powerpc: Add module autoloading based on CPU features
powerpc/powernv/ioda: Fix endianness when reading TCEs
powerpc/mm: Add memory barrier in __hugepte_alloc()
powerpc/modules: Never restore r2 for a mprofile-kernel style mcount() call
powerpc/ftrace: Separate the heuristics for checking call sites
powerpc: Merge 32-bit and 64-bit setup_arch()
powerpc/64: Make a few boot functions __init
powerpc: Re-order setup_panic()
powerpc: Re-order the call to smp_setup_cpu_maps()
powerpc/32: Move cache info inits to a separate function
powerpc/64: Move the content of setup_system() to setup_arch()
...
This commit is contained in:
Linus Torvalds
@@ -1,67 +0,0 @@
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* Freescale Communications Processor Module
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NOTE: This is an interim binding, and will likely change slightly,
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as more devices are supported. The QE bindings especially are
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incomplete.
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* Root CPM node
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Properties:
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- compatible : "fsl,cpm1", "fsl,cpm2", or "fsl,qe".
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- reg : A 48-byte region beginning with CPCR.
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Example:
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cpm@119c0 {
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#address-cells = <1>;
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#size-cells = <1>;
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#interrupt-cells = <2>;
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compatible = "fsl,mpc8272-cpm", "fsl,cpm2";
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reg = <119c0 30>;
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}
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* Properties common to multiple CPM/QE devices
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- fsl,cpm-command : This value is ORed with the opcode and command flag
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to specify the device on which a CPM command operates.
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- fsl,cpm-brg : Indicates which baud rate generator the device
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is associated with. If absent, an unused BRG
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should be dynamically allocated. If zero, the
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device uses an external clock rather than a BRG.
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- reg : Unless otherwise specified, the first resource represents the
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scc/fcc/ucc registers, and the second represents the device's
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parameter RAM region (if it has one).
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* Multi-User RAM (MURAM)
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The multi-user/dual-ported RAM is expressed as a bus under the CPM node.
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Ranges must be set up subject to the following restrictions:
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- Children's reg nodes must be offsets from the start of all muram, even
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if the user-data area does not begin at zero.
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- If multiple range entries are used, the difference between the parent
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address and the child address must be the same in all, so that a single
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mapping can cover them all while maintaining the ability to determine
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CPM-side offsets with pointer subtraction. It is recommended that
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multiple range entries not be used.
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- A child address of zero must be translatable, even if no reg resources
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contain it.
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A child "data" node must exist, compatible with "fsl,cpm-muram-data", to
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indicate the portion of muram that is usable by the OS for arbitrary
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purposes. The data node may have an arbitrary number of reg resources,
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all of which contribute to the allocatable muram pool.
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Example, based on mpc8272:
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muram@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 10000>;
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data@0 {
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compatible = "fsl,cpm-muram-data";
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reg = <0 2000 9800 800>;
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};
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};
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@@ -1,21 +0,0 @@
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* Baud Rate Generators
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Currently defined compatibles:
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fsl,cpm-brg
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fsl,cpm1-brg
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fsl,cpm2-brg
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Properties:
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- reg : There may be an arbitrary number of reg resources; BRG
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numbers are assigned to these in order.
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- clock-frequency : Specifies the base frequency driving
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the BRG.
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Example:
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brg@119f0 {
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compatible = "fsl,mpc8272-brg",
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"fsl,cpm2-brg",
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"fsl,cpm-brg";
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reg = <119f0 10 115f0 10>;
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clock-frequency = <d#25000000>;
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};
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@@ -1,41 +0,0 @@
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* I2C
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The I2C controller is expressed as a bus under the CPM node.
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Properties:
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- compatible : "fsl,cpm1-i2c", "fsl,cpm2-i2c"
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- reg : On CPM2 devices, the second resource doesn't specify the I2C
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Parameter RAM itself, but the I2C_BASE field of the CPM2 Parameter RAM
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(typically 0x8afc 0x2).
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- #address-cells : Should be one. The cell is the i2c device address with
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the r/w bit set to zero.
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- #size-cells : Should be zero.
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- clock-frequency : Can be used to set the i2c clock frequency. If
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unspecified, a default frequency of 60kHz is being used.
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The following two properties are deprecated. They are only used by legacy
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i2c drivers to find the bus to probe:
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- linux,i2c-index : Can be used to hard code an i2c bus number. By default,
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the bus number is dynamically assigned by the i2c core.
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- linux,i2c-class : Can be used to override the i2c class. The class is used
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by legacy i2c device drivers to find a bus in a specific context like
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system management, video or sound. By default, I2C_CLASS_HWMON (1) is
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being used. The definition of the classes can be found in
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include/i2c/i2c.h
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Example, based on mpc823:
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i2c@860 {
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compatible = "fsl,mpc823-i2c",
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"fsl,cpm1-i2c";
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reg = <0x860 0x20 0x3c80 0x30>;
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interrupts = <16>;
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interrupt-parent = <&CPM_PIC>;
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fsl,cpm-command = <0x10>;
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#address-cells = <1>;
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#size-cells = <0>;
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rtc@68 {
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compatible = "dallas,ds1307";
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reg = <0x68>;
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};
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};
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@@ -1,18 +0,0 @@
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* Interrupt Controllers
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Currently defined compatibles:
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- fsl,cpm1-pic
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- only one interrupt cell
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- fsl,pq1-pic
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- fsl,cpm2-pic
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- second interrupt cell is level/sense:
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- 2 is falling edge
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- 8 is active low
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Example:
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interrupt-controller@10c00 {
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <10c00 80>;
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compatible = "mpc8272-pic", "fsl,cpm2-pic";
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};
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@@ -1,15 +0,0 @@
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* USB (Universal Serial Bus Controller)
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Properties:
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- compatible : "fsl,cpm1-usb", "fsl,cpm2-usb", "fsl,qe-usb"
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Example:
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usb@11bc0 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,cpm2-usb";
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reg = <11b60 18 8b00 100>;
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interrupts = <b 8>;
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interrupt-parent = <&PIC>;
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fsl,cpm-command = <2e600000>;
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};
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@@ -1,38 +0,0 @@
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Every GPIO controller node must have #gpio-cells property defined,
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this information will be used to translate gpio-specifiers.
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On CPM1 devices, all ports are using slightly different register layouts.
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Ports A, C and D are 16bit ports and Ports B and E are 32bit ports.
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On CPM2 devices, all ports are 32bit ports and use a common register layout.
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Required properties:
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- compatible : "fsl,cpm1-pario-bank-a", "fsl,cpm1-pario-bank-b",
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"fsl,cpm1-pario-bank-c", "fsl,cpm1-pario-bank-d",
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"fsl,cpm1-pario-bank-e", "fsl,cpm2-pario-bank"
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- #gpio-cells : Should be two. The first cell is the pin number and the
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second cell is used to specify optional parameters (currently unused).
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- gpio-controller : Marks the port as GPIO controller.
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Example of three SOC GPIO banks defined as gpio-controller nodes:
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CPM1_PIO_A: gpio-controller@950 {
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#gpio-cells = <2>;
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compatible = "fsl,cpm1-pario-bank-a";
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reg = <0x950 0x10>;
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gpio-controller;
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};
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CPM1_PIO_B: gpio-controller@ab8 {
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#gpio-cells = <2>;
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compatible = "fsl,cpm1-pario-bank-b";
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reg = <0xab8 0x10>;
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gpio-controller;
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};
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CPM1_PIO_E: gpio-controller@ac8 {
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#gpio-cells = <2>;
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compatible = "fsl,cpm1-pario-bank-e";
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reg = <0xac8 0x18>;
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gpio-controller;
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};
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@@ -1,43 +0,0 @@
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* Network
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Currently defined compatibles:
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- fsl,cpm1-scc-enet
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- fsl,cpm2-scc-enet
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- fsl,cpm1-fec-enet
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- fsl,cpm2-fcc-enet (third resource is GFEMR)
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- fsl,qe-enet
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Example:
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ethernet@11300 {
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compatible = "fsl,mpc8272-fcc-enet",
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"fsl,cpm2-fcc-enet";
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reg = <11300 20 8400 100 11390 1>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <20 8>;
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interrupt-parent = <&PIC>;
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phy-handle = <&PHY0>;
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fsl,cpm-command = <12000300>;
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};
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* MDIO
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Currently defined compatibles:
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fsl,pq1-fec-mdio (reg is same as first resource of FEC device)
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fsl,cpm2-mdio-bitbang (reg is port C registers)
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|
||||
Properties for fsl,cpm2-mdio-bitbang:
|
||||
fsl,mdio-pin : pin of port C controlling mdio data
|
||||
fsl,mdc-pin : pin of port C controlling mdio clock
|
||||
|
||||
Example:
|
||||
mdio@10d40 {
|
||||
compatible = "fsl,mpc8272ads-mdio-bitbang",
|
||||
"fsl,mpc8272-mdio-bitbang",
|
||||
"fsl,cpm2-mdio-bitbang";
|
||||
reg = <10d40 14>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
fsl,mdio-pin = <12>;
|
||||
fsl,mdc-pin = <13>;
|
||||
};
|
||||
@@ -1,115 +0,0 @@
|
||||
* Freescale QUICC Engine module (QE)
|
||||
This represents qe module that is installed on PowerQUICC II Pro.
|
||||
|
||||
NOTE: This is an interim binding; it should be updated to fit
|
||||
in with the CPM binding later in this document.
|
||||
|
||||
Basically, it is a bus of devices, that could act more or less
|
||||
as a complete entity (UCC, USB etc ). All of them should be siblings on
|
||||
the "root" qe node, using the common properties from there.
|
||||
The description below applies to the qe of MPC8360 and
|
||||
more nodes and properties would be extended in the future.
|
||||
|
||||
i) Root QE device
|
||||
|
||||
Required properties:
|
||||
- compatible : should be "fsl,qe";
|
||||
- model : precise model of the QE, Can be "QE", "CPM", or "CPM2"
|
||||
- reg : offset and length of the device registers.
|
||||
- bus-frequency : the clock frequency for QUICC Engine.
|
||||
- fsl,qe-num-riscs: define how many RISC engines the QE has.
|
||||
- fsl,qe-num-snums: define how many serial number(SNUM) the QE can use for the
|
||||
threads.
|
||||
|
||||
Optional properties:
|
||||
- fsl,firmware-phandle:
|
||||
Usage: required only if there is no fsl,qe-firmware child node
|
||||
Value type: <phandle>
|
||||
Definition: Points to a firmware node (see "QE Firmware Node" below)
|
||||
that contains the firmware that should be uploaded for this QE.
|
||||
The compatible property for the firmware node should say,
|
||||
"fsl,qe-firmware".
|
||||
|
||||
Recommended properties
|
||||
- brg-frequency : the internal clock source frequency for baud-rate
|
||||
generators in Hz.
|
||||
|
||||
Example:
|
||||
qe@e0100000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
#interrupt-cells = <2>;
|
||||
compatible = "fsl,qe";
|
||||
ranges = <0 e0100000 00100000>;
|
||||
reg = <e0100000 480>;
|
||||
brg-frequency = <0>;
|
||||
bus-frequency = <179A7B00>;
|
||||
}
|
||||
|
||||
* Multi-User RAM (MURAM)
|
||||
|
||||
Required properties:
|
||||
- compatible : should be "fsl,qe-muram", "fsl,cpm-muram".
|
||||
- mode : the could be "host" or "slave".
|
||||
- ranges : Should be defined as specified in 1) to describe the
|
||||
translation of MURAM addresses.
|
||||
- data-only : sub-node which defines the address area under MURAM
|
||||
bus that can be allocated as data/parameter
|
||||
|
||||
Example:
|
||||
|
||||
muram@10000 {
|
||||
compatible = "fsl,qe-muram", "fsl,cpm-muram";
|
||||
ranges = <0 00010000 0000c000>;
|
||||
|
||||
data-only@0{
|
||||
compatible = "fsl,qe-muram-data",
|
||||
"fsl,cpm-muram-data";
|
||||
reg = <0 c000>;
|
||||
};
|
||||
};
|
||||
|
||||
* QE Firmware Node
|
||||
|
||||
This node defines a firmware binary that is embedded in the device tree, for
|
||||
the purpose of passing the firmware from bootloader to the kernel, or from
|
||||
the hypervisor to the guest.
|
||||
|
||||
The firmware node itself contains the firmware binary contents, a compatible
|
||||
property, and any firmware-specific properties. The node should be placed
|
||||
inside a QE node that needs it. Doing so eliminates the need for a
|
||||
fsl,firmware-phandle property. Other QE nodes that need the same firmware
|
||||
should define an fsl,firmware-phandle property that points to the firmware node
|
||||
in the first QE node.
|
||||
|
||||
The fsl,firmware property can be specified in the DTS (possibly using incbin)
|
||||
or can be inserted by the boot loader at boot time.
|
||||
|
||||
Required properties:
|
||||
- compatible
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: A standard property. Specify a string that indicates what
|
||||
kind of firmware it is. For QE, this should be "fsl,qe-firmware".
|
||||
|
||||
- fsl,firmware
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>, encoded as an array of bytes
|
||||
Definition: A standard property. This property contains the firmware
|
||||
binary "blob".
|
||||
|
||||
Example:
|
||||
qe1@e0080000 {
|
||||
compatible = "fsl,qe";
|
||||
qe_firmware:qe-firmware {
|
||||
compatible = "fsl,qe-firmware";
|
||||
fsl,firmware = [0x70 0xcd 0x00 0x00 0x01 0x46 0x45 ...];
|
||||
};
|
||||
...
|
||||
};
|
||||
|
||||
qe2@e0090000 {
|
||||
compatible = "fsl,qe";
|
||||
fsl,firmware-phandle = <&qe_firmware>;
|
||||
...
|
||||
};
|
||||
@@ -1,24 +0,0 @@
|
||||
* Uploaded QE firmware
|
||||
|
||||
If a new firmware has been uploaded to the QE (usually by the
|
||||
boot loader), then a 'firmware' child node should be added to the QE
|
||||
node. This node provides information on the uploaded firmware that
|
||||
device drivers may need.
|
||||
|
||||
Required properties:
|
||||
- id: The string name of the firmware. This is taken from the 'id'
|
||||
member of the qe_firmware structure of the uploaded firmware.
|
||||
Device drivers can search this string to determine if the
|
||||
firmware they want is already present.
|
||||
- extended-modes: The Extended Modes bitfield, taken from the
|
||||
firmware binary. It is a 64-bit number represented
|
||||
as an array of two 32-bit numbers.
|
||||
- virtual-traps: The virtual traps, taken from the firmware binary.
|
||||
It is an array of 8 32-bit numbers.
|
||||
|
||||
Example:
|
||||
firmware {
|
||||
id = "Soft-UART";
|
||||
extended-modes = <0 0>;
|
||||
virtual-traps = <0 0 0 0 0 0 0 0>;
|
||||
};
|
||||
@@ -1,51 +0,0 @@
|
||||
* Parallel I/O Ports
|
||||
|
||||
This node configures Parallel I/O ports for CPUs with QE support.
|
||||
The node should reside in the "soc" node of the tree. For each
|
||||
device that using parallel I/O ports, a child node should be created.
|
||||
See the definition of the Pin configuration nodes below for more
|
||||
information.
|
||||
|
||||
Required properties:
|
||||
- device_type : should be "par_io".
|
||||
- reg : offset to the register set and its length.
|
||||
- num-ports : number of Parallel I/O ports
|
||||
|
||||
Example:
|
||||
par_io@1400 {
|
||||
reg = <1400 100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
device_type = "par_io";
|
||||
num-ports = <7>;
|
||||
ucc_pin@01 {
|
||||
......
|
||||
};
|
||||
|
||||
Note that "par_io" nodes are obsolete, and should not be used for
|
||||
the new device trees. Instead, each Par I/O bank should be represented
|
||||
via its own gpio-controller node:
|
||||
|
||||
Required properties:
|
||||
- #gpio-cells : should be "2".
|
||||
- compatible : should be "fsl,<chip>-qe-pario-bank",
|
||||
"fsl,mpc8323-qe-pario-bank".
|
||||
- reg : offset to the register set and its length.
|
||||
- gpio-controller : node to identify gpio controllers.
|
||||
|
||||
Example:
|
||||
qe_pio_a: gpio-controller@1400 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "fsl,mpc8360-qe-pario-bank",
|
||||
"fsl,mpc8323-qe-pario-bank";
|
||||
reg = <0x1400 0x18>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
qe_pio_e: gpio-controller@1460 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "fsl,mpc8360-qe-pario-bank",
|
||||
"fsl,mpc8323-qe-pario-bank";
|
||||
reg = <0x1460 0x18>;
|
||||
gpio-controller;
|
||||
};
|
||||
@@ -1,57 +0,0 @@
|
||||
* Pin configuration nodes
|
||||
|
||||
Required properties:
|
||||
- pio-map : array of pin configurations. Each pin is defined by 6
|
||||
integers. The six numbers are respectively: port, pin, dir,
|
||||
open_drain, assignment, has_irq.
|
||||
- port : port number of the pin; 0-6 represent port A-G in UM.
|
||||
- pin : pin number in the port.
|
||||
- dir : direction of the pin, should encode as follows:
|
||||
|
||||
0 = The pin is disabled
|
||||
1 = The pin is an output
|
||||
2 = The pin is an input
|
||||
3 = The pin is I/O
|
||||
|
||||
- open_drain : indicates the pin is normal or wired-OR:
|
||||
|
||||
0 = The pin is actively driven as an output
|
||||
1 = The pin is an open-drain driver. As an output, the pin is
|
||||
driven active-low, otherwise it is three-stated.
|
||||
|
||||
- assignment : function number of the pin according to the Pin Assignment
|
||||
tables in User Manual. Each pin can have up to 4 possible functions in
|
||||
QE and two options for CPM.
|
||||
- has_irq : indicates if the pin is used as source of external
|
||||
interrupts.
|
||||
|
||||
Example:
|
||||
ucc_pin@01 {
|
||||
pio-map = <
|
||||
/* port pin dir open_drain assignment has_irq */
|
||||
0 3 1 0 1 0 /* TxD0 */
|
||||
0 4 1 0 1 0 /* TxD1 */
|
||||
0 5 1 0 1 0 /* TxD2 */
|
||||
0 6 1 0 1 0 /* TxD3 */
|
||||
1 6 1 0 3 0 /* TxD4 */
|
||||
1 7 1 0 1 0 /* TxD5 */
|
||||
1 9 1 0 2 0 /* TxD6 */
|
||||
1 a 1 0 2 0 /* TxD7 */
|
||||
0 9 2 0 1 0 /* RxD0 */
|
||||
0 a 2 0 1 0 /* RxD1 */
|
||||
0 b 2 0 1 0 /* RxD2 */
|
||||
0 c 2 0 1 0 /* RxD3 */
|
||||
0 d 2 0 1 0 /* RxD4 */
|
||||
1 1 2 0 2 0 /* RxD5 */
|
||||
1 0 2 0 2 0 /* RxD6 */
|
||||
1 4 2 0 2 0 /* RxD7 */
|
||||
0 7 1 0 1 0 /* TX_EN */
|
||||
0 8 1 0 1 0 /* TX_ER */
|
||||
0 f 2 0 1 0 /* RX_DV */
|
||||
0 10 2 0 1 0 /* RX_ER */
|
||||
0 0 2 0 1 0 /* RX_CLK */
|
||||
2 9 1 0 3 0 /* GTX_CLK - CLK10 */
|
||||
2 8 2 0 1 0>; /* GTX125 - CLK9 */
|
||||
};
|
||||
|
||||
|
||||
@@ -1,70 +0,0 @@
|
||||
* UCC (Unified Communications Controllers)
|
||||
|
||||
Required properties:
|
||||
- device_type : should be "network", "hldc", "uart", "transparent"
|
||||
"bisync", "atm", or "serial".
|
||||
- compatible : could be "ucc_geth" or "fsl_atm" and so on.
|
||||
- cell-index : the ucc number(1-8), corresponding to UCCx in UM.
|
||||
- reg : Offset and length of the register set for the device
|
||||
- interrupts : <a b> where a is the interrupt number and b is a
|
||||
field that represents an encoding of the sense and level
|
||||
information for the interrupt. This should be encoded based on
|
||||
the information in section 2) depending on the type of interrupt
|
||||
controller you have.
|
||||
- interrupt-parent : the phandle for the interrupt controller that
|
||||
services interrupts for this device.
|
||||
- pio-handle : The phandle for the Parallel I/O port configuration.
|
||||
- port-number : for UART drivers, the port number to use, between 0 and 3.
|
||||
This usually corresponds to the /dev/ttyQE device, e.g. <0> = /dev/ttyQE0.
|
||||
The port number is added to the minor number of the device. Unlike the
|
||||
CPM UART driver, the port-number is required for the QE UART driver.
|
||||
- soft-uart : for UART drivers, if specified this means the QE UART device
|
||||
driver should use "Soft-UART" mode, which is needed on some SOCs that have
|
||||
broken UART hardware. Soft-UART is provided via a microcode upload.
|
||||
- rx-clock-name: the UCC receive clock source
|
||||
"none": clock source is disabled
|
||||
"brg1" through "brg16": clock source is BRG1-BRG16, respectively
|
||||
"clk1" through "clk24": clock source is CLK1-CLK24, respectively
|
||||
- tx-clock-name: the UCC transmit clock source
|
||||
"none": clock source is disabled
|
||||
"brg1" through "brg16": clock source is BRG1-BRG16, respectively
|
||||
"clk1" through "clk24": clock source is CLK1-CLK24, respectively
|
||||
The following two properties are deprecated. rx-clock has been replaced
|
||||
with rx-clock-name, and tx-clock has been replaced with tx-clock-name.
|
||||
Drivers that currently use the deprecated properties should continue to
|
||||
do so, in order to support older device trees, but they should be updated
|
||||
to check for the new properties first.
|
||||
- rx-clock : represents the UCC receive clock source.
|
||||
0x00 : clock source is disabled;
|
||||
0x1~0x10 : clock source is BRG1~BRG16 respectively;
|
||||
0x11~0x28: clock source is QE_CLK1~QE_CLK24 respectively.
|
||||
- tx-clock: represents the UCC transmit clock source;
|
||||
0x00 : clock source is disabled;
|
||||
0x1~0x10 : clock source is BRG1~BRG16 respectively;
|
||||
0x11~0x28: clock source is QE_CLK1~QE_CLK24 respectively.
|
||||
|
||||
Required properties for network device_type:
|
||||
- mac-address : list of bytes representing the ethernet address.
|
||||
- phy-handle : The phandle for the PHY connected to this controller.
|
||||
|
||||
Recommended properties:
|
||||
- phy-connection-type : a string naming the controller/PHY interface type,
|
||||
i.e., "mii" (default), "rmii", "gmii", "rgmii", "rgmii-id" (Internal
|
||||
Delay), "rgmii-txid" (delay on TX only), "rgmii-rxid" (delay on RX only),
|
||||
"tbi", or "rtbi".
|
||||
|
||||
Example:
|
||||
ucc@2000 {
|
||||
device_type = "network";
|
||||
compatible = "ucc_geth";
|
||||
cell-index = <1>;
|
||||
reg = <2000 200>;
|
||||
interrupts = <a0 0>;
|
||||
interrupt-parent = <700>;
|
||||
mac-address = [ 00 04 9f 00 23 23 ];
|
||||
rx-clock = "none";
|
||||
tx-clock = "clk9";
|
||||
phy-handle = <212000>;
|
||||
phy-connection-type = "gmii";
|
||||
pio-handle = <140001>;
|
||||
};
|
||||
@@ -1,37 +0,0 @@
|
||||
Freescale QUICC Engine USB Controller
|
||||
|
||||
Required properties:
|
||||
- compatible : should be "fsl,<chip>-qe-usb", "fsl,mpc8323-qe-usb".
|
||||
- reg : the first two cells should contain usb registers location and
|
||||
length, the next two two cells should contain PRAM location and
|
||||
length.
|
||||
- interrupts : should contain USB interrupt.
|
||||
- interrupt-parent : interrupt source phandle.
|
||||
- fsl,fullspeed-clock : specifies the full speed USB clock source:
|
||||
"none": clock source is disabled
|
||||
"brg1" through "brg16": clock source is BRG1-BRG16, respectively
|
||||
"clk1" through "clk24": clock source is CLK1-CLK24, respectively
|
||||
- fsl,lowspeed-clock : specifies the low speed USB clock source:
|
||||
"none": clock source is disabled
|
||||
"brg1" through "brg16": clock source is BRG1-BRG16, respectively
|
||||
"clk1" through "clk24": clock source is CLK1-CLK24, respectively
|
||||
- hub-power-budget : USB power budget for the root hub, in mA.
|
||||
- gpios : should specify GPIOs in this order: USBOE, USBTP, USBTN, USBRP,
|
||||
USBRN, SPEED (optional), and POWER (optional).
|
||||
|
||||
Example:
|
||||
|
||||
usb@6c0 {
|
||||
compatible = "fsl,mpc8360-qe-usb", "fsl,mpc8323-qe-usb";
|
||||
reg = <0x6c0 0x40 0x8b00 0x100>;
|
||||
interrupts = <11>;
|
||||
interrupt-parent = <&qeic>;
|
||||
fsl,fullspeed-clock = "clk21";
|
||||
gpios = <&qe_pio_b 2 0 /* USBOE */
|
||||
&qe_pio_b 3 0 /* USBTP */
|
||||
&qe_pio_b 8 0 /* USBTN */
|
||||
&qe_pio_b 9 0 /* USBRP */
|
||||
&qe_pio_b 11 0 /* USBRN */
|
||||
&qe_pio_e 20 0 /* SPEED */
|
||||
&qe_pio_e 21 0 /* POWER */>;
|
||||
};
|
||||
@@ -1,32 +0,0 @@
|
||||
* Serial
|
||||
|
||||
Currently defined compatibles:
|
||||
- fsl,cpm1-smc-uart
|
||||
- fsl,cpm2-smc-uart
|
||||
- fsl,cpm1-scc-uart
|
||||
- fsl,cpm2-scc-uart
|
||||
- fsl,qe-uart
|
||||
|
||||
Modem control lines connected to GPIO controllers are listed in the gpios
|
||||
property as described in booting-without-of.txt, section IX.1 in the following
|
||||
order:
|
||||
|
||||
CTS, RTS, DCD, DSR, DTR, and RI.
|
||||
|
||||
The gpios property is optional and can be left out when control lines are
|
||||
not used.
|
||||
|
||||
Example:
|
||||
|
||||
serial@11a00 {
|
||||
device_type = "serial";
|
||||
compatible = "fsl,mpc8272-scc-uart",
|
||||
"fsl,cpm2-scc-uart";
|
||||
reg = <11a00 20 8000 100>;
|
||||
interrupts = <28 8>;
|
||||
interrupt-parent = <&PIC>;
|
||||
fsl,cpm-brg = <1>;
|
||||
fsl,cpm-command = <00800000>;
|
||||
gpios = <&gpio_c 15 0
|
||||
&gpio_d 29 0>;
|
||||
};
|
||||
@@ -0,0 +1,14 @@
|
||||
IBM OPAL Operator Panel Binding
|
||||
-------------------------------
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "ibm,opal-oppanel".
|
||||
- #lines : Number of lines on the operator panel e.g. <0x2>.
|
||||
- #length : Number of characters per line of the operator panel e.g. <0x10>.
|
||||
|
||||
Example:
|
||||
oppanel {
|
||||
compatible = "ibm,opal-oppanel";
|
||||
#lines = <0x2>;
|
||||
#length = <0x10>;
|
||||
};
|
||||
Reference in New Issue
Block a user