Merge tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC-specific updates from Arnd Bergmann: "This is a larger set of new functionality for the existing SoC families, including: - vt8500 gains support for new CPU cores, notably the Cortex-A9 based wm8850 - prima2 gains support for the "marco" SoC family, its SMP based cousin - tegra gains support for the new Tegra4 (Tegra114) family - socfpga now supports a newer version of the hardware including SMP - i.mx31 and bcm2835 are now using DT probing for their clocks - lots of updates for sh-mobile - OMAP updates for clocks, power management and USB - i.mx6q and tegra now support cpuidle - kirkwood now supports PCIe hot plugging - tegra clock support is updated - tegra USB PHY probing gets implemented diffently" * tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (148 commits) ARM: prima2: remove duplicate v7_invalidate_l1 ARM: shmobile: r8a7779: Correct TMU clock support again ARM: prima2: fix __init section for cpu hotplug ARM: OMAP: Consolidate OMAP USB-HS platform data (part 3/3) ARM: OMAP: Consolidate OMAP USB-HS platform data (part 1/3) arm: socfpga: Add SMP support for actual socfpga harware arm: Add v7_invalidate_l1 to cache-v7.S arm: socfpga: Add entries to enable make dtbs socfpga arm: socfpga: Add new device tree source for actual socfpga HW ARM: tegra: sort Kconfig selects for Tegra114 ARM: tegra: enable ARCH_REQUIRE_GPIOLIB for Tegra114 ARM: tegra: Fix build error w/ ARCH_TEGRA_114_SOC w/o ARCH_TEGRA_3x_SOC ARM: tegra: Fix build error for gic update ARM: tegra: remove empty tegra_smp_init_cpus() ARM: shmobile: Register ARM architected timer ARM: MARCO: fix the build issue due to gic-vic-to-irqchip move ARM: shmobile: r8a7779: Correct TMU clock support ARM: mxs_defconfig: Select CONFIG_DEVTMPFS_MOUNT ARM: mxs: decrease mxs_clockevent_device.min_delta_ns to 2 clock cycles ARM: mxs: use apbx bus clock to drive the timers on timrotv2 ...
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@@ -26,11 +26,13 @@
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#include <mach/bcm2835_soc.h>
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#define PM_RSTC 0x1c
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#define PM_RSTS 0x20
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#define PM_WDOG 0x24
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#define PM_PASSWORD 0x5a000000
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#define PM_RSTC_WRCFG_MASK 0x00000030
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#define PM_RSTC_WRCFG_FULL_RESET 0x00000020
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#define PM_RSTS_HADWRH_SET 0x00000040
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static void __iomem *wdt_regs;
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@@ -67,6 +69,29 @@ static void bcm2835_restart(char mode, const char *cmd)
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mdelay(1);
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}
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/*
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* We can't really power off, but if we do the normal reset scheme, and
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* indicate to bootcode.bin not to reboot, then most of the chip will be
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* powered off.
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*/
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static void bcm2835_power_off(void)
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{
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u32 val;
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/*
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* We set the watchdog hard reset bit here to distinguish this reset
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* from the normal (full) reset. bootcode.bin will not reboot after a
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* hard reset.
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*/
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val = readl_relaxed(wdt_regs + PM_RSTS);
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val &= ~PM_RSTC_WRCFG_MASK;
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val |= PM_PASSWORD | PM_RSTS_HADWRH_SET;
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writel_relaxed(val, wdt_regs + PM_RSTS);
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/* Continue with normal reset mechanism */
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bcm2835_restart(0, "");
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}
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static struct map_desc io_map __initdata = {
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.virtual = BCM2835_PERIPH_VIRT,
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.pfn = __phys_to_pfn(BCM2835_PERIPH_PHYS),
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@@ -84,6 +109,9 @@ static void __init bcm2835_init(void)
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int ret;
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bcm2835_setup_restart();
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if (wdt_regs)
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pm_power_off = bcm2835_power_off;
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bcm2835_init_clocks();
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ret = of_platform_populate(NULL, of_default_bus_match_table, NULL,
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