[POWERPC] Use the genirq framework
This adapts the generic powerpc interrupt handling code, and all of the platforms except for the embedded 6xx machines, to use the new genirq framework. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Benjamin Herrenschmidt
zatwierdzone przez
Paul Mackerras
Paul Mackerras
rodzic
5a43a066b1
commit
b9e5b4e6a9
@@ -70,18 +70,19 @@ static struct interrupt_info gatwick_int_pool[GATWICK_IRQ_POOL_SIZE];
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#define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
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static unsigned long ppc_lost_interrupts[NR_MASK_WORDS];
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static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
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static int pmac_irq_cascade = -1;
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/*
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* Mark an irq as "lost". This is only used on the pmac
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* since it can lose interrupts (see pmac_set_irq_mask).
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* -- Cort
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*/
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void __set_lost(unsigned long irq_nr, int nokick)
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static void __pmac_retrigger(unsigned int irq_nr)
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{
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if (!test_and_set_bit(irq_nr, ppc_lost_interrupts)) {
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if (irq_nr >= max_real_irqs && pmac_irq_cascade > 0) {
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__set_bit(irq_nr, ppc_lost_interrupts);
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irq_nr = pmac_irq_cascade;
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mb();
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}
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if (!__test_and_set_bit(irq_nr, ppc_lost_interrupts)) {
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atomic_inc(&ppc_n_lost_interrupts);
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if (!nokick)
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set_dec(1);
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set_dec(1);
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}
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}
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@@ -94,10 +95,10 @@ static void pmac_mask_and_ack_irq(unsigned int irq_nr)
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if ((unsigned)irq_nr >= max_irqs)
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return;
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clear_bit(irq_nr, ppc_cached_irq_mask);
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if (test_and_clear_bit(irq_nr, ppc_lost_interrupts))
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atomic_dec(&ppc_n_lost_interrupts);
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spin_lock_irqsave(&pmac_pic_lock, flags);
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__clear_bit(irq_nr, ppc_cached_irq_mask);
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if (__test_and_clear_bit(irq_nr, ppc_lost_interrupts))
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atomic_dec(&ppc_n_lost_interrupts);
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out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
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out_le32(&pmac_irq_hw[i]->ack, bit);
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do {
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@@ -109,7 +110,7 @@ static void pmac_mask_and_ack_irq(unsigned int irq_nr)
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spin_unlock_irqrestore(&pmac_pic_lock, flags);
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}
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static void pmac_set_irq_mask(unsigned int irq_nr, int nokicklost)
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static void pmac_ack_irq(unsigned int irq_nr)
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{
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unsigned long bit = 1UL << (irq_nr & 0x1f);
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int i = irq_nr >> 5;
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@@ -118,7 +119,22 @@ static void pmac_set_irq_mask(unsigned int irq_nr, int nokicklost)
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if ((unsigned)irq_nr >= max_irqs)
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return;
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spin_lock_irqsave(&pmac_pic_lock, flags);
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spin_lock_irqsave(&pmac_pic_lock, flags);
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if (__test_and_clear_bit(irq_nr, ppc_lost_interrupts))
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atomic_dec(&ppc_n_lost_interrupts);
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out_le32(&pmac_irq_hw[i]->ack, bit);
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(void)in_le32(&pmac_irq_hw[i]->ack);
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spin_unlock_irqrestore(&pmac_pic_lock, flags);
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}
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static void __pmac_set_irq_mask(unsigned int irq_nr, int nokicklost)
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{
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unsigned long bit = 1UL << (irq_nr & 0x1f);
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int i = irq_nr >> 5;
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if ((unsigned)irq_nr >= max_irqs)
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return;
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/* enable unmasked interrupts */
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out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
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@@ -135,8 +151,7 @@ static void pmac_set_irq_mask(unsigned int irq_nr, int nokicklost)
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* the bit in the flag register or request another interrupt.
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*/
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if (bit & ppc_cached_irq_mask[i] & in_le32(&pmac_irq_hw[i]->level))
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__set_lost((ulong)irq_nr, nokicklost);
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spin_unlock_irqrestore(&pmac_pic_lock, flags);
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__pmac_retrigger(irq_nr);
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}
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/* When an irq gets requested for the first client, if it's an
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@@ -144,62 +159,67 @@ static void pmac_set_irq_mask(unsigned int irq_nr, int nokicklost)
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*/
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static unsigned int pmac_startup_irq(unsigned int irq_nr)
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{
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unsigned long flags;
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unsigned long bit = 1UL << (irq_nr & 0x1f);
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int i = irq_nr >> 5;
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spin_lock_irqsave(&pmac_pic_lock, flags);
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if ((irq_desc[irq_nr].status & IRQ_LEVEL) == 0)
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out_le32(&pmac_irq_hw[i]->ack, bit);
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set_bit(irq_nr, ppc_cached_irq_mask);
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pmac_set_irq_mask(irq_nr, 0);
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__set_bit(irq_nr, ppc_cached_irq_mask);
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__pmac_set_irq_mask(irq_nr, 0);
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spin_unlock_irqrestore(&pmac_pic_lock, flags);
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return 0;
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}
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static void pmac_mask_irq(unsigned int irq_nr)
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{
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clear_bit(irq_nr, ppc_cached_irq_mask);
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pmac_set_irq_mask(irq_nr, 0);
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mb();
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unsigned long flags;
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spin_lock_irqsave(&pmac_pic_lock, flags);
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__clear_bit(irq_nr, ppc_cached_irq_mask);
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__pmac_set_irq_mask(irq_nr, 0);
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spin_unlock_irqrestore(&pmac_pic_lock, flags);
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}
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static void pmac_unmask_irq(unsigned int irq_nr)
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{
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set_bit(irq_nr, ppc_cached_irq_mask);
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pmac_set_irq_mask(irq_nr, 0);
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unsigned long flags;
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spin_lock_irqsave(&pmac_pic_lock, flags);
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__set_bit(irq_nr, ppc_cached_irq_mask);
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__pmac_set_irq_mask(irq_nr, 0);
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spin_unlock_irqrestore(&pmac_pic_lock, flags);
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}
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static void pmac_end_irq(unsigned int irq_nr)
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static int pmac_retrigger(unsigned int irq_nr)
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{
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if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))
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&& irq_desc[irq_nr].action) {
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set_bit(irq_nr, ppc_cached_irq_mask);
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pmac_set_irq_mask(irq_nr, 1);
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}
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unsigned long flags;
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spin_lock_irqsave(&pmac_pic_lock, flags);
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__pmac_retrigger(irq_nr);
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spin_unlock_irqrestore(&pmac_pic_lock, flags);
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return 1;
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}
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struct hw_interrupt_type pmac_pic = {
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static struct irq_chip pmac_pic = {
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.typename = " PMAC-PIC ",
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.startup = pmac_startup_irq,
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.enable = pmac_unmask_irq,
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.disable = pmac_mask_irq,
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.ack = pmac_mask_and_ack_irq,
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.end = pmac_end_irq,
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};
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struct hw_interrupt_type gatwick_pic = {
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.typename = " GATWICK ",
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.startup = pmac_startup_irq,
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.enable = pmac_unmask_irq,
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.disable = pmac_mask_irq,
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.ack = pmac_mask_and_ack_irq,
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.end = pmac_end_irq,
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.mask = pmac_mask_irq,
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.ack = pmac_ack_irq,
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.mask_ack = pmac_mask_and_ack_irq,
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.unmask = pmac_unmask_irq,
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.retrigger = pmac_retrigger,
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};
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static irqreturn_t gatwick_action(int cpl, void *dev_id, struct pt_regs *regs)
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{
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unsigned long flags;
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int irq, bits;
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int rc = IRQ_NONE;
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spin_lock_irqsave(&pmac_pic_lock, flags);
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for (irq = max_irqs; (irq -= 32) >= max_real_irqs; ) {
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int i = irq >> 5;
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bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
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@@ -209,17 +229,20 @@ static irqreturn_t gatwick_action(int cpl, void *dev_id, struct pt_regs *regs)
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if (bits == 0)
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continue;
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irq += __ilog2(bits);
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spin_unlock_irqrestore(&pmac_pic_lock, flags);
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__do_IRQ(irq, regs);
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return IRQ_HANDLED;
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spin_lock_irqsave(&pmac_pic_lock, flags);
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rc = IRQ_HANDLED;
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}
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printk("gatwick irq not from gatwick pic\n");
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return IRQ_NONE;
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spin_unlock_irqrestore(&pmac_pic_lock, flags);
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return rc;
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}
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static int pmac_get_irq(struct pt_regs *regs)
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{
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int irq;
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unsigned long bits = 0;
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unsigned long flags;
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#ifdef CONFIG_SMP
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void psurge_smp_message_recv(struct pt_regs *);
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@@ -230,6 +253,7 @@ static int pmac_get_irq(struct pt_regs *regs)
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return -2; /* ignore, already handled */
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}
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#endif /* CONFIG_SMP */
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spin_lock_irqsave(&pmac_pic_lock, flags);
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for (irq = max_real_irqs; (irq -= 32) >= 0; ) {
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int i = irq >> 5;
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bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
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@@ -241,6 +265,7 @@ static int pmac_get_irq(struct pt_regs *regs)
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irq += __ilog2(bits);
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break;
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}
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spin_unlock_irqrestore(&pmac_pic_lock, flags);
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return irq;
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}
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@@ -389,7 +414,6 @@ static struct irqaction gatwick_cascade_action = {
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static void __init pmac_pic_probe_oldstyle(void)
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{
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int i;
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int irq_cascade = -1;
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struct device_node *master = NULL;
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struct device_node *slave = NULL;
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u8 __iomem *addr;
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@@ -443,9 +467,16 @@ static void __init pmac_pic_probe_oldstyle(void)
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}
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BUG_ON(master == NULL);
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/* Set the handler for the main PIC */
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for ( i = 0; i < max_real_irqs ; i++ )
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irq_desc[i].chip = &pmac_pic;
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/* Mark level interrupts and set handlers */
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for (i = 0; i < max_irqs; i++) {
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int level = !!(level_mask[i >> 5] & (1UL << (i & 0x1f)));
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if (level)
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irq_desc[i].status |= IRQ_LEVEL;
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else
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irq_desc[i].status |= IRQ_DELAYED_DISABLE;
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set_irq_chip_and_handler(i, &pmac_pic, level ?
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handle_level_irq : handle_edge_irq);
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}
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/* Get addresses of first controller if we have a node for it */
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BUG_ON(of_address_to_resource(master, 0, &r));
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@@ -472,29 +503,22 @@ static void __init pmac_pic_probe_oldstyle(void)
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pmac_irq_hw[i++] =
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(volatile struct pmac_irq_hw __iomem *)
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(addr + 0x10);
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irq_cascade = slave->intrs[0].line;
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pmac_irq_cascade = slave->intrs[0].line;
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printk(KERN_INFO "irq: Found slave Apple PIC %s for %d irqs"
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" cascade: %d\n", slave->full_name,
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max_irqs - max_real_irqs, irq_cascade);
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max_irqs - max_real_irqs, pmac_irq_cascade);
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}
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of_node_put(slave);
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/* disable all interrupts in all controllers */
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/* Disable all interrupts in all controllers */
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for (i = 0; i * 32 < max_irqs; ++i)
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out_le32(&pmac_irq_hw[i]->enable, 0);
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/* mark level interrupts */
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for (i = 0; i < max_irqs; i++)
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if (level_mask[i >> 5] & (1UL << (i & 0x1f)))
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irq_desc[i].status = IRQ_LEVEL;
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/* Hookup cascade irq */
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if (slave)
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setup_irq(pmac_irq_cascade, &gatwick_cascade_action);
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/* Setup handlers for secondary controller and hook cascade irq*/
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if (slave) {
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for ( i = max_real_irqs ; i < max_irqs ; i++ )
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irq_desc[i].chip = &gatwick_pic;
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setup_irq(irq_cascade, &gatwick_cascade_action);
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}
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printk(KERN_INFO "irq: System has %d possible interrupts\n", max_irqs);
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#ifdef CONFIG_XMON
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setup_irq(20, &xmon_action);
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@@ -502,9 +526,20 @@ static void __init pmac_pic_probe_oldstyle(void)
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}
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#endif /* CONFIG_PPC32 */
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static int pmac_u3_cascade(struct pt_regs *regs, void *data)
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static void pmac_u3_cascade(unsigned int irq, struct irq_desc *desc,
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struct pt_regs *regs)
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{
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return mpic_get_one_irq((struct mpic *)data, regs);
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struct mpic *mpic = desc->handler_data;
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unsigned int max = 100;
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while(max--) {
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int cascade_irq = mpic_get_one_irq(mpic, regs);
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if (max == 99)
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desc->chip->eoi(irq);
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if (irq < 0)
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break;
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generic_handle_irq(cascade_irq, regs);
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};
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}
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static void __init pmac_pic_setup_mpic_nmi(struct mpic *mpic)
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@@ -612,7 +647,8 @@ static int __init pmac_pic_probe_mpic(void)
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of_node_put(slave);
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return 0;
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}
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mpic_setup_cascade(slave->intrs[0].line, pmac_u3_cascade, mpic2);
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set_irq_data(slave->intrs[0].line, mpic2);
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set_irq_chained_handler(slave->intrs[0].line, pmac_u3_cascade);
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of_node_put(slave);
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return 0;
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