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clk: renesas: rcar-gen3: Add support for RCKSEL clock selection

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Add a clock type and macro for defining clocks where the parent and
divider are selected based on the value of the RCKCR.CKSEL bit.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Geert Uytterhoeven
2018-07-11 13:54:30 +02:00
parent 0d2602d750
commit b9d0b84b3d
2 changed files with 26 additions and 4 deletions
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23
drivers/clk/renesas/rcar-gen3-cpg.c
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@@ -1,7 +1,7 @@
/*
* R-Car Gen3 Clock Pulse Generator
*
* Copyright (C) 2015-2016 Glider bvba
* Copyright (C) 2015-2018 Glider bvba
*
* Based on clk-rcar-gen3.c
*
@@ -31,6 +31,8 @@
#define CPG_PLL2CR 0x002c
#define CPG_PLL4CR 0x01f4
#define CPG_RCKCR_CKSEL BIT(15) /* RCLK Clock Source Select */
struct cpg_simple_notifier {
struct notifier_block nb;
void __iomem *reg;
@@ -444,7 +446,7 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
unsigned int div = 1;
u32 value;
parent = clks[core->parent & 0xffff]; /* CLK_TYPE_PE uses high bits */
parent = clks[core->parent & 0xffff]; /* some types use high bits */
if (IS_ERR(parent))
return ERR_CAST(parent);
@@ -524,7 +526,7 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
if (clk_get_rate(clks[cpg_clk_extalr])) {
parent = clks[cpg_clk_extalr];
value |= BIT(15);
value |= CPG_RCKCR_CKSEL;
}
writel(value, csn->reg);
@@ -570,6 +572,21 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
div = cpg_pll_config->osc_prediv * core->div;
break;
case CLK_TYPE_GEN3_RCKSEL:
/*
* Clock selectable between two parents and two fixed dividers
* using RCKCR.CKSEL
*/
if (readl(base + CPG_RCKCR) & CPG_RCKCR_CKSEL) {
div = core->div & 0xffff;
} else {
parent = clks[core->parent >> 16];
if (IS_ERR(parent))
return ERR_CAST(parent);
div = core->div >> 16;
}
break;
default:
return ERR_PTR(-EINVAL);
}