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Docs: dt: document ARM SMMUv3 generic binding usage

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We're about to ratify our use of the generic binding, so document it.

CC: Rob Herring <robh+dt@kernel.org>
CC: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
This commit is contained in:
Robin Murphy
2016-09-12 17:13:43 +01:00
committed by Will Deacon
parent 57f98d2f61
commit b9bc881180
1 changed files with 7 additions and 1 deletions
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8
Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt
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@@ -27,6 +27,12 @@ the PCIe specification.
* "cmdq-sync" - CMD_SYNC complete * "cmdq-sync" - CMD_SYNC complete
* "gerror" - Global Error activated * "gerror" - Global Error activated
- #iommu-cells : See the generic IOMMU binding described in
devicetree/bindings/pci/pci-iommu.txt
for details. For SMMUv3, must be 1, with each cell
describing a single stream ID. All possible stream
IDs which a device may emit must be described.
** SMMUv3 optional properties: ** SMMUv3 optional properties:
- dma-coherent : Present if DMA operations made by the SMMU (page - dma-coherent : Present if DMA operations made by the SMMU (page
@@ -54,6 +60,6 @@ the PCIe specification.
<GIC_SPI 79 IRQ_TYPE_EDGE_RISING>; <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "eventq", "priq", "cmdq-sync", "gerror"; interrupt-names = "eventq", "priq", "cmdq-sync", "gerror";
dma-coherent; dma-coherent;
#iommu-cells = <0>; #iommu-cells = <1>;
msi-parent = <&its 0xff0000>; msi-parent = <&its 0xff0000>;
}; };