Merge branch 'for-linus' into next
Conflicts: drivers/dma/edma.c Moved the memory leak fix post merge Signed-off-by: Vinod Koul <vinod.koul@intel.com>
This commit is contained in:
Vinod Koul
@@ -46,8 +46,14 @@
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#define EDMA_CHANS 64
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#endif /* CONFIG_ARCH_DAVINCI_DA8XX */
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/* Max of 16 segments per channel to conserve PaRAM slots */
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#define MAX_NR_SG 16
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/*
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* Max of 20 segments per channel to conserve PaRAM slots
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* Also note that MAX_NR_SG should be atleast the no.of periods
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* that are required for ASoC, otherwise DMA prep calls will
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* fail. Today davinci-pcm is the only user of this driver and
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* requires atleast 17 slots, so we setup the default to 20.
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*/
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#define MAX_NR_SG 20
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#define EDMA_MAX_SLOTS MAX_NR_SG
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#define EDMA_DESCRIPTORS 16
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@@ -250,6 +256,117 @@ static int edma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
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return ret;
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}
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/*
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* A PaRAM set configuration abstraction used by other modes
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* @chan: Channel who's PaRAM set we're configuring
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* @pset: PaRAM set to initialize and setup.
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* @src_addr: Source address of the DMA
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* @dst_addr: Destination address of the DMA
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* @burst: In units of dev_width, how much to send
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* @dev_width: How much is the dev_width
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* @dma_length: Total length of the DMA transfer
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* @direction: Direction of the transfer
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*/
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static int edma_config_pset(struct dma_chan *chan, struct edmacc_param *pset,
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dma_addr_t src_addr, dma_addr_t dst_addr, u32 burst,
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enum dma_slave_buswidth dev_width, unsigned int dma_length,
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enum dma_transfer_direction direction)
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{
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struct edma_chan *echan = to_edma_chan(chan);
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struct device *dev = chan->device->dev;
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int acnt, bcnt, ccnt, cidx;
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int src_bidx, dst_bidx, src_cidx, dst_cidx;
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int absync;
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acnt = dev_width;
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/*
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* If the maxburst is equal to the fifo width, use
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* A-synced transfers. This allows for large contiguous
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* buffer transfers using only one PaRAM set.
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*/
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if (burst == 1) {
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/*
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* For the A-sync case, bcnt and ccnt are the remainder
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* and quotient respectively of the division of:
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* (dma_length / acnt) by (SZ_64K -1). This is so
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* that in case bcnt over flows, we have ccnt to use.
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* Note: In A-sync tranfer only, bcntrld is used, but it
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* only applies for sg_dma_len(sg) >= SZ_64K.
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* In this case, the best way adopted is- bccnt for the
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* first frame will be the remainder below. Then for
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* every successive frame, bcnt will be SZ_64K-1. This
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* is assured as bcntrld = 0xffff in end of function.
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*/
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absync = false;
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ccnt = dma_length / acnt / (SZ_64K - 1);
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bcnt = dma_length / acnt - ccnt * (SZ_64K - 1);
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/*
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* If bcnt is non-zero, we have a remainder and hence an
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* extra frame to transfer, so increment ccnt.
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*/
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if (bcnt)
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ccnt++;
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else
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bcnt = SZ_64K - 1;
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cidx = acnt;
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} else {
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/*
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* If maxburst is greater than the fifo address_width,
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* use AB-synced transfers where A count is the fifo
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* address_width and B count is the maxburst. In this
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* case, we are limited to transfers of C count frames
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* of (address_width * maxburst) where C count is limited
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* to SZ_64K-1. This places an upper bound on the length
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* of an SG segment that can be handled.
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*/
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absync = true;
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bcnt = burst;
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ccnt = dma_length / (acnt * bcnt);
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if (ccnt > (SZ_64K - 1)) {
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dev_err(dev, "Exceeded max SG segment size\n");
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return -EINVAL;
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}
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cidx = acnt * bcnt;
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}
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if (direction == DMA_MEM_TO_DEV) {
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src_bidx = acnt;
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src_cidx = cidx;
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dst_bidx = 0;
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dst_cidx = 0;
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} else if (direction == DMA_DEV_TO_MEM) {
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src_bidx = 0;
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src_cidx = 0;
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dst_bidx = acnt;
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dst_cidx = cidx;
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} else {
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dev_err(dev, "%s: direction not implemented yet\n", __func__);
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return -EINVAL;
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}
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pset->opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num));
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/* Configure A or AB synchronized transfers */
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if (absync)
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pset->opt |= SYNCDIM;
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pset->src = src_addr;
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pset->dst = dst_addr;
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pset->src_dst_bidx = (dst_bidx << 16) | src_bidx;
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pset->src_dst_cidx = (dst_cidx << 16) | src_cidx;
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pset->a_b_cnt = bcnt << 16 | acnt;
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pset->ccnt = ccnt;
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/*
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* Only time when (bcntrld) auto reload is required is for
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* A-sync case, and in this case, a requirement of reload value
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* of SZ_64K-1 only is assured. 'link' is initially set to NULL
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* and then later will be populated by edma_execute.
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*/
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pset->link_bcntrld = 0xffffffff;
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return absync;
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}
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static struct dma_async_tx_descriptor *edma_prep_slave_sg(
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struct dma_chan *chan, struct scatterlist *sgl,
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unsigned int sg_len, enum dma_transfer_direction direction,
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@@ -258,23 +375,21 @@ static struct dma_async_tx_descriptor *edma_prep_slave_sg(
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struct edma_chan *echan = to_edma_chan(chan);
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struct device *dev = chan->device->dev;
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struct edma_desc *edesc;
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dma_addr_t dev_addr;
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dma_addr_t src_addr = 0, dst_addr = 0;
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enum dma_slave_buswidth dev_width;
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u32 burst;
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struct scatterlist *sg;
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int acnt, bcnt, ccnt, src, dst, cidx;
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int src_bidx, dst_bidx, src_cidx, dst_cidx;
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int i, nslots;
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int i, nslots, ret;
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if (unlikely(!echan || !sgl || !sg_len))
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return NULL;
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if (direction == DMA_DEV_TO_MEM) {
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dev_addr = echan->cfg.src_addr;
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src_addr = echan->cfg.src_addr;
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dev_width = echan->cfg.src_addr_width;
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burst = echan->cfg.src_maxburst;
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} else if (direction == DMA_MEM_TO_DEV) {
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dev_addr = echan->cfg.dst_addr;
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dst_addr = echan->cfg.dst_addr;
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dev_width = echan->cfg.dst_addr_width;
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burst = echan->cfg.dst_maxburst;
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} else {
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@@ -315,64 +430,21 @@ static struct dma_async_tx_descriptor *edma_prep_slave_sg(
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/* Configure PaRAM sets for each SG */
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for_each_sg(sgl, sg, sg_len, i) {
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/* Get address for each SG */
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if (direction == DMA_DEV_TO_MEM)
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dst_addr = sg_dma_address(sg);
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else
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src_addr = sg_dma_address(sg);
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acnt = dev_width;
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/*
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* If the maxburst is equal to the fifo width, use
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* A-synced transfers. This allows for large contiguous
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* buffer transfers using only one PaRAM set.
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*/
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if (burst == 1) {
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edesc->absync = false;
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ccnt = sg_dma_len(sg) / acnt / (SZ_64K - 1);
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bcnt = sg_dma_len(sg) / acnt - ccnt * (SZ_64K - 1);
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if (bcnt)
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ccnt++;
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else
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bcnt = SZ_64K - 1;
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cidx = acnt;
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/*
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* If maxburst is greater than the fifo address_width,
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* use AB-synced transfers where A count is the fifo
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* address_width and B count is the maxburst. In this
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* case, we are limited to transfers of C count frames
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* of (address_width * maxburst) where C count is limited
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* to SZ_64K-1. This places an upper bound on the length
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* of an SG segment that can be handled.
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*/
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} else {
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edesc->absync = true;
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bcnt = burst;
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ccnt = sg_dma_len(sg) / (acnt * bcnt);
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if (ccnt > (SZ_64K - 1)) {
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dev_err(dev, "Exceeded max SG segment size\n");
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kfree(edesc);
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return NULL;
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}
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cidx = acnt * bcnt;
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ret = edma_config_pset(chan, &edesc->pset[i], src_addr,
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dst_addr, burst, dev_width,
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sg_dma_len(sg), direction);
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if (ret < 0) {
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kfree(edesc);
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return NULL;
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}
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if (direction == DMA_MEM_TO_DEV) {
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src = sg_dma_address(sg);
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dst = dev_addr;
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src_bidx = acnt;
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src_cidx = cidx;
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dst_bidx = 0;
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dst_cidx = 0;
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} else {
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src = dev_addr;
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dst = sg_dma_address(sg);
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src_bidx = 0;
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src_cidx = 0;
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dst_bidx = acnt;
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dst_cidx = cidx;
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}
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edesc->pset[i].opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num));
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/* Configure A or AB synchronized transfers */
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if (edesc->absync)
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edesc->pset[i].opt |= SYNCDIM;
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edesc->absync = ret;
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/* If this is the last in a current SG set of transactions,
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enable interrupts so that next set is processed */
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@@ -382,17 +454,6 @@ static struct dma_async_tx_descriptor *edma_prep_slave_sg(
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/* If this is the last set, enable completion interrupt flag */
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if (i == sg_len - 1)
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edesc->pset[i].opt |= TCINTEN;
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edesc->pset[i].src = src;
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edesc->pset[i].dst = dst;
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edesc->pset[i].src_dst_bidx = (dst_bidx << 16) | src_bidx;
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edesc->pset[i].src_dst_cidx = (dst_cidx << 16) | src_cidx;
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edesc->pset[i].a_b_cnt = bcnt << 16 | acnt;
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edesc->pset[i].ccnt = ccnt;
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edesc->pset[i].link_bcntrld = 0xffffffff;
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}
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return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
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