cxgb3 - parity initialization for T3C adapters.
Add parity initialization for T3C adapters. Signed-off-by: Divy Le Ray <divy@chelsio.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Esse commit está contido em:
@@ -62,7 +62,7 @@ int t3_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
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return 0;
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}
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if (--attempts == 0)
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return -EAGAIN;
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return -EAGAIN;
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if (delay)
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udelay(delay);
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}
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@@ -1263,7 +1263,13 @@ static int t3_handle_intr_status(struct adapter *adapter, unsigned int reg,
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return fatal;
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}
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#define SGE_INTR_MASK (F_RSPQDISABLED)
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#define SGE_INTR_MASK (F_RSPQDISABLED | \
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F_UC_REQ_FRAMINGERROR | F_R_REQ_FRAMINGERROR | \
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F_CPPARITYERROR | F_OCPARITYERROR | F_RCPARITYERROR | \
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F_IRPARITYERROR | V_ITPARITYERROR(M_ITPARITYERROR) | \
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V_FLPARITYERROR(M_FLPARITYERROR) | F_LODRBPARITYERROR | \
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F_HIDRBPARITYERROR | F_LORCQPARITYERROR | \
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F_HIRCQPARITYERROR)
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#define MC5_INTR_MASK (F_PARITYERR | F_ACTRGNFULL | F_UNKNOWNCMD | \
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F_REQQPARERR | F_DISPQPARERR | F_DELACTEMPTY | \
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F_NFASRCHFAIL)
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@@ -1280,16 +1286,23 @@ static int t3_handle_intr_status(struct adapter *adapter, unsigned int reg,
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#define PCIE_INTR_MASK (F_UNXSPLCPLERRR | F_UNXSPLCPLERRC | F_PCIE_PIOPARERR |\
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F_PCIE_WFPARERR | F_PCIE_RFPARERR | F_PCIE_CFPARERR | \
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/* V_PCIE_MSIXPARERR(M_PCIE_MSIXPARERR) | */ \
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V_BISTERR(M_BISTERR))
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#define ULPRX_INTR_MASK F_PARERR
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#define ULPTX_INTR_MASK 0
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#define CPLSW_INTR_MASK (F_TP_FRAMING_ERROR | \
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F_RETRYBUFPARERR | F_RETRYLUTPARERR | F_RXPARERR | \
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F_TXPARERR | V_BISTERR(M_BISTERR))
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#define ULPRX_INTR_MASK (F_PARERRDATA | F_PARERRPCMD | F_ARBPF1PERR | \
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F_ARBPF0PERR | F_ARBFPERR | F_PCMDMUXPERR | \
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F_DATASELFRAMEERR1 | F_DATASELFRAMEERR0)
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#define ULPTX_INTR_MASK 0xfc
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#define CPLSW_INTR_MASK (F_CIM_OP_MAP_PERR | F_TP_FRAMING_ERROR | \
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F_SGE_FRAMING_ERROR | F_CIM_FRAMING_ERROR | \
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F_ZERO_SWITCH_ERROR)
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#define CIM_INTR_MASK (F_BLKWRPLINT | F_BLKRDPLINT | F_BLKWRCTLINT | \
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F_BLKRDCTLINT | F_BLKWRFLASHINT | F_BLKRDFLASHINT | \
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F_SGLWRFLASHINT | F_WRBLKFLASHINT | F_BLKWRBOOTINT | \
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F_FLASHRANGEINT | F_SDRAMRANGEINT | F_RSVDSPACEINT)
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F_FLASHRANGEINT | F_SDRAMRANGEINT | F_RSVDSPACEINT | \
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F_DRAMPARERR | F_ICACHEPARERR | F_DCACHEPARERR | \
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F_OBQSGEPARERR | F_OBQULPHIPARERR | F_OBQULPLOPARERR | \
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F_IBQSGELOPARERR | F_IBQSGEHIPARERR | F_IBQULPPARERR | \
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F_IBQTPPARERR | F_ITAGPARERR | F_DTAGPARERR)
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#define PMTX_INTR_MASK (F_ZERO_C_CMD_ERROR | ICSPI_FRM_ERR | OESPI_FRM_ERR | \
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V_ICSPI_PAR_ERROR(M_ICSPI_PAR_ERROR) | \
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V_OESPI_PAR_ERROR(M_OESPI_PAR_ERROR))
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@@ -1358,6 +1371,10 @@ static void pcie_intr_handler(struct adapter *adapter)
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{F_PCIE_CFPARERR, "PCI command FIFO parity error", -1, 1},
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{V_PCIE_MSIXPARERR(M_PCIE_MSIXPARERR),
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"PCI MSI-X table/PBA parity error", -1, 1},
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{F_RETRYBUFPARERR, "PCI retry buffer parity error", -1, 1},
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{F_RETRYLUTPARERR, "PCI retry LUT parity error", -1, 1},
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{F_RXPARERR, "PCI Rx parity error", -1, 1},
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{F_TXPARERR, "PCI Tx parity error", -1, 1},
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{V_BISTERR(M_BISTERR), "PCI BIST error", -1, 1},
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{0}
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};
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@@ -1384,15 +1401,15 @@ static void tp_intr_handler(struct adapter *adapter)
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};
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static struct intr_info tp_intr_info_t3c[] = {
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{ 0x1ffffff, "TP parity error", -1, 1 },
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{ F_FLMRXFLSTEMPTY, "TP out of Rx pages", -1, 1 },
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{ F_FLMTXFLSTEMPTY, "TP out of Tx pages", -1, 1 },
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{ 0 }
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{0x1fffffff, "TP parity error", -1, 1},
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{F_FLMRXFLSTEMPTY, "TP out of Rx pages", -1, 1},
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{F_FLMTXFLSTEMPTY, "TP out of Tx pages", -1, 1},
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{0}
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};
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if (t3_handle_intr_status(adapter, A_TP_INT_CAUSE, 0xffffffff,
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adapter->params.rev < T3_REV_C ?
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tp_intr_info : tp_intr_info_t3c, NULL))
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tp_intr_info : tp_intr_info_t3c, NULL))
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t3_fatal_err(adapter);
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}
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@@ -1414,6 +1431,18 @@ static void cim_intr_handler(struct adapter *adapter)
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{F_BLKWRCTLINT, "CIM block write to CTL space", -1, 1},
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{F_BLKRDPLINT, "CIM block read from PL space", -1, 1},
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{F_BLKWRPLINT, "CIM block write to PL space", -1, 1},
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{F_DRAMPARERR, "CIM DRAM parity error", -1, 1},
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{F_ICACHEPARERR, "CIM icache parity error", -1, 1},
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{F_DCACHEPARERR, "CIM dcache parity error", -1, 1},
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{F_OBQSGEPARERR, "CIM OBQ SGE parity error", -1, 1},
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{F_OBQULPHIPARERR, "CIM OBQ ULPHI parity error", -1, 1},
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{F_OBQULPLOPARERR, "CIM OBQ ULPLO parity error", -1, 1},
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{F_IBQSGELOPARERR, "CIM IBQ SGELO parity error", -1, 1},
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{F_IBQSGEHIPARERR, "CIM IBQ SGEHI parity error", -1, 1},
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{F_IBQULPPARERR, "CIM IBQ ULP parity error", -1, 1},
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{F_IBQTPPARERR, "CIM IBQ TP parity error", -1, 1},
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{F_ITAGPARERR, "CIM itag parity error", -1, 1},
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{F_DTAGPARERR, "CIM dtag parity error", -1, 1},
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{0}
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};
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@@ -1428,7 +1457,14 @@ static void cim_intr_handler(struct adapter *adapter)
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static void ulprx_intr_handler(struct adapter *adapter)
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{
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static const struct intr_info ulprx_intr_info[] = {
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{F_PARERR, "ULP RX parity error", -1, 1},
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{F_PARERRDATA, "ULP RX data parity error", -1, 1},
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{F_PARERRPCMD, "ULP RX command parity error", -1, 1},
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{F_ARBPF1PERR, "ULP RX ArbPF1 parity error", -1, 1},
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{F_ARBPF0PERR, "ULP RX ArbPF0 parity error", -1, 1},
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{F_ARBFPERR, "ULP RX ArbF parity error", -1, 1},
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{F_PCMDMUXPERR, "ULP RX PCMDMUX parity error", -1, 1},
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{F_DATASELFRAMEERR1, "ULP RX frame error", -1, 1},
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{F_DATASELFRAMEERR0, "ULP RX frame error", -1, 1},
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{0}
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};
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@@ -1447,6 +1483,7 @@ static void ulptx_intr_handler(struct adapter *adapter)
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STAT_ULP_CH0_PBL_OOB, 0},
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{F_PBL_BOUND_ERR_CH1, "ULP TX channel 1 PBL out of bounds",
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STAT_ULP_CH1_PBL_OOB, 0},
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{0xfc, "ULP TX parity error", -1, 1},
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{0}
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};
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@@ -1521,7 +1558,8 @@ static void pmrx_intr_handler(struct adapter *adapter)
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static void cplsw_intr_handler(struct adapter *adapter)
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{
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static const struct intr_info cplsw_intr_info[] = {
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/* { F_CIM_OVFL_ERROR, "CPL switch CIM overflow", -1, 1 }, */
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{F_CIM_OP_MAP_PERR, "CPL switch CIM parity error", -1, 1},
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{F_CIM_OVFL_ERROR, "CPL switch CIM overflow", -1, 1},
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{F_TP_FRAMING_ERROR, "CPL switch TP framing error", -1, 1},
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{F_SGE_FRAMING_ERROR, "CPL switch SGE framing error", -1, 1},
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{F_CIM_FRAMING_ERROR, "CPL switch CIM framing error", -1, 1},
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@@ -1907,6 +1945,16 @@ static int t3_sge_write_context(struct adapter *adapter, unsigned int id,
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0, SG_CONTEXT_CMD_ATTEMPTS, 1);
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}
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static int clear_sge_ctxt(struct adapter *adap, unsigned int id,
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unsigned int type)
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{
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t3_write_reg(adap, A_SG_CONTEXT_DATA0, 0);
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t3_write_reg(adap, A_SG_CONTEXT_DATA1, 0);
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t3_write_reg(adap, A_SG_CONTEXT_DATA2, 0);
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t3_write_reg(adap, A_SG_CONTEXT_DATA3, 0);
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return t3_sge_write_context(adap, id, type);
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}
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/**
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* t3_sge_init_ecntxt - initialize an SGE egress context
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* @adapter: the adapter to configure
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@@ -2408,7 +2456,7 @@ static inline unsigned int pm_num_pages(unsigned int mem_size,
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t3_write_reg((adap), A_ ## reg, (start)); \
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start += size
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/*
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/**
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* partition_mem - partition memory and configure TP memory settings
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* @adap: the adapter
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* @p: the TP parameters
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@@ -2493,7 +2541,7 @@ static void tp_config(struct adapter *adap, const struct tp_params *p)
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V_AUTOSTATE2(1) | V_AUTOSTATE1(0) |
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V_BYTETHRESHOLD(16384) | V_MSSTHRESHOLD(2) |
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F_AUTOCAREFUL | F_AUTOENABLE | V_DACK_MODE(1));
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t3_set_reg_field(adap, A_TP_IN_CONFIG, F_IPV6ENABLE | F_NICMODE,
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t3_set_reg_field(adap, A_TP_IN_CONFIG, F_RXFBARBPRIO | F_TXFBARBPRIO,
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F_IPV6ENABLE | F_NICMODE);
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t3_write_reg(adap, A_TP_TX_RESOURCE_LIMIT, 0x18141814);
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t3_write_reg(adap, A_TP_PARA_REG4, 0x5050105);
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@@ -2505,7 +2553,9 @@ static void tp_config(struct adapter *adap, const struct tp_params *p)
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F_ENABLEEPCMDAFULL,
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F_ENABLEOCSPIFULL |F_TXDEFERENABLE | F_HEARBEATDACK |
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F_TXCONGESTIONMODE | F_RXCONGESTIONMODE);
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t3_set_reg_field(adap, A_TP_PC_CONFIG2, F_CHDRAFULL, 0);
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t3_set_reg_field(adap, A_TP_PC_CONFIG2, F_CHDRAFULL,
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F_ENABLEIPV6RSS | F_ENABLENONOFDTNLSYN |
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F_ENABLEARPMISS | F_DISBLEDAPARBIT0);
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t3_write_reg(adap, A_TP_PROXY_FLOW_CNTL, 1080);
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t3_write_reg(adap, A_TP_PROXY_FLOW_CNTL, 1000);
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@@ -3212,7 +3262,8 @@ static void config_pcie(struct adapter *adap)
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V_REPLAYLMT(rpllmt));
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t3_write_reg(adap, A_PCIE_PEX_ERR, 0xffffffff);
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t3_set_reg_field(adap, A_PCIE_CFG, F_PCIE_CLIDECEN, F_PCIE_CLIDECEN);
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t3_set_reg_field(adap, A_PCIE_CFG, 0,
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F_PCIE_DMASTOPEN | F_PCIE_CLIDECEN);
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}
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/*
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@@ -3225,7 +3276,7 @@ static void config_pcie(struct adapter *adap)
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*/
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int t3_init_hw(struct adapter *adapter, u32 fw_params)
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{
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int err = -EIO, attempts = 100;
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int err = -EIO, attempts, i;
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const struct vpd_params *vpd = &adapter->params.vpd;
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if (adapter->params.rev > 0)
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@@ -3243,6 +3294,10 @@ int t3_init_hw(struct adapter *adapter, u32 fw_params)
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adapter->params.mc5.nfilters,
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adapter->params.mc5.nroutes))
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goto out_err;
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for (i = 0; i < 32; i++)
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if (clear_sge_ctxt(adapter, i, F_CQ))
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goto out_err;
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}
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if (tp_init(adapter, &adapter->params.tp))
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@@ -3258,7 +3313,8 @@ int t3_init_hw(struct adapter *adapter, u32 fw_params)
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if (is_pcie(adapter))
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config_pcie(adapter);
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else
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t3_set_reg_field(adapter, A_PCIX_CFG, 0, F_CLIDECEN);
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t3_set_reg_field(adapter, A_PCIX_CFG, 0,
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F_DMASTOPEN | F_CLIDECEN);
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if (adapter->params.rev == T3_REV_C)
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t3_set_reg_field(adapter, A_ULPTX_CONFIG, 0,
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@@ -3275,6 +3331,7 @@ int t3_init_hw(struct adapter *adapter, u32 fw_params)
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V_BOOTADDR(FW_FLASH_BOOT_ADDR >> 2));
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t3_read_reg(adapter, A_CIM_BOOT_CFG); /* flush */
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attempts = 100;
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do { /* wait for uP to initialize */
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msleep(20);
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} while (t3_read_reg(adapter, A_CIM_HOST_ACC_DATA) && --attempts);
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@@ -3409,6 +3466,7 @@ void early_hw_init(struct adapter *adapter, const struct adapter_info *ai)
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t3_write_reg(adapter, A_T3DBG_GPIO_EN,
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ai->gpio_out | F_GPIO0_OEN | F_GPIO0_OUT_VAL);
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t3_write_reg(adapter, A_MC5_DB_SERVER_INDEX, 0);
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t3_write_reg(adapter, A_SG_OCO_BASE, V_BASE1(0xfff));
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if (adapter->params.rev == 0 || !uses_xaui(adapter))
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val |= F_ENRGMII;
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@@ -3458,6 +3516,36 @@ static int t3_reset_adapter(struct adapter *adapter)
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return 0;
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}
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static int __devinit init_parity(struct adapter *adap)
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{
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int i, err, addr;
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if (t3_read_reg(adap, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
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return -EBUSY;
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for (err = i = 0; !err && i < 16; i++)
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err = clear_sge_ctxt(adap, i, F_EGRESS);
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for (i = 0xfff0; !err && i <= 0xffff; i++)
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err = clear_sge_ctxt(adap, i, F_EGRESS);
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for (i = 0; !err && i < SGE_QSETS; i++)
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err = clear_sge_ctxt(adap, i, F_RESPONSEQ);
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if (err)
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return err;
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t3_write_reg(adap, A_CIM_IBQ_DBG_DATA, 0);
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for (i = 0; i < 4; i++)
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for (addr = 0; addr <= M_IBQDBGADDR; addr++) {
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t3_write_reg(adap, A_CIM_IBQ_DBG_CFG, F_IBQDBGEN |
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F_IBQDBGWR | V_IBQDBGQID(i) |
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V_IBQDBGADDR(addr));
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err = t3_wait_op_done(adap, A_CIM_IBQ_DBG_CFG,
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F_IBQDBGBUSY, 0, 2, 1);
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if (err)
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return err;
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}
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return 0;
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}
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/*
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* Initialize adapter SW state for the various HW modules, set initial values
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* for some adapter tunables, take PHYs out of reset, and initialize the MDIO
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@@ -3525,6 +3613,9 @@ int __devinit t3_prep_adapter(struct adapter *adapter,
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}
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early_hw_init(adapter, ai);
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ret = init_parity(adapter);
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if (ret)
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return ret;
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for_each_port(adapter, i) {
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u8 hw_addr[6];
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