DMAENGINE: COH 901 318 descriptor pool refactoring
This centralize some spread-out initialization of descriptors into one function and cleans up the error paths. Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
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committed by
Dan Williams

parent
848ad12124
commit
b87108a772
@@ -53,7 +53,7 @@ struct coh901318_params {
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* struct coh_dma_channel - dma channel base
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* struct coh_dma_channel - dma channel base
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* @name: ascii name of dma channel
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* @name: ascii name of dma channel
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* @number: channel id number
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* @number: channel id number
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* @desc_nbr_max: number of preallocated descriptortors
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* @desc_nbr_max: number of preallocated descriptors
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* @priority_high: prio of channel, 0 low otherwise high.
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* @priority_high: prio of channel, 0 low otherwise high.
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* @param: configuration parameters
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* @param: configuration parameters
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* @dev_addr: physical address of periphal connected to channel
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* @dev_addr: physical address of periphal connected to channel
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@@ -335,16 +335,22 @@ coh901318_desc_get(struct coh901318_chan *cohc)
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* TODO: alloc a pile of descs instead of just one,
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* TODO: alloc a pile of descs instead of just one,
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* avoid many small allocations.
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* avoid many small allocations.
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*/
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*/
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desc = kmalloc(sizeof(struct coh901318_desc), GFP_NOWAIT);
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desc = kzalloc(sizeof(struct coh901318_desc), GFP_NOWAIT);
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if (desc == NULL)
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if (desc == NULL)
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goto out;
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goto out;
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INIT_LIST_HEAD(&desc->node);
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INIT_LIST_HEAD(&desc->node);
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dma_async_tx_descriptor_init(&desc->desc, &cohc->chan);
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} else {
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} else {
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/* Reuse an old desc. */
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/* Reuse an old desc. */
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desc = list_first_entry(&cohc->free,
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desc = list_first_entry(&cohc->free,
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struct coh901318_desc,
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struct coh901318_desc,
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node);
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node);
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list_del(&desc->node);
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list_del(&desc->node);
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/* Initialize it a bit so it's not insane */
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desc->sg = NULL;
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desc->sg_len = 0;
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desc->desc.callback = NULL;
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desc->desc.callback_param = NULL;
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}
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}
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out:
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out:
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@@ -885,6 +891,7 @@ coh901318_prep_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
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struct coh901318_chan *cohc = to_coh901318_chan(chan);
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struct coh901318_chan *cohc = to_coh901318_chan(chan);
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int lli_len;
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int lli_len;
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u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last;
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u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last;
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int ret;
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spin_lock_irqsave(&cohc->lock, flg);
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spin_lock_irqsave(&cohc->lock, flg);
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@@ -905,22 +912,19 @@ coh901318_prep_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
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if (data == NULL)
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if (data == NULL)
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goto err;
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goto err;
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cohd = coh901318_desc_get(cohc);
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ret = coh901318_lli_fill_memcpy(
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cohd->sg = NULL;
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&cohc->base->pool, data, src, size, dest,
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cohd->sg_len = 0;
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cohc_chan_param(cohc)->ctrl_lli_chained,
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cohd->data = data;
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ctrl_last);
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if (ret)
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cohd->pending_irqs =
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goto err;
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coh901318_lli_fill_memcpy(
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&cohc->base->pool, data, src, size, dest,
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cohc_chan_param(cohc)->ctrl_lli_chained,
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ctrl_last);
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cohd->flags = flags;
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COH_DBG(coh901318_list_print(cohc, data));
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COH_DBG(coh901318_list_print(cohc, data));
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dma_async_tx_descriptor_init(&cohd->desc, chan);
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/* Pick a descriptor to handle this transfer */
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cohd = coh901318_desc_get(cohc);
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cohd->data = data;
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cohd->flags = flags;
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cohd->desc.tx_submit = coh901318_tx_submit;
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cohd->desc.tx_submit = coh901318_tx_submit;
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spin_unlock_irqrestore(&cohc->lock, flg);
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spin_unlock_irqrestore(&cohc->lock, flg);
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@@ -962,11 +966,6 @@ coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
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/* Trigger interrupt after last lli */
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/* Trigger interrupt after last lli */
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ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE;
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ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE;
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cohd = coh901318_desc_get(cohc);
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cohd->sg = NULL;
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cohd->sg_len = 0;
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cohd->dir = direction;
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if (direction == DMA_TO_DEVICE) {
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if (direction == DMA_TO_DEVICE) {
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u32 tx_flags = COH901318_CX_CTRL_PRDD_SOURCE |
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u32 tx_flags = COH901318_CX_CTRL_PRDD_SOURCE |
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COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE;
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COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE;
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@@ -984,11 +983,6 @@ coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
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} else
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} else
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goto err_direction;
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goto err_direction;
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dma_async_tx_descriptor_init(&cohd->desc, chan);
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cohd->desc.tx_submit = coh901318_tx_submit;
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/* The dma only supports transmitting packages up to
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/* The dma only supports transmitting packages up to
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* MAX_DMA_PACKET_SIZE. Calculate to total number of
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* MAX_DMA_PACKET_SIZE. Calculate to total number of
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* dma elemts required to send the entire sg list
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* dma elemts required to send the entire sg list
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@@ -1023,19 +1017,21 @@ coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
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ctrl,
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ctrl,
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ctrl_last,
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ctrl_last,
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direction, COH901318_CX_CTRL_TC_IRQ_ENABLE);
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direction, COH901318_CX_CTRL_TC_IRQ_ENABLE);
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cohd->data = data;
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cohd->flags = flags;
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COH_DBG(coh901318_list_print(cohc, data));
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COH_DBG(coh901318_list_print(cohc, data));
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/* Pick a descriptor to handle this transfer */
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cohd = coh901318_desc_get(cohc);
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cohd->dir = direction;
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cohd->flags = flags;
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cohd->desc.tx_submit = coh901318_tx_submit;
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cohd->data = data;
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spin_unlock_irqrestore(&cohc->lock, flg);
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spin_unlock_irqrestore(&cohc->lock, flg);
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return &cohd->desc;
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return &cohd->desc;
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err_dma_alloc:
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err_dma_alloc:
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err_direction:
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err_direction:
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coh901318_desc_remove(cohd);
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coh901318_desc_free(cohc, cohd);
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spin_unlock_irqrestore(&cohc->lock, flg);
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spin_unlock_irqrestore(&cohc->lock, flg);
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out:
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out:
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return NULL;
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return NULL;
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