Merge branch 'omap-all' into devel
Conflicts: arch/arm/mach-omap2/gpmc.c arch/arm/mach-omap2/irq.c
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@@ -62,11 +62,14 @@ static void omap3_dpll_recalc(struct clk *clk)
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static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
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{
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const struct dpll_data *dd;
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u32 v;
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dd = clk->dpll_data;
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cm_rmw_reg_bits(dd->enable_mask, clken_bits << __ffs(dd->enable_mask),
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dd->control_reg);
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v = __raw_readl(dd->control_reg);
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v &= ~dd->enable_mask;
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v |= clken_bits << __ffs(dd->enable_mask);
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__raw_writel(v, dd->control_reg);
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}
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/* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
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@@ -82,7 +85,7 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
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state <<= dd->idlest_bit;
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idlest_mask = 1 << dd->idlest_bit;
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while (((cm_read_reg(dd->idlest_reg) & idlest_mask) != state) &&
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while (((__raw_readl(dd->idlest_reg) & idlest_mask) != state) &&
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i < MAX_DPLL_WAIT_TRIES) {
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i++;
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udelay(1);
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@@ -285,7 +288,7 @@ static u32 omap3_dpll_autoidle_read(struct clk *clk)
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dd = clk->dpll_data;
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v = cm_read_reg(dd->autoidle_reg);
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v = __raw_readl(dd->autoidle_reg);
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v &= dd->autoidle_mask;
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v >>= __ffs(dd->autoidle_mask);
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@@ -304,6 +307,7 @@ static u32 omap3_dpll_autoidle_read(struct clk *clk)
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static void omap3_dpll_allow_idle(struct clk *clk)
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{
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const struct dpll_data *dd;
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u32 v;
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if (!clk || !clk->dpll_data)
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return;
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@@ -315,9 +319,10 @@ static void omap3_dpll_allow_idle(struct clk *clk)
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* by writing 0x5 instead of 0x1. Add some mechanism to
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* optionally enter this mode.
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*/
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cm_rmw_reg_bits(dd->autoidle_mask,
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DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask),
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dd->autoidle_reg);
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v = __raw_readl(dd->autoidle_reg);
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v &= ~dd->autoidle_mask;
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v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
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__raw_writel(v, dd->autoidle_reg);
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}
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/**
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@@ -329,15 +334,17 @@ static void omap3_dpll_allow_idle(struct clk *clk)
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static void omap3_dpll_deny_idle(struct clk *clk)
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{
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const struct dpll_data *dd;
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u32 v;
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if (!clk || !clk->dpll_data)
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return;
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dd = clk->dpll_data;
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cm_rmw_reg_bits(dd->autoidle_mask,
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DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask),
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dd->autoidle_reg);
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v = __raw_readl(dd->autoidle_reg);
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v &= ~dd->autoidle_mask;
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v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
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__raw_writel(v, dd->autoidle_reg);
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}
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/* Clock control for DPLL outputs */
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@@ -482,8 +489,10 @@ int __init omap2_clk_init(void)
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for (clkp = onchip_34xx_clks;
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clkp < onchip_34xx_clks + ARRAY_SIZE(onchip_34xx_clks);
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clkp++) {
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if ((*clkp)->flags & cpu_clkflg)
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if ((*clkp)->flags & cpu_clkflg) {
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clk_register(*clkp);
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omap2_init_clk_clkdm(*clkp);
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}
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}
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/* REVISIT: Not yet ready for OMAP3 */
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