Merge tag 'mailbox-v5.4' of git://git.linaro.org/landing-teams/working/fujitsu/integration
Pull mailbox updates from Jassi Brar: - qcom: - enable support for ipq8074, sm1850 and sm7180 - add child device node for qcs404 - misc fixes - mediatek: - enable support for mt8183 - misc rejig of cmdq driver - new client-reg dt property - armada: - use device-managed registration api * tag 'mailbox-v5.4' of git://git.linaro.org/landing-teams/working/fujitsu/integration: mailbox: qcom-apcs: fix max_register value mailbox: qcom: Add support for IPQ8074 APCS dt-bindings: mailbox: qom: Add ipq8074 APPS compatible mailbox: qcom: Add support for Qualcomm SM8150 and SC7180 SoCs dt-bindings: mailbox: Add APSS shared for SM8150 and SC7180 SoCs mbox: qcom: replace integer with valid macro mbox: qcom: add APCS child device for QCS404 mailbox: mediatek: cmdq: clear the event in cmdq initial flow mailbox: mediatek: cmdq: support mt8183 gce function mailbox: mediatek: cmdq: move the CMDQ_IRQ_MASK into cmdq driver data dt-binding: gce: add binding for gce client reg property dt-binding: gce: add gce header file for mt8183 dt-binding: gce: remove thread-num property mailbox: armada-37xx-rwtm: Use device-managed registration API
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@@ -9,7 +9,7 @@ CMDQ driver uses mailbox framework for communication. Please refer to
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mailbox.txt for generic information about mailbox device-tree bindings.
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Required properties:
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- compatible: Must be "mediatek,mt8173-gce"
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- compatible: can be "mediatek,mt8173-gce" or "mediatek,mt8183-gce"
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- reg: Address range of the GCE unit
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- interrupts: The interrupt signal from the GCE block
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- clock: Clocks according to the common clock binding
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@@ -25,11 +25,19 @@ Required properties:
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Required properties for a client device:
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- mboxes: Client use mailbox to communicate with GCE, it should have this
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property and list of phandle, mailbox specifiers.
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- mediatek,gce-subsys: u32, specify the sub-system id which is corresponding
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to the register address.
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Optional properties for a client device:
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- mediatek,gce-client-reg: Specify the sub-system id which is corresponding
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to the register address, it should have this property and list of phandle,
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sub-system specifiers.
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<&phandle subsys_number start_offset size>
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phandle: Label name of a gce node.
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subsys_number: specify the sub-system id which is corresponding
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to the register address.
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start_offset: the start offset of register address that GCE can access.
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size: the total size of register address that GCE can access.
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Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h'. Such as
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sub-system ids, thread priority, event ids.
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Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h'
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or 'dt-binding/gce/mt8183-gce.h'. Such as sub-system ids, thread priority, event ids.
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Example:
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@@ -39,7 +47,6 @@ Example:
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interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&infracfg CLK_INFRA_GCE>;
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clock-names = "gce";
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thread-num = CMDQ_THR_MAX_COUNT;
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#mbox-cells = <3>;
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};
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@@ -49,9 +56,9 @@ Example for a client device:
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compatible = "mediatek,mt8173-mmsys";
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mboxes = <&gce 0 CMDQ_THR_PRIO_LOWEST 1>,
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<&gce 1 CMDQ_THR_PRIO_LOWEST 1>;
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mediatek,gce-subsys = <SUBSYS_1400XXXX>;
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mutex-event-eof = <CMDQ_EVENT_MUTEX0_STREAM_EOF
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CMDQ_EVENT_MUTEX1_STREAM_EOF>;
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mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>,
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<&gce SUBSYS_1401XXXX 0x2000 0x100>;
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...
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};
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@@ -12,7 +12,10 @@ platforms.
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"qcom,msm8996-apcs-hmss-global"
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"qcom,msm8998-apcs-hmss-global"
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"qcom,qcs404-apcs-apps-global"
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"qcom,sc7180-apss-shared"
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"qcom,sdm845-apss-shared"
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"qcom,sm8150-apss-shared"
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"qcom,ipq8074-apcs-apps-global"
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- reg:
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Usage: required
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