Merge tag 'mips_5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
Pull MIPS upates from Thomas Bogendoerfer: - improvements for Loongson64 - extended ingenic support - removal of not maintained paravirt system type - cleanups and fixes * tag 'mips_5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (81 commits) MIPS: SGI-IP27: always enable NUMA in Kconfig MAINTAINERS: Update KVM/MIPS maintainers MIPS: Update default config file for Loongson-3 MIPS: KVM: Add kvm guest support for Loongson-3 dt-bindings: mips: Document Loongson kvm guest board MIPS: handle Loongson-specific GSExc exception MIPS: add definitions for Loongson-specific CP0.Diag1 register MIPS: only register FTLBPar exception handler for supported models MIPS: ingenic: Hardcode mem size for qi,lb60 board MIPS: DTS: ingenic/qi,lb60: Add model and memory node MIPS: ingenic: Use fw_passed_dtb even if CONFIG_BUILTIN_DTB MIPS: head.S: Init fw_passed_dtb to builtin DTB of: address: Fix parser address/size cells initialization of_address: Guard of_bus_pci_get_flags with CONFIG_PCI MIPS: DTS: Fix number of msi vectors for Loongson64G MIPS: Loongson64: Add ISA node for LS7A PCH MIPS: Loongson64: DTS: Fix ISA and PCI I/O ranges for RS780E PCH MIPS: Loongson64: Enlarge IO_SPACE_LIMIT MIPS: Loongson64: Process ISA Node in DeviceTree of_address: Add bus type match for pci ranges parser ...
This commit is contained in:
Linus Torvalds
@@ -1,7 +1,9 @@
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||||
# SPDX-License-Identifier: GPL-2.0
|
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dtb-$(CONFIG_JZ4740_QI_LB60) += qi_lb60.dtb
|
||||
dtb-$(CONFIG_JZ4740_RS90) += rs90.dtb
|
||||
dtb-$(CONFIG_JZ4770_GCW0) += gcw0.dtb
|
||||
dtb-$(CONFIG_JZ4780_CI20) += ci20.dtb
|
||||
dtb-$(CONFIG_X1000_CU1000_NEO) += cu1000-neo.dtb
|
||||
dtb-$(CONFIG_X1830_CU1830_NEO) += cu1830-neo.dtb
|
||||
|
||||
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
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||||
|
||||
@@ -7,8 +7,8 @@
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
compatible = "yna,cu1000-neo", "ingenic,x1000";
|
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model = "YSH & ATIL General Board CU Neo";
|
||||
compatible = "yna,cu1000-neo", "ingenic,x1000e";
|
||||
model = "YSH & ATIL General Board CU1000-Neo";
|
||||
|
||||
aliases {
|
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serial2 = &uart2;
|
||||
@@ -23,20 +23,19 @@
|
||||
reg = <0x0 0x04000000>;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
led-0 {
|
||||
gpios = <&gpb 21 GPIO_ACTIVE_HIGH>;
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||||
linux,default-trigger = "mmc0";
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||||
};
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||||
};
|
||||
|
||||
wlan_pwrseq: msc1-pwrseq {
|
||||
compatible = "mmc-pwrseq-simple";
|
||||
|
||||
clocks = <&lpoclk>;
|
||||
clock-names = "ext_clock";
|
||||
|
||||
reset-gpios = <&gpc 17 GPIO_ACTIVE_LOW>;
|
||||
post-power-on-delay-ms = <200>;
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||||
|
||||
lpoclk: ap6212a {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
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||||
};
|
||||
};
|
||||
};
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||||
|
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@@ -53,6 +52,13 @@
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||||
ingenic,pwm-channels-mask = <0xfa>;
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};
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|
||||
&uart2 {
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status = "okay";
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||||
pinctrl-names = "default";
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||||
pinctrl-0 = <&pins_uart2>;
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||||
};
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||||
|
||||
&i2c0 {
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status = "okay";
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||||
|
||||
@@ -61,43 +67,15 @@
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||||
pinctrl-names = "default";
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||||
pinctrl-0 = <&pins_i2c0>;
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||||
|
||||
ads7830@48 {
|
||||
ads7830: adc@48 {
|
||||
compatible = "ti,ads7830";
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||||
reg = <0x48>;
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||||
};
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pins_uart2>;
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||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mac {
|
||||
phy-mode = "rmii";
|
||||
phy-handle = <&lan8720a>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pins_mac>;
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||||
|
||||
snps,reset-gpio = <&gpc 23 GPIO_ACTIVE_LOW>; /* PC23 */
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||||
snps,reset-active-low;
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snps,reset-delays-us = <0 10000 30000>;
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||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdio {
|
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status = "okay";
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||||
|
||||
lan8720a: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-id0007.c0f0", "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&msc0 {
|
||||
status = "okay";
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||||
|
||||
bus-width = <8>;
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||||
max-frequency = <50000000>;
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||||
|
||||
@@ -105,26 +83,23 @@
|
||||
pinctrl-0 = <&pins_msc0>;
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||||
|
||||
non-removable;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&msc1 {
|
||||
status = "okay";
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||||
|
||||
#address-cells = <1>;
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||||
#size-cells = <0>;
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||||
bus-width = <4>;
|
||||
max-frequency = <50000000>;
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||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pins_msc1>;
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||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
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||||
|
||||
non-removable;
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||||
|
||||
mmc-pwrseq = <&wlan_pwrseq>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
ap6212a: wifi@1 {
|
||||
compatible = "brcm,bcm4329-fmac";
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||||
reg = <1>;
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||||
@@ -137,23 +112,40 @@
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||||
};
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||||
};
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||||
|
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&pinctrl {
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||||
pins_i2c0: i2c0 {
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||||
function = "i2c0";
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||||
groups = "i2c0-data";
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bias-disable;
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};
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&mac {
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||||
status = "okay";
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||||
|
||||
phy-mode = "rmii";
|
||||
phy-handle = <&lan8720a>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pins_mac>;
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||||
|
||||
snps,reset-gpio = <&gpc 23 GPIO_ACTIVE_LOW>; /* PC23 */
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||||
snps,reset-active-low;
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||||
snps,reset-delays-us = <0 10000 30000>;
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||||
};
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||||
|
||||
&mdio {
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||||
status = "okay";
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||||
|
||||
lan8720a: ethernet-phy@0 {
|
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compatible = "ethernet-phy-id0007.c0f0", "ethernet-phy-ieee802.3-c22";
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||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
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&pinctrl {
|
||||
pins_uart2: uart2 {
|
||||
function = "uart2";
|
||||
groups = "uart2-data-d";
|
||||
bias-disable;
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||||
bias-pull-up;
|
||||
};
|
||||
|
||||
pins_mac: mac {
|
||||
function = "mac";
|
||||
groups = "mac";
|
||||
bias-disable;
|
||||
pins_i2c0: i2c0 {
|
||||
function = "i2c0";
|
||||
groups = "i2c0-data";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
pins_msc0: msc0 {
|
||||
@@ -167,4 +159,10 @@
|
||||
groups = "mmc1-1bit", "mmc1-4bit";
|
||||
bias-disable;
|
||||
};
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||||
|
||||
pins_mac: mac {
|
||||
function = "mac";
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||||
groups = "mac";
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||||
bias-disable;
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||||
};
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||||
};
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|
||||
168
arch/mips/boot/dts/ingenic/cu1830-neo.dts
Normal file
168
arch/mips/boot/dts/ingenic/cu1830-neo.dts
Normal file
@@ -0,0 +1,168 @@
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||||
// SPDX-License-Identifier: GPL-2.0
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||||
/dts-v1/;
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||||
|
||||
#include "x1830.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clock/ingenic,tcu.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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||||
|
||||
/ {
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||||
compatible = "yna,cu1830-neo", "ingenic,x1830";
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model = "YSH & ATIL General Board CU1830-Neo";
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||||
|
||||
aliases {
|
||||
serial1 = &uart1;
|
||||
};
|
||||
|
||||
chosen {
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||||
stdout-path = "serial1:115200n8";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
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||||
reg = <0x0 0x08000000>;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
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||||
led-0 {
|
||||
gpios = <&gpc 17 GPIO_ACTIVE_HIGH>;
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||||
linux,default-trigger = "mmc0";
|
||||
};
|
||||
};
|
||||
|
||||
wlan_pwrseq: msc1-pwrseq {
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||||
compatible = "mmc-pwrseq-simple";
|
||||
|
||||
reset-gpios = <&gpc 13 GPIO_ACTIVE_LOW>;
|
||||
post-power-on-delay-ms = <200>;
|
||||
};
|
||||
};
|
||||
|
||||
&exclk {
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clock-frequency = <24000000>;
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||||
};
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||||
|
||||
&tcu {
|
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/* 1500 kHz for the system timer and clocksource */
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assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER2>;
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assigned-clock-rates = <1500000>, <1500000>;
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|
||||
/* Use channel #0 for the system timer channel #2 for the clocksource */
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||||
ingenic,pwm-channels-mask = <0xfa>;
|
||||
};
|
||||
|
||||
&uart1 {
|
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status = "okay";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pins_uart1>;
|
||||
};
|
||||
|
||||
&i2c0 {
|
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status = "okay";
|
||||
|
||||
clock-frequency = <400000>;
|
||||
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||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pins_i2c0>;
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|
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ads7830: adc@48 {
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compatible = "ti,ads7830";
|
||||
reg = <0x48>;
|
||||
};
|
||||
};
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||||
|
||||
&msc0 {
|
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status = "okay";
|
||||
|
||||
bus-width = <4>;
|
||||
max-frequency = <50000000>;
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||||
|
||||
pinctrl-names = "default";
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pinctrl-0 = <&pins_msc0>;
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||||
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||||
non-removable;
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||||
};
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||||
|
||||
&msc1 {
|
||||
status = "okay";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
bus-width = <4>;
|
||||
max-frequency = <50000000>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pins_msc1>;
|
||||
|
||||
non-removable;
|
||||
|
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mmc-pwrseq = <&wlan_pwrseq>;
|
||||
|
||||
ap6212a: wifi@1 {
|
||||
compatible = "brcm,bcm4329-fmac";
|
||||
reg = <1>;
|
||||
|
||||
interrupt-parent = <&gpc>;
|
||||
interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
|
||||
interrupt-names = "host-wake";
|
||||
|
||||
brcm,drive-strength = <10>;
|
||||
};
|
||||
};
|
||||
|
||||
&mac {
|
||||
status = "okay";
|
||||
|
||||
phy-mode = "rmii";
|
||||
phy-handle = <&ip101gr>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pins_mac>;
|
||||
|
||||
snps,reset-gpio = <&gpb 28 GPIO_ACTIVE_LOW>; /* PB28 */
|
||||
snps,reset-active-low;
|
||||
snps,reset-delays-us = <0 10000 30000>;
|
||||
};
|
||||
|
||||
&mdio {
|
||||
status = "okay";
|
||||
|
||||
ip101gr: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-id0243.0c54", "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
pins_uart1: uart1 {
|
||||
function = "uart1";
|
||||
groups = "uart1-data";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
pins_i2c0: i2c0 {
|
||||
function = "i2c0";
|
||||
groups = "i2c0-data";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
pins_msc0: msc0 {
|
||||
function = "mmc0";
|
||||
groups = "mmc0-1bit", "mmc0-4bit";
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pins_msc1: msc1 {
|
||||
function = "mmc1";
|
||||
groups = "mmc1-1bit", "mmc1-4bit";
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pins_mac: mac {
|
||||
function = "mac";
|
||||
groups = "mac";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
364
arch/mips/boot/dts/ingenic/jz4725b.dtsi
Normal file
364
arch/mips/boot/dts/ingenic/jz4725b.dtsi
Normal file
@@ -0,0 +1,364 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
#include <dt-bindings/clock/jz4725b-cgu.h>
|
||||
#include <dt-bindings/clock/ingenic,tcu.h>
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "ingenic,jz4725b";
|
||||
|
||||
cpuintc: interrupt-controller {
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
compatible = "mti,cpu-interrupt-controller";
|
||||
};
|
||||
|
||||
intc: interrupt-controller@10001000 {
|
||||
compatible = "ingenic,jz4725b-intc", "ingenic,jz4740-intc";
|
||||
reg = <0x10001000 0x14>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&cpuintc>;
|
||||
interrupts = <2>;
|
||||
};
|
||||
|
||||
ext: ext {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
osc32k: osc32k {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
cgu: clock-controller@10000000 {
|
||||
compatible = "ingenic,jz4725b-cgu";
|
||||
reg = <0x10000000 0x100>;
|
||||
|
||||
clocks = <&ext>, <&osc32k>;
|
||||
clock-names = "ext", "osc32k";
|
||||
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
tcu: timer@10002000 {
|
||||
compatible = "ingenic,jz4725b-tcu", "simple-mfd";
|
||||
reg = <0x10002000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x10002000 0x1000>;
|
||||
|
||||
#clock-cells = <1>;
|
||||
|
||||
clocks = <&cgu JZ4725B_CLK_RTC>,
|
||||
<&cgu JZ4725B_CLK_EXT>,
|
||||
<&cgu JZ4725B_CLK_PCLK>,
|
||||
<&cgu JZ4725B_CLK_TCU>;
|
||||
clock-names = "rtc", "ext", "pclk", "tcu";
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <23>, <22>, <21>;
|
||||
|
||||
watchdog: watchdog@0 {
|
||||
compatible = "ingenic,jz4725b-watchdog", "ingenic,jz4740-watchdog";
|
||||
reg = <0x0 0xc>;
|
||||
|
||||
clocks = <&tcu TCU_CLK_WDT>;
|
||||
clock-names = "wdt";
|
||||
};
|
||||
|
||||
pwm: pwm@60 {
|
||||
compatible = "ingenic,jz4725b-pwm";
|
||||
reg = <0x60 0x40>;
|
||||
|
||||
#pwm-cells = <3>;
|
||||
|
||||
clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
|
||||
<&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_TIMER3>,
|
||||
<&tcu TCU_CLK_TIMER4>, <&tcu TCU_CLK_TIMER5>;
|
||||
clock-names = "timer0", "timer1", "timer2",
|
||||
"timer3", "timer4", "timer5";
|
||||
};
|
||||
|
||||
ost: timer@e0 {
|
||||
compatible = "ingenic,jz4725b-ost";
|
||||
reg = <0xe0 0x20>;
|
||||
|
||||
clocks = <&tcu TCU_CLK_OST>;
|
||||
clock-names = "ost";
|
||||
|
||||
interrupts = <15>;
|
||||
};
|
||||
};
|
||||
|
||||
rtc_dev: rtc@10003000 {
|
||||
compatible = "ingenic,jz4725b-rtc", "ingenic,jz4740-rtc";
|
||||
reg = <0x10003000 0x40>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <6>;
|
||||
|
||||
clocks = <&cgu JZ4725B_CLK_RTC>;
|
||||
clock-names = "rtc";
|
||||
};
|
||||
|
||||
pinctrl: pinctrl@10010000 {
|
||||
compatible = "ingenic,jz4725b-pinctrl";
|
||||
reg = <0x10010000 0x400>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
gpa: gpio@0 {
|
||||
compatible = "ingenic,jz4725b-gpio";
|
||||
reg = <0>;
|
||||
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pinctrl 0 0 32>;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <16>;
|
||||
};
|
||||
|
||||
gpb: gpio@1 {
|
||||
compatible = "ingenic,jz4725b-gpio";
|
||||
reg = <1>;
|
||||
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pinctrl 0 32 32>;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <15>;
|
||||
};
|
||||
|
||||
gpc: gpio@2 {
|
||||
compatible = "ingenic,jz4725b-gpio";
|
||||
reg = <2>;
|
||||
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pinctrl 0 64 32>;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <14>;
|
||||
};
|
||||
|
||||
gpd: gpio@3 {
|
||||
compatible = "ingenic,jz4725b-gpio";
|
||||
reg = <3>;
|
||||
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pinctrl 0 96 32>;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <13>;
|
||||
};
|
||||
};
|
||||
|
||||
aic: audio-controller@10020000 {
|
||||
compatible = "ingenic,jz4725b-i2s", "ingenic,jz4740-i2s";
|
||||
reg = <0x10020000 0x38>;
|
||||
|
||||
#sound-dai-cells = <0>;
|
||||
|
||||
clocks = <&cgu JZ4725B_CLK_AIC>,
|
||||
<&cgu JZ4725B_CLK_I2S>,
|
||||
<&cgu JZ4725B_CLK_EXT>,
|
||||
<&cgu JZ4725B_CLK_PLL_HALF>;
|
||||
clock-names = "aic", "i2s", "ext", "pll half";
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <10>;
|
||||
|
||||
dmas = <&dmac 25 0xffffffff>, <&dmac 24 0xffffffff>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
|
||||
codec: audio-codec@100200a4 {
|
||||
compatible = "ingenic,jz4725b-codec";
|
||||
reg = <0x100200a4 0x8>;
|
||||
|
||||
#sound-dai-cells = <0>;
|
||||
|
||||
clocks = <&cgu JZ4725B_CLK_AIC>;
|
||||
clock-names = "aic";
|
||||
};
|
||||
|
||||
mmc0: mmc@10021000 {
|
||||
compatible = "ingenic,jz4725b-mmc";
|
||||
reg = <0x10021000 0x1000>;
|
||||
|
||||
clocks = <&cgu JZ4725B_CLK_MMC0>;
|
||||
clock-names = "mmc";
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <25>;
|
||||
|
||||
dmas = <&dmac 27 0xffffffff>, <&dmac 26 0xffffffff>;
|
||||
dma-names = "rx", "tx";
|
||||
|
||||
cap-sd-highspeed;
|
||||
cap-mmc-highspeed;
|
||||
cap-sdio-irq;
|
||||
};
|
||||
|
||||
mmc1: mmc@10022000 {
|
||||
compatible = "ingenic,jz4725b-mmc";
|
||||
reg = <0x10022000 0x1000>;
|
||||
|
||||
clocks = <&cgu JZ4725B_CLK_MMC1>;
|
||||
clock-names = "mmc";
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <24>;
|
||||
|
||||
dmas = <&dmac 31 0xffffffff>, <&dmac 30 0xffffffff>;
|
||||
dma-names = "rx", "tx";
|
||||
|
||||
cap-sd-highspeed;
|
||||
cap-mmc-highspeed;
|
||||
cap-sdio-irq;
|
||||
};
|
||||
|
||||
uart: serial@10030000 {
|
||||
compatible = "ingenic,jz4725b-uart", "ingenic,jz4740-uart";
|
||||
reg = <0x10030000 0x100>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <9>;
|
||||
|
||||
clocks = <&ext>, <&cgu JZ4725B_CLK_UART>;
|
||||
clock-names = "baud", "module";
|
||||
};
|
||||
|
||||
adc: adc@10070000 {
|
||||
compatible = "ingenic,jz4725b-adc";
|
||||
#io-channel-cells = <1>;
|
||||
|
||||
reg = <0x10070000 0x30>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x10070000 0x30>;
|
||||
|
||||
clocks = <&cgu JZ4725B_CLK_ADC>;
|
||||
clock-names = "adc";
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <18>;
|
||||
};
|
||||
|
||||
nemc: memory-controller@13010000 {
|
||||
compatible = "ingenic,jz4725b-nemc", "ingenic,jz4740-nemc";
|
||||
reg = <0x13010000 0x10000>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <1 0 0x18000000 0x4000000>, <2 0 0x14000000 0x4000000>,
|
||||
<3 0 0x0c000000 0x4000000>, <4 0 0x08000000 0x4000000>;
|
||||
|
||||
clocks = <&cgu JZ4725B_CLK_MCLK>;
|
||||
};
|
||||
|
||||
dmac: dma-controller@13020000 {
|
||||
compatible = "ingenic,jz4725b-dma";
|
||||
reg = <0x13020000 0xd8>, <0x13020300 0x14>;
|
||||
|
||||
#dma-cells = <2>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <29>;
|
||||
|
||||
clocks = <&cgu JZ4725B_CLK_DMA>;
|
||||
};
|
||||
|
||||
udc: usb@13040000 {
|
||||
compatible = "ingenic,jz4725b-musb", "ingenic,jz4740-musb";
|
||||
reg = <0x13040000 0x10000>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <27>;
|
||||
interrupt-names = "mc";
|
||||
|
||||
clocks = <&cgu JZ4725B_CLK_UDC>;
|
||||
clock-names = "udc";
|
||||
};
|
||||
|
||||
lcd: lcd-controller@13050000 {
|
||||
compatible = "ingenic,jz4725b-lcd";
|
||||
reg = <0x13050000 0x1000>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <31>;
|
||||
|
||||
clocks = <&cgu JZ4725B_CLK_LCD>;
|
||||
clock-names = "lcd_pclk";
|
||||
|
||||
lcd_ports: ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@8 {
|
||||
reg = <8>;
|
||||
|
||||
ipu_output: endpoint {
|
||||
remote-endpoint = <&ipu_input>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ipu: ipu@13080000 {
|
||||
compatible = "ingenic,jz4725b-ipu";
|
||||
reg = <0x13080000 0x64>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <30>;
|
||||
|
||||
clocks = <&cgu JZ4725B_CLK_IPU>;
|
||||
clock-names = "ipu";
|
||||
|
||||
port {
|
||||
ipu_input: endpoint {
|
||||
remote-endpoint = <&ipu_output>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
bch: ecc-controller@130d0000 {
|
||||
compatible = "ingenic,jz4725b-bch";
|
||||
reg = <0x130d0000 0x44>;
|
||||
|
||||
clocks = <&cgu JZ4725B_CLK_BCH>;
|
||||
};
|
||||
|
||||
rom: memory@1fc00000 {
|
||||
compatible = "mtd-rom";
|
||||
probe-type = "map_rom";
|
||||
reg = <0x1fc00000 0x2000>;
|
||||
|
||||
bank-width = <4>;
|
||||
device-width = <1>;
|
||||
};
|
||||
};
|
||||
@@ -16,6 +16,12 @@
|
||||
|
||||
/ {
|
||||
compatible = "qi,lb60", "ingenic,jz4740";
|
||||
model = "Ben Nanonote";
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x2000000>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart0;
|
||||
@@ -69,7 +75,7 @@
|
||||
"Speaker", "OUTL",
|
||||
"Speaker", "OUTR",
|
||||
"INL", "LOUT",
|
||||
"INL", "ROUT";
|
||||
"INR", "ROUT";
|
||||
|
||||
simple-audio-card,aux-devs = <&>;
|
||||
|
||||
|
||||
315
arch/mips/boot/dts/ingenic/rs90.dts
Normal file
315
arch/mips/boot/dts/ingenic/rs90.dts
Normal file
@@ -0,0 +1,315 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/dts-v1/;
|
||||
|
||||
#include "jz4725b.dtsi"
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/iio/adc/ingenic,adc.h>
|
||||
#include <dt-bindings/input/linux-event-codes.h>
|
||||
|
||||
/ {
|
||||
compatible = "ylm,rs90", "ingenic,jz4725b";
|
||||
model = "RS-90";
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x2000000>;
|
||||
};
|
||||
|
||||
vcc: regulator {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "vcc";
|
||||
regulaor-min-microvolt = <3300000>;
|
||||
regulaor-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
backlight: backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm 3 40000 0>;
|
||||
|
||||
brightness-levels = <0 16 32 48 64 80 112 144 192 255>;
|
||||
default-brightness-level = <8>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pins_pwm3>;
|
||||
|
||||
power-supply = <&vcc>;
|
||||
};
|
||||
|
||||
keys@0 {
|
||||
compatible = "gpio-keys";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
key@0 {
|
||||
label = "D-pad up";
|
||||
linux,code = <KEY_UP>;
|
||||
gpios = <&gpc 10 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
key@1 {
|
||||
label = "D-pad down";
|
||||
linux,code = <KEY_DOWN>;
|
||||
gpios = <&gpc 11 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
key@2 {
|
||||
label = "D-pad left";
|
||||
linux,code = <KEY_LEFT>;
|
||||
gpios = <&gpb 31 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
key@3 {
|
||||
label = "D-pad right";
|
||||
linux,code = <KEY_RIGHT>;
|
||||
gpios = <&gpd 21 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
key@4 {
|
||||
label = "Button A";
|
||||
linux,code = <KEY_LEFTCTRL>;
|
||||
gpios = <&gpc 31 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
key@5 {
|
||||
label = "Button B";
|
||||
linux,code = <KEY_LEFTALT>;
|
||||
gpios = <&gpc 30 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
key@6 {
|
||||
label = "Right shoulder button";
|
||||
linux,code = <KEY_BACKSPACE>;
|
||||
gpios = <&gpc 12 GPIO_ACTIVE_LOW>;
|
||||
debounce-interval = <10>;
|
||||
};
|
||||
|
||||
key@7 {
|
||||
label = "Start button";
|
||||
linux,code = <KEY_ENTER>;
|
||||
gpios = <&gpd 17 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
keys@1 {
|
||||
compatible = "adc-keys";
|
||||
io-channels = <&adc INGENIC_ADC_AUX>;
|
||||
io-channel-names = "buttons";
|
||||
keyup-threshold-microvolt = <1400000>;
|
||||
poll-interval = <30>;
|
||||
|
||||
key@0 {
|
||||
label = "Left shoulder button";
|
||||
linux,code = <KEY_TAB>;
|
||||
press-threshold-microvolt = <800000>;
|
||||
};
|
||||
|
||||
key@1 {
|
||||
label = "Select button";
|
||||
linux,code = <KEY_ESC>;
|
||||
press-threshold-microvolt = <1100000>;
|
||||
};
|
||||
};
|
||||
|
||||
amp: analog-amplifier {
|
||||
compatible = "simple-audio-amplifier";
|
||||
enable-gpios = <&gpc 15 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
VCC-supply = <&vcc>;
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "simple-audio-card";
|
||||
|
||||
simple-audio-card,name = "rs90-audio";
|
||||
simple-audio-card,format = "i2s";
|
||||
|
||||
simple-audio-card,widgets =
|
||||
"Speaker", "Speaker",
|
||||
"Headphone", "Headphones";
|
||||
simple-audio-card,routing =
|
||||
"INL", "LHPOUT",
|
||||
"INR", "RHPOUT",
|
||||
"Headphones", "LHPOUT",
|
||||
"Headphones", "RHPOUT",
|
||||
"Speaker", "OUTL",
|
||||
"Speaker", "OUTR";
|
||||
simple-audio-card,pin-switches = "Speaker";
|
||||
|
||||
simple-audio-card,hp-det-gpio = <&gpd 16 GPIO_ACTIVE_LOW>;
|
||||
simple-audio-card,aux-devs = <&>;
|
||||
|
||||
simple-audio-card,bitclock-master = <&dai_codec>;
|
||||
simple-audio-card,frame-master = <&dai_codec>;
|
||||
|
||||
dai_cpu: simple-audio-card,cpu {
|
||||
sound-dai = <&aic>;
|
||||
};
|
||||
|
||||
dai_codec: simple-audio-card,codec {
|
||||
sound-dai = <&codec>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
usb_phy: usb-phy {
|
||||
compatible = "usb-nop-xceiv";
|
||||
#phy-cells = <0>;
|
||||
|
||||
clocks = <&cgu JZ4725B_CLK_UDC_PHY>;
|
||||
clock-names = "main_clk";
|
||||
vcc-supply = <&vcc>;
|
||||
};
|
||||
|
||||
panel {
|
||||
compatible = "sharp,ls020b1dd01d";
|
||||
|
||||
backlight = <&backlight>;
|
||||
power-supply = <&vcc>;
|
||||
|
||||
port {
|
||||
panel_input: endpoint {
|
||||
remote-endpoint = <&panel_output>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ext {
|
||||
clock-frequency = <12000000>;
|
||||
};
|
||||
|
||||
&rtc_dev {
|
||||
system-power-controller;
|
||||
};
|
||||
|
||||
&udc {
|
||||
phys = <&usb_phy>;
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
pins_mmc1: mmc1 {
|
||||
function = "mmc1";
|
||||
groups = "mmc1-1bit";
|
||||
};
|
||||
|
||||
pins_nemc: nemc {
|
||||
function = "nand";
|
||||
groups = "nand-cs1", "nand-cle-ale", "nand-fre-fwe";
|
||||
};
|
||||
|
||||
pins_pwm3: pwm3 {
|
||||
function = "pwm3";
|
||||
groups = "pwm3";
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pins_lcd: lcd {
|
||||
function = "lcd";
|
||||
groups = "lcd-8bit", "lcd-16bit", "lcd-special";
|
||||
};
|
||||
};
|
||||
|
||||
&mmc0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
bus-width = <1>;
|
||||
max-frequency = <48000000>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pins_mmc1>;
|
||||
|
||||
cd-gpios = <&gpc 20 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&uart {
|
||||
/*
|
||||
* The pins for RX/TX are used for the right shoulder button and
|
||||
* backlight PWM.
|
||||
*/
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&nemc {
|
||||
nandc: nand-controller@1 {
|
||||
compatible = "ingenic,jz4725b-nand";
|
||||
reg = <1 0 0x4000000>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ecc-engine = <&bch>;
|
||||
|
||||
ingenic,nemc-tAS = <10>;
|
||||
ingenic,nemc-tAH = <5>;
|
||||
ingenic,nemc-tBP = <10>;
|
||||
ingenic,nemc-tAW = <15>;
|
||||
ingenic,nemc-tSTRV = <100>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pins_nemc>;
|
||||
|
||||
rb-gpios = <&gpc 27 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
nand@1 {
|
||||
reg = <1>;
|
||||
|
||||
nand-ecc-step-size = <512>;
|
||||
nand-ecc-strength = <8>;
|
||||
nand-ecc-mode = "hw";
|
||||
nand-is-boot-medium;
|
||||
nand-on-flash-bbt;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "bootloader";
|
||||
reg = <0x0 0x20000>;
|
||||
};
|
||||
|
||||
partition@20000 {
|
||||
label = "system";
|
||||
reg = <0x20000 0x0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cgu {
|
||||
/* Use 32kHz oscillator as the parent of the RTC clock */
|
||||
assigned-clocks = <&cgu JZ4725B_CLK_RTC>;
|
||||
assigned-clock-parents = <&cgu JZ4725B_CLK_OSC32K>;
|
||||
};
|
||||
|
||||
&tcu {
|
||||
/*
|
||||
* 750 kHz for the system timer and clocksource, and use RTC as the
|
||||
* parent for the watchdog clock.
|
||||
*/
|
||||
assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>, <&tcu TCU_CLK_WDT>;
|
||||
assigned-clock-parents = <0>, <0>, <&cgu JZ4725B_CLK_RTC>;
|
||||
assigned-clock-rates = <750000>, <750000>;
|
||||
};
|
||||
|
||||
&lcd {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pins_lcd>;
|
||||
};
|
||||
|
||||
&lcd_ports {
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
panel_output: endpoint {
|
||||
remote-endpoint = <&panel_input>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -48,9 +48,7 @@
|
||||
};
|
||||
|
||||
tcu: timer@10002000 {
|
||||
compatible = "ingenic,x1000-tcu",
|
||||
"ingenic,jz4770-tcu",
|
||||
"simple-mfd";
|
||||
compatible = "ingenic,x1000-tcu", "simple-mfd";
|
||||
reg = <0x10002000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
@@ -156,6 +154,45 @@
|
||||
};
|
||||
};
|
||||
|
||||
uart0: serial@10030000 {
|
||||
compatible = "ingenic,x1000-uart";
|
||||
reg = <0x10030000 0x100>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <51>;
|
||||
|
||||
clocks = <&exclk>, <&cgu X1000_CLK_UART0>;
|
||||
clock-names = "baud", "module";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@10031000 {
|
||||
compatible = "ingenic,x1000-uart";
|
||||
reg = <0x10031000 0x100>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <50>;
|
||||
|
||||
clocks = <&exclk>, <&cgu X1000_CLK_UART1>;
|
||||
clock-names = "baud", "module";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@10032000 {
|
||||
compatible = "ingenic,x1000-uart";
|
||||
reg = <0x10032000 0x100>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <49>;
|
||||
|
||||
clocks = <&exclk>, <&cgu X1000_CLK_UART2>;
|
||||
clock-names = "baud", "module";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c-controller@10050000 {
|
||||
compatible = "ingenic,x1000-i2c";
|
||||
reg = <0x10050000 0x1000>;
|
||||
@@ -198,45 +235,6 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart0: serial@10030000 {
|
||||
compatible = "ingenic,x1000-uart";
|
||||
reg = <0x10030000 0x100>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <51>;
|
||||
|
||||
clocks = <&exclk>, <&cgu X1000_CLK_UART0>;
|
||||
clock-names = "baud", "module";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@10031000 {
|
||||
compatible = "ingenic,x1000-uart";
|
||||
reg = <0x10031000 0x100>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <50>;
|
||||
|
||||
clocks = <&exclk>, <&cgu X1000_CLK_UART1>;
|
||||
clock-names = "baud", "module";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@10032000 {
|
||||
compatible = "ingenic,x1000-uart";
|
||||
reg = <0x10032000 0x100>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <49>;
|
||||
|
||||
clocks = <&exclk>, <&cgu X1000_CLK_UART2>;
|
||||
clock-names = "baud", "module";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pdma: dma-controller@13420000 {
|
||||
compatible = "ingenic,x1000-dma";
|
||||
reg = <0x13420000 0x400>, <0x13421000 0x40>;
|
||||
@@ -248,28 +246,6 @@
|
||||
clocks = <&cgu X1000_CLK_PDMA>;
|
||||
};
|
||||
|
||||
mac: ethernet@134b0000 {
|
||||
compatible = "ingenic,x1000-mac", "snps,dwmac";
|
||||
reg = <0x134b0000 0x2000>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <55>;
|
||||
interrupt-names = "macirq";
|
||||
|
||||
clocks = <&cgu X1000_CLK_MAC>;
|
||||
clock-names = "stmmaceth";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
mdio: mdio {
|
||||
compatible = "snps,dwmac-mdio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
msc0: mmc@13450000 {
|
||||
compatible = "ingenic,x1000-mmc";
|
||||
reg = <0x13450000 0x1000>;
|
||||
@@ -311,4 +287,26 @@
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mac: ethernet@134b0000 {
|
||||
compatible = "ingenic,x1000-mac", "snps,dwmac";
|
||||
reg = <0x134b0000 0x2000>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <55>;
|
||||
interrupt-names = "macirq";
|
||||
|
||||
clocks = <&cgu X1000_CLK_MAC>;
|
||||
clock-names = "stmmaceth";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
mdio: mdio {
|
||||
compatible = "snps,dwmac-mdio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
300
arch/mips/boot/dts/ingenic/x1830.dtsi
Normal file
300
arch/mips/boot/dts/ingenic/x1830.dtsi
Normal file
@@ -0,0 +1,300 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
#include <dt-bindings/clock/ingenic,tcu.h>
|
||||
#include <dt-bindings/clock/x1830-cgu.h>
|
||||
#include <dt-bindings/dma/x1830-dma.h>
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "ingenic,x1830";
|
||||
|
||||
cpuintc: interrupt-controller {
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
compatible = "mti,cpu-interrupt-controller";
|
||||
};
|
||||
|
||||
intc: interrupt-controller@10001000 {
|
||||
compatible = "ingenic,x1830-intc", "ingenic,jz4780-intc";
|
||||
reg = <0x10001000 0x50>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&cpuintc>;
|
||||
interrupts = <2>;
|
||||
};
|
||||
|
||||
exclk: ext {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
rtclk: rtc {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
cgu: x1830-cgu@10000000 {
|
||||
compatible = "ingenic,x1830-cgu";
|
||||
reg = <0x10000000 0x100>;
|
||||
|
||||
#clock-cells = <1>;
|
||||
|
||||
clocks = <&exclk>, <&rtclk>;
|
||||
clock-names = "ext", "rtc";
|
||||
};
|
||||
|
||||
tcu: timer@10002000 {
|
||||
compatible = "ingenic,x1830-tcu", "ingenic,x1000-tcu", "simple-mfd";
|
||||
reg = <0x10002000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x10002000 0x1000>;
|
||||
|
||||
#clock-cells = <1>;
|
||||
|
||||
clocks = <&cgu X1830_CLK_RTCLK
|
||||
&cgu X1830_CLK_EXCLK
|
||||
&cgu X1830_CLK_PCLK>;
|
||||
clock-names = "rtc", "ext", "pclk";
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <27 26 25>;
|
||||
|
||||
wdt: watchdog@0 {
|
||||
compatible = "ingenic,x1830-watchdog", "ingenic,jz4780-watchdog";
|
||||
reg = <0x0 0x10>;
|
||||
|
||||
clocks = <&tcu TCU_CLK_WDT>;
|
||||
clock-names = "wdt";
|
||||
};
|
||||
};
|
||||
|
||||
rtc: rtc@10003000 {
|
||||
compatible = "ingenic,x1830-rtc", "ingenic,jz4780-rtc";
|
||||
reg = <0x10003000 0x4c>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <32>;
|
||||
|
||||
clocks = <&cgu X1830_CLK_RTCLK>;
|
||||
clock-names = "rtc";
|
||||
};
|
||||
|
||||
pinctrl: pin-controller@10010000 {
|
||||
compatible = "ingenic,x1830-pinctrl";
|
||||
reg = <0x10010000 0x800>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
gpa: gpio@0 {
|
||||
compatible = "ingenic,x1830-gpio";
|
||||
reg = <0>;
|
||||
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pinctrl 0 0 32>;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <17>;
|
||||
};
|
||||
|
||||
gpb: gpio@1 {
|
||||
compatible = "ingenic,x1830-gpio";
|
||||
reg = <1>;
|
||||
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pinctrl 0 32 32>;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <16>;
|
||||
};
|
||||
|
||||
gpc: gpio@2 {
|
||||
compatible = "ingenic,x1830-gpio";
|
||||
reg = <2>;
|
||||
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pinctrl 0 64 32>;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <15>;
|
||||
};
|
||||
|
||||
gpd: gpio@3 {
|
||||
compatible = "ingenic,x1830-gpio";
|
||||
reg = <3>;
|
||||
|
||||
gpio-controller;
|
||||
gpio-ranges = <&pinctrl 0 96 32>;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <14>;
|
||||
};
|
||||
};
|
||||
|
||||
uart0: serial@10030000 {
|
||||
compatible = "ingenic,x1830-uart", "ingenic,x1000-uart";
|
||||
reg = <0x10030000 0x100>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <51>;
|
||||
|
||||
clocks = <&exclk>, <&cgu X1830_CLK_UART0>;
|
||||
clock-names = "baud", "module";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@10031000 {
|
||||
compatible = "ingenic,x1830-uart", "ingenic,x1000-uart";
|
||||
reg = <0x10031000 0x100>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <50>;
|
||||
|
||||
clocks = <&exclk>, <&cgu X1830_CLK_UART1>;
|
||||
clock-names = "baud", "module";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c-controller@10050000 {
|
||||
compatible = "ingenic,x1830-i2c", "ingenic,x1000-i2c";
|
||||
reg = <0x10050000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <60>;
|
||||
|
||||
clocks = <&cgu X1830_CLK_SMB0>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c-controller@10051000 {
|
||||
compatible = "ingenic,x1830-i2c", "ingenic,x1000-i2c";
|
||||
reg = <0x10051000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <59>;
|
||||
|
||||
clocks = <&cgu X1830_CLK_SMB1>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c-controller@10052000 {
|
||||
compatible = "ingenic,x1830-i2c", "ingenic,x1000-i2c";
|
||||
reg = <0x10052000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <58>;
|
||||
|
||||
clocks = <&cgu X1830_CLK_SMB2>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pdma: dma-controller@13420000 {
|
||||
compatible = "ingenic,x1830-dma";
|
||||
reg = <0x13420000 0x400
|
||||
0x13421000 0x40>;
|
||||
#dma-cells = <2>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <10>;
|
||||
|
||||
clocks = <&cgu X1830_CLK_PDMA>;
|
||||
};
|
||||
|
||||
msc0: mmc@13450000 {
|
||||
compatible = "ingenic,x1830-mmc", "ingenic,x1000-mmc";
|
||||
reg = <0x13450000 0x1000>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <37>;
|
||||
|
||||
clocks = <&cgu X1830_CLK_MSC0>;
|
||||
clock-names = "mmc";
|
||||
|
||||
cap-sd-highspeed;
|
||||
cap-mmc-highspeed;
|
||||
cap-sdio-irq;
|
||||
|
||||
dmas = <&pdma X1830_DMA_MSC0_RX 0xffffffff>,
|
||||
<&pdma X1830_DMA_MSC0_TX 0xffffffff>;
|
||||
dma-names = "rx", "tx";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
msc1: mmc@13460000 {
|
||||
compatible = "ingenic,x1830-mmc", "ingenic,x1000-mmc";
|
||||
reg = <0x13460000 0x1000>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <36>;
|
||||
|
||||
clocks = <&cgu X1830_CLK_MSC1>;
|
||||
clock-names = "mmc";
|
||||
|
||||
cap-sd-highspeed;
|
||||
cap-mmc-highspeed;
|
||||
cap-sdio-irq;
|
||||
|
||||
dmas = <&pdma X1830_DMA_MSC1_RX 0xffffffff>,
|
||||
<&pdma X1830_DMA_MSC1_TX 0xffffffff>;
|
||||
dma-names = "rx", "tx";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mac: ethernet@134b0000 {
|
||||
compatible = "ingenic,x1830-mac", "snps,dwmac";
|
||||
reg = <0x134b0000 0x2000>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <55>;
|
||||
interrupt-names = "macirq";
|
||||
|
||||
clocks = <&cgu X1830_CLK_MAC>;
|
||||
clock-names = "stmmaceth";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
mdio: mdio {
|
||||
compatible = "snps,dwmac-mdio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -1,4 +1,8 @@
|
||||
# SPDX_License_Identifier: GPL_2.0
|
||||
dtb-$(CONFIG_MACH_LOONGSON64) += loongson3_4core_rs780e.dtb loongson3_8core_rs780e.dtb
|
||||
dtb-$(CONFIG_MACH_LOONGSON64) += loongson64c_4core_ls7a.dtb
|
||||
dtb-$(CONFIG_MACH_LOONGSON64) += loongson64c_4core_rs780e.dtb
|
||||
dtb-$(CONFIG_MACH_LOONGSON64) += loongson64c_8core_rs780e.dtb
|
||||
dtb-$(CONFIG_MACH_LOONGSON64) += loongson64g_4core_ls7a.dtb
|
||||
dtb-$(CONFIG_MACH_LOONGSON64) += loongson64v_4core_virtio.dtb
|
||||
|
||||
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
|
||||
|
||||
37
arch/mips/boot/dts/loongson/loongson64c_4core_ls7a.dts
Normal file
37
arch/mips/boot/dts/loongson/loongson64c_4core_ls7a.dts
Normal file
@@ -0,0 +1,37 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "loongson64c-package.dtsi"
|
||||
#include "ls7a-pch.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "loongson,loongson64c-4core-ls7a";
|
||||
};
|
||||
|
||||
&package0 {
|
||||
htvec: interrupt-controller@efdfb000080 {
|
||||
compatible = "loongson,htvec-1.0";
|
||||
reg = <0xefd 0xfb000080 0x40>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&liointc>;
|
||||
interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<25 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<26 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<27 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
&pch {
|
||||
msi: msi-controller@2ff00000 {
|
||||
compatible = "loongson,pch-msi-1.0";
|
||||
reg = <0 0x2ff00000 0 0x8>;
|
||||
interrupt-controller;
|
||||
msi-controller;
|
||||
loongson,msi-base-vec = <64>;
|
||||
loongson,msi-num-vecs = <64>;
|
||||
interrupt-parent = <&htvec>;
|
||||
};
|
||||
};
|
||||
@@ -2,11 +2,11 @@
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "loongson3-package.dtsi"
|
||||
#include "loongson64c-package.dtsi"
|
||||
#include "rs780e-pch.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "loongson,loongson3-4core-rs780e";
|
||||
compatible = "loongson,loongson64c-4core-rs780e";
|
||||
};
|
||||
|
||||
&package0 {
|
||||
@@ -2,11 +2,11 @@
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "loongson3-package.dtsi"
|
||||
#include "loongson64c-package.dtsi"
|
||||
#include "rs780e-pch.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "loongson,loongson3-8core-rs780e";
|
||||
compatible = "loongson,loongson64c-8core-rs780e";
|
||||
};
|
||||
|
||||
&package0 {
|
||||
61
arch/mips/boot/dts/loongson/loongson64g-package.dtsi
Normal file
61
arch/mips/boot/dts/loongson/loongson64g-package.dtsi
Normal file
@@ -0,0 +1,61 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
cpuintc: interrupt-controller {
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
compatible = "mti,cpu-interrupt-controller";
|
||||
};
|
||||
|
||||
package0: bus@1fe00000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x1fe00000 0 0x1fe00000 0x100000
|
||||
0 0x3ff00000 0 0x3ff00000 0x100000
|
||||
0xefd 0xfb000000 0xefd 0xfb000000 0x10000000>;
|
||||
|
||||
liointc: interrupt-controller@3ff01400 {
|
||||
compatible = "loongson,liointc-1.0";
|
||||
reg = <0 0x3ff01400 0x64>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
interrupt-parent = <&cpuintc>;
|
||||
interrupts = <2>, <3>;
|
||||
interrupt-names = "int0", "int1";
|
||||
|
||||
loongson,parent_int_map = <0x00ffffff>, /* int0 */
|
||||
<0xff000000>, /* int1 */
|
||||
<0x00000000>, /* int2 */
|
||||
<0x00000000>; /* int3 */
|
||||
|
||||
};
|
||||
|
||||
cpu_uart0: serial@1fe001e0 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0 0x1fe00100 0x10>;
|
||||
clock-frequency = <100000000>;
|
||||
interrupt-parent = <&liointc>;
|
||||
interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
no-loopback-test;
|
||||
};
|
||||
|
||||
cpu_uart1: serial@1fe001e8 {
|
||||
status = "disabled";
|
||||
compatible = "ns16550a";
|
||||
reg = <0 0x1fe00110 0x10>;
|
||||
clock-frequency = <100000000>;
|
||||
interrupts = <15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&liointc>;
|
||||
no-loopback-test;
|
||||
};
|
||||
};
|
||||
};
|
||||
41
arch/mips/boot/dts/loongson/loongson64g_4core_ls7a.dts
Normal file
41
arch/mips/boot/dts/loongson/loongson64g_4core_ls7a.dts
Normal file
@@ -0,0 +1,41 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "loongson64g-package.dtsi"
|
||||
#include "ls7a-pch.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "loongson,loongson64g-4core-ls7a";
|
||||
};
|
||||
|
||||
&package0 {
|
||||
htvec: interrupt-controller@efdfb000080 {
|
||||
compatible = "loongson,htvec-1.0";
|
||||
reg = <0xefd 0xfb000080 0x40>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&liointc>;
|
||||
interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<25 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<26 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<27 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<28 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<29 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<30 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<31 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
&pch {
|
||||
msi: msi-controller@2ff00000 {
|
||||
compatible = "loongson,pch-msi-1.0";
|
||||
reg = <0 0x2ff00000 0 0x8>;
|
||||
interrupt-controller;
|
||||
msi-controller;
|
||||
loongson,msi-base-vec = <64>;
|
||||
loongson,msi-num-vecs = <192>;
|
||||
interrupt-parent = <&htvec>;
|
||||
};
|
||||
};
|
||||
102
arch/mips/boot/dts/loongson/loongson64v_4core_virtio.dts
Normal file
102
arch/mips/boot/dts/loongson/loongson64v_4core_virtio.dts
Normal file
@@ -0,0 +1,102 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/dts-v1/;
|
||||
/ {
|
||||
compatible = "loongson,loongson64v-4core-virtio";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
cpuintc: interrupt-controller {
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
compatible = "mti,cpu-interrupt-controller";
|
||||
};
|
||||
|
||||
package0: bus@1fe00000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x1fe00000 0 0x1fe00000 0x100000
|
||||
0 0x3ff00000 0 0x3ff00000 0x100000
|
||||
0xefd 0xfb000000 0xefd 0xfb000000 0x10000000>;
|
||||
|
||||
liointc: interrupt-controller@3ff01400 {
|
||||
compatible = "loongson,liointc-1.0";
|
||||
reg = <0 0x3ff01400 0x64>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
interrupt-parent = <&cpuintc>;
|
||||
interrupts = <2>, <3>;
|
||||
interrupt-names = "int0", "int1";
|
||||
|
||||
loongson,parent_int_map = <0x00000001>, /* int0 */
|
||||
<0xfffffffe>, /* int1 */
|
||||
<0x00000000>, /* int2 */
|
||||
<0x00000000>; /* int3 */
|
||||
|
||||
};
|
||||
|
||||
cpu_uart0: serial@1fe001e0 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0 0x1fe001e0 0x8>;
|
||||
clock-frequency = <33000000>;
|
||||
interrupt-parent = <&liointc>;
|
||||
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
|
||||
no-loopback-test;
|
||||
};
|
||||
};
|
||||
|
||||
bus@10000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0 0x10000000 0 0x10000000 0 0x10000000 /* PIO & CONF & APB */
|
||||
0 0x40000000 0 0x40000000 0 0x40000000>; /* PCI MEM */
|
||||
|
||||
rtc0: rtc@10081000 {
|
||||
compatible = "google,goldfish-rtc";
|
||||
reg = <0 0x10081000 0 0x1000>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&liointc>;
|
||||
};
|
||||
|
||||
pci@1a000000 {
|
||||
compatible = "pci-host-ecam-generic";
|
||||
device_type = "pci";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
bus-range = <0x0 0x1f>;
|
||||
reg = <0 0x1a000000 0 0x02000000>;
|
||||
|
||||
ranges = <0x01000000 0x0 0x00004000 0x0 0x18004000 0x0 0x0000c000>,
|
||||
<0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>;
|
||||
|
||||
interrupt-map = <
|
||||
0x0000 0x0 0x0 0x1 &liointc 0x2 IRQ_TYPE_LEVEL_HIGH
|
||||
0x0800 0x0 0x0 0x1 &liointc 0x3 IRQ_TYPE_LEVEL_HIGH
|
||||
0x1000 0x0 0x0 0x1 &liointc 0x4 IRQ_TYPE_LEVEL_HIGH
|
||||
0x1800 0x0 0x0 0x1 &liointc 0x5 IRQ_TYPE_LEVEL_HIGH
|
||||
>;
|
||||
|
||||
interrupt-map-mask = <0x1800 0x0 0x0 0x7>;
|
||||
};
|
||||
|
||||
isa {
|
||||
compatible = "isa";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <1 0 0 0x18000000 0x4000>;
|
||||
};
|
||||
};
|
||||
|
||||
hypervisor {
|
||||
compatible = "linux,kvm";
|
||||
};
|
||||
};
|
||||
378
arch/mips/boot/dts/loongson/ls7a-pch.dtsi
Normal file
378
arch/mips/boot/dts/loongson/ls7a-pch.dtsi
Normal file
@@ -0,0 +1,378 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
/ {
|
||||
pch: bus@10000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0 0x10000000 0 0x10000000 0 0x10000000 /* PIO & CONF & APB */
|
||||
0 0x20000000 0 0x20000000 0 0x10000000
|
||||
0 0x40000000 0 0x40000000 0 0x40000000 /* PCI MEM */
|
||||
0xe00 0x00000000 0xe00 0x00000000 0x100 0x0000000>;
|
||||
|
||||
pic: interrupt-controller@10000000 {
|
||||
compatible = "loongson,pch-pic-1.0";
|
||||
reg = <0 0x10000000 0 0x400>;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&htvec>;
|
||||
loongson,pic-base-vec = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
pci@1a000000 {
|
||||
compatible = "loongson,ls7a-pci";
|
||||
device_type = "pci";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
msi-parent = <&msi>;
|
||||
|
||||
reg = <0 0x1a000000 0 0x02000000>,
|
||||
<0xefe 0x00000000 0 0x20000000>;
|
||||
|
||||
ranges = <0x01000000 0x0 0x00020000 0x0 0x18020000 0x0 0x00020000>,
|
||||
<0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>;
|
||||
|
||||
ohci@4,0 {
|
||||
compatible = "pci0014,7a24.0",
|
||||
"pci0014,7a24",
|
||||
"pciclass0c0310",
|
||||
"pciclass0c03";
|
||||
|
||||
reg = <0x2000 0x0 0x0 0x0 0x0>;
|
||||
interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&pic>;
|
||||
};
|
||||
|
||||
ehci@4,1 {
|
||||
compatible = "pci0014,7a14.0",
|
||||
"pci0014,7a14",
|
||||
"pciclass0c0320",
|
||||
"pciclass0c03";
|
||||
|
||||
reg = <0x2100 0x0 0x0 0x0 0x0>;
|
||||
interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&pic>;
|
||||
};
|
||||
|
||||
ohci@5,0 {
|
||||
compatible = "pci0014,7a24.0",
|
||||
"pci0014,7a24",
|
||||
"pciclass0c0310",
|
||||
"pciclass0c03";
|
||||
|
||||
reg = <0x2800 0x0 0x0 0x0 0x0>;
|
||||
interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&pic>;
|
||||
};
|
||||
|
||||
ehci@5,1 {
|
||||
compatible = "pci0014,7a14.0",
|
||||
"pci0014,7a14",
|
||||
"pciclass0c0320",
|
||||
"pciclass0c03";
|
||||
|
||||
reg = <0x2900 0x0 0x0 0x0 0x0>;
|
||||
interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&pic>;
|
||||
};
|
||||
|
||||
sata@8,0 {
|
||||
compatible = "pci0014,7a08.0",
|
||||
"pci0014,7a08",
|
||||
"pciclass010601",
|
||||
"pciclass0106";
|
||||
|
||||
reg = <0x4000 0x0 0x0 0x0 0x0>;
|
||||
interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&pic>;
|
||||
};
|
||||
|
||||
sata@8,1 {
|
||||
compatible = "pci0014,7a08.0",
|
||||
"pci0014,7a08",
|
||||
"pciclass010601",
|
||||
"pciclass0106";
|
||||
|
||||
reg = <0x4100 0x0 0x0 0x0 0x0>;
|
||||
interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&pic>;
|
||||
};
|
||||
|
||||
sata@8,2 {
|
||||
compatible = "pci0014,7a08.0",
|
||||
"pci0014,7a08",
|
||||
"pciclass010601",
|
||||
"pciclass0106";
|
||||
|
||||
reg = <0x4200 0x0 0x0 0x0 0x0>;
|
||||
interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&pic>;
|
||||
};
|
||||
|
||||
gpu@6,0 {
|
||||
compatible = "pci0014,7a15.0",
|
||||
"pci0014,7a15",
|
||||
"pciclass030200",
|
||||
"pciclass0302";
|
||||
|
||||
reg = <0x3000 0x0 0x0 0x0 0x0>;
|
||||
interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&pic>;
|
||||
};
|
||||
|
||||
dc@6,1 {
|
||||
compatible = "pci0014,7a06.0",
|
||||
"pci0014,7a06",
|
||||
"pciclass030000",
|
||||
"pciclass0300";
|
||||
|
||||
reg = <0x3100 0x0 0x0 0x0 0x0>;
|
||||
interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&pic>;
|
||||
};
|
||||
|
||||
hda@7,0 {
|
||||
compatible = "pci0014,7a07.0",
|
||||
"pci0014,7a07",
|
||||
"pciclass040300",
|
||||
"pciclass0403";
|
||||
|
||||
reg = <0x3800 0x0 0x0 0x0 0x0>;
|
||||
interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&pic>;
|
||||
};
|
||||
|
||||
gmac@3,0 {
|
||||
compatible = "pci0014,7a03.0",
|
||||
"pci0014,7a03",
|
||||
"pciclass020000",
|
||||
"pciclass0200";
|
||||
|
||||
reg = <0x1800 0x0 0x0 0x0 0x0>;
|
||||
interrupts = <12 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "macirq", "eth_lpi";
|
||||
interrupt-parent = <&pic>;
|
||||
phy-mode = "rgmii";
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,dwmac-mdio";
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gmac@3,1 {
|
||||
compatible = "pci0014,7a03.0",
|
||||
"pci0014,7a03",
|
||||
"pciclass020000",
|
||||
"pciclass0200";
|
||||
|
||||
reg = <0x1900 0x0 0x0 0x0 0x0>;
|
||||
interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "macirq", "eth_lpi";
|
||||
interrupt-parent = <&pic>;
|
||||
phy-mode = "rgmii";
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,dwmac-mdio";
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pci_bridge@9,0 {
|
||||
compatible = "pci0014,7a19.1",
|
||||
"pci0014,7a19",
|
||||
"pciclass060400",
|
||||
"pciclass0604";
|
||||
|
||||
reg = <0x4800 0x0 0x0 0x0 0x0>;
|
||||
interrupts = <32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&pic>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &pic 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pci_bridge@a,0 {
|
||||
compatible = "pci0014,7a09.1",
|
||||
"pci0014,7a09",
|
||||
"pciclass060400",
|
||||
"pciclass0604";
|
||||
|
||||
reg = <0x5000 0x0 0x0 0x0 0x0>;
|
||||
interrupts = <33 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&pic>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &pic 33 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pci_bridge@b,0 {
|
||||
compatible = "pci0014,7a09.1",
|
||||
"pci0014,7a09",
|
||||
"pciclass060400",
|
||||
"pciclass0604";
|
||||
|
||||
reg = <0x5800 0x0 0x0 0x0 0x0>;
|
||||
interrupts = <34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&pic>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &pic 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pci_bridge@c,0 {
|
||||
compatible = "pci0014,7a09.1",
|
||||
"pci0014,7a09",
|
||||
"pciclass060400",
|
||||
"pciclass0604";
|
||||
|
||||
reg = <0x6000 0x0 0x0 0x0 0x0>;
|
||||
interrupts = <35 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&pic>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &pic 35 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pci_bridge@d,0 {
|
||||
compatible = "pci0014,7a19.1",
|
||||
"pci0014,7a19",
|
||||
"pciclass060400",
|
||||
"pciclass0604";
|
||||
|
||||
reg = <0x6800 0x0 0x0 0x0 0x0>;
|
||||
interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&pic>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &pic 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pci_bridge@e,0 {
|
||||
compatible = "pci0014,7a09.1",
|
||||
"pci0014,7a09",
|
||||
"pciclass060400",
|
||||
"pciclass0604";
|
||||
|
||||
reg = <0x7000 0x0 0x0 0x0 0x0>;
|
||||
interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&pic>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &pic 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pci_bridge@f,0 {
|
||||
compatible = "pci0014,7a29.1",
|
||||
"pci0014,7a29",
|
||||
"pciclass060400",
|
||||
"pciclass0604";
|
||||
|
||||
reg = <0x7800 0x0 0x0 0x0 0x0>;
|
||||
interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&pic>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &pic 40 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pci_bridge@10,0 {
|
||||
compatible = "pci0014,7a19.1",
|
||||
"pci0014,7a19",
|
||||
"pciclass060400",
|
||||
"pciclass0604";
|
||||
|
||||
reg = <0x8000 0x0 0x0 0x0 0x0>;
|
||||
interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&pic>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &pic 41 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pci_bridge@11,0 {
|
||||
compatible = "pci0014,7a29.1",
|
||||
"pci0014,7a29",
|
||||
"pciclass060400",
|
||||
"pciclass0604";
|
||||
|
||||
reg = <0x8800 0x0 0x0 0x0 0x0>;
|
||||
interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&pic>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &pic 42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pci_bridge@12,0 {
|
||||
compatible = "pci0014,7a19.1",
|
||||
"pci0014,7a19",
|
||||
"pciclass060400",
|
||||
"pciclass0604";
|
||||
|
||||
reg = <0x9000 0x0 0x0 0x0 0x0>;
|
||||
interrupts = <43 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&pic>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &pic 43 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pci_bridge@13,0 {
|
||||
compatible = "pci0014,7a29.1",
|
||||
"pci0014,7a29",
|
||||
"pciclass060400",
|
||||
"pciclass0604";
|
||||
|
||||
reg = <0x9800 0x0 0x0 0x0 0x0>;
|
||||
interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&pic>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &pic 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pci_bridge@14,0 {
|
||||
compatible = "pci0014,7a19.1",
|
||||
"pci0014,7a19",
|
||||
"pciclass060400",
|
||||
"pciclass0604";
|
||||
|
||||
reg = <0xa000 0x0 0x0 0x0 0x0>;
|
||||
interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&pic>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &pic 39 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
isa {
|
||||
compatible = "isa";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <1 0 0 0x18000000 0x20000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -17,7 +17,7 @@
|
||||
|
||||
reg = <0 0x1a000000 0 0x02000000>;
|
||||
|
||||
ranges = <0x01000000 0 0x00004000 0 0x18004000 0 0x00004000>,
|
||||
ranges = <0x01000000 0 0x00004000 0 0x18004000 0 0x0000c000>,
|
||||
<0x02000000 0 0x40000000 0 0x40000000 0 0x40000000>;
|
||||
};
|
||||
|
||||
@@ -25,7 +25,7 @@
|
||||
compatible = "isa";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <1 0 0 0 0x1000>;
|
||||
ranges = <1 0 0 0x18000000 0x4000>;
|
||||
|
||||
rtc0: rtc@70 {
|
||||
compatible = "motorola,mc146818";
|
||||
|
||||
Reference in New Issue
Block a user