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Merge tag 'mips_5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

Browse Source 
Pull MIPS upates from Thomas Bogendoerfer:

 - improvements for Loongson64

 - extended ingenic support

 - removal of not maintained paravirt system type

 - cleanups and fixes

* tag 'mips_5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (81 commits)
  MIPS: SGI-IP27: always enable NUMA in Kconfig
  MAINTAINERS: Update KVM/MIPS maintainers
  MIPS: Update default config file for Loongson-3
  MIPS: KVM: Add kvm guest support for Loongson-3
  dt-bindings: mips: Document Loongson kvm guest board
  MIPS: handle Loongson-specific GSExc exception
  MIPS: add definitions for Loongson-specific CP0.Diag1 register
  MIPS: only register FTLBPar exception handler for supported models
  MIPS: ingenic: Hardcode mem size for qi,lb60 board
  MIPS: DTS: ingenic/qi,lb60: Add model and memory node
  MIPS: ingenic: Use fw_passed_dtb even if CONFIG_BUILTIN_DTB
  MIPS: head.S: Init fw_passed_dtb to builtin DTB
  of: address: Fix parser address/size cells initialization
  of_address: Guard of_bus_pci_get_flags with CONFIG_PCI
  MIPS: DTS: Fix number of msi vectors for Loongson64G
  MIPS: Loongson64: Add ISA node for LS7A PCH
  MIPS: Loongson64: DTS: Fix ISA and PCI I/O ranges for RS780E PCH
  MIPS: Loongson64: Enlarge IO_SPACE_LIMIT
  MIPS: Loongson64: Process ISA Node in DeviceTree
  of_address: Add bus type match for pci ranges parser
  ...
This commit is contained in:
Linus Torvalds
2020-08-06 10:54:07 -07:00
parent 40ddad1913 6c86a3029c
commit b62e419707
108 changed files with 3139 additions and 1608 deletions
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35
Documentation/devicetree/bindings/bus/mti,mips-cdmm.yaml Normal file
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@@ -0,0 +1,35 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/bus/mti,mips-cdmm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MIPS Common Device Memory Map
description: |
Defines a location of the MIPS Common Device Memory Map registers.
maintainers:
- James Hogan <jhogan@kernel.org>
properties:
compatible:
const: mti,mips-cdmm
reg:
description: |
Base address and size of an unoccupied memory region, which will be
used to map the MIPS CDMM registers block.
maxItems: 1
required:
- compatible
- reg
examples:
- |
cdmm@1bde8000 {
compatible = "mti,mips-cdmm";
reg = <0x1bde8000 0x8000>;
};
...

67
Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
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@@ -1,67 +0,0 @@
MIPS Global Interrupt Controller (GIC)
The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
It also supports local (per-processor) interrupts and software-generated
interrupts which can be used as IPIs. The GIC also includes a free-running
global timer, per-CPU count/compare timers, and a watchdog.
Required properties:
- compatible : Should be "mti,gic".
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
interrupt specifier. Should be 3.
- The first cell is the type of interrupt, local or shared.
See <include/dt-bindings/interrupt-controller/mips-gic.h>.
- The second cell is the GIC interrupt number.
- The third cell encodes the interrupt flags.
See <include/dt-bindings/interrupt-controller/irq.h> for a list of valid
flags.
Optional properties:
- reg : Base address and length of the GIC registers. If not present,
the base address reported by the hardware GCR_GIC_BASE will be used.
- mti,reserved-cpu-vectors : Specifies the list of CPU interrupt vectors
to which the GIC may not route interrupts. Valid values are 2 - 7.
This property is ignored if the CPU is started in EIC mode.
- mti,reserved-ipi-vectors : Specifies the range of GIC interrupts that are
reserved for IPIs.
It accepts 2 values, the 1st is the starting interrupt and the 2nd is the size
of the reserved range.
If not specified, the driver will allocate the last 2 * number of VPEs in the
system.
Required properties for timer sub-node:
- compatible : Should be "mti,gic-timer".
- interrupts : Interrupt for the GIC local timer.
Optional properties for timer sub-node:
- clocks : GIC timer operating clock.
- clock-frequency : Clock frequency at which the GIC timers operate.
Note that one of clocks or clock-frequency must be specified.
Example:
gic: interrupt-controller@1bdc0000 {
compatible = "mti,gic";
reg = <0x1bdc0000 0x20000>;
interrupt-controller;
#interrupt-cells = <3>;
mti,reserved-cpu-vectors = <7>;
mti,reserved-ipi-vectors = <40 8>;
timer {
compatible = "mti,gic-timer";
interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
clock-frequency = <50000000>;
};
};
uart@18101400 {
...
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
...
};

148
Documentation/devicetree/bindings/interrupt-controller/mti,gic.yaml Normal file
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@@ -0,0 +1,148 @@
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MIPS Global Interrupt Controller
maintainers:
- Paul Burton <paulburton@kernel.org>
- Thomas Bogendoerfer <tsbogend@alpha.franken.de>
description: |
The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
It also supports local (per-processor) interrupts and software-generated
interrupts which can be used as IPIs. The GIC also includes a free-running
global timer, per-CPU count/compare timers, and a watchdog.
properties:
compatible:
const: mti,gic
"#interrupt-cells":
const: 3
description: |
The 1st cell is the type of interrupt: local or shared defined in the
file 'dt-bindings/interrupt-controller/mips-gic.h'. The 2nd cell is the
GIC interrupt number. The 3d cell encodes the interrupt flags setting up
the IRQ trigger modes, which are defined in the file
'dt-bindings/interrupt-controller/irq.h'.
reg:
description: |
Base address and length of the GIC registers space. If not present,
the base address reported by the hardware GCR_GIC_BASE will be used.
maxItems: 1
interrupt-controller: true
mti,reserved-cpu-vectors:
description: |
Specifies the list of CPU interrupt vectors to which the GIC may not
route interrupts. This property is ignored if the CPU is started in EIC
mode.
allOf:
- $ref: /schemas/types.yaml#definitions/uint32-array
- minItems: 1
maxItems: 6
uniqueItems: true
items:
minimum: 2
maximum: 7
mti,reserved-ipi-vectors:
description: |
Specifies the range of GIC interrupts that are reserved for IPIs.
It accepts two values: the 1st is the starting interrupt and the 2nd is
the size of the reserved range. If not specified, the driver will
allocate the last (2 * number of VPEs in the system).
allOf:
- $ref: /schemas/types.yaml#definitions/uint32-array
- items:
- minimum: 0
maximum: 254
- minimum: 2
maximum: 254
timer:
type: object
description: |
MIPS GIC includes a free-running global timer, per-CPU count/compare
timers, and a watchdog. Currently only the GIC Timer is supported.
properties:
compatible:
const: mti,gic-timer
interrupts:
description: |
Interrupt for the GIC local timer, so normally it's suppose to be of
<GIC_LOCAL X IRQ_TYPE_NONE> format.
maxItems: 1
clocks:
maxItems: 1
clock-frequency: true
required:
- compatible
- interrupts
oneOf:
- required:
- clocks
- required:
- clock-frequency
additionalProperties: false
unevaluatedProperties: false
required:
- compatible
- "#interrupt-cells"
- interrupt-controller
examples:
- |
#include <dt-bindings/interrupt-controller/mips-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
interrupt-controller@1bdc0000 {
compatible = "mti,gic";
reg = <0x1bdc0000 0x20000>;
interrupt-controller;
#interrupt-cells = <3>;
mti,reserved-cpu-vectors = <7>;
mti,reserved-ipi-vectors = <40 8>;
timer {
compatible = "mti,gic-timer";
interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
clock-frequency = <50000000>;
};
};
- |
#include <dt-bindings/interrupt-controller/mips-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
interrupt-controller@1bdc0000 {
compatible = "mti,gic";
reg = <0x1bdc0000 0x20000>;
interrupt-controller;
#interrupt-cells = <3>;
timer {
compatible = "mti,gic-timer";
interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
clocks = <&cpu_pll>;
};
};
- |
interrupt-controller {
compatible = "mti,gic";
interrupt-controller;
#interrupt-cells = <3>;
};
...

17
Documentation/devicetree/bindings/mips/ingenic/devices.yaml
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@@ -8,7 +8,8 @@ title: Ingenic XBurst based Platforms Device Tree Bindings
maintainers:
- 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
description: |
description:
Devices with a Ingenic XBurst CPU shall have the following properties.
properties:
@@ -22,6 +23,11 @@ properties:
- const: qi,lb60
- const: ingenic,jz4740
- description: YLM RetroMini RS-90
items:
- const: ylm,rs90
- const: ingenic,jz4725b
- description: Game Consoles Worldwide GCW Zero
items:
- const: gcw,zero
@@ -32,8 +38,13 @@ properties:
- const: img,ci20
- const: ingenic,jz4780
- description: YSH & ATIL General Board CU Neo
- description: YSH & ATIL General Board, CU1000 Module with Neo Backplane
items:
- const: yna,cu1000-neo
- const: ingenic,x1000
- const: ingenic,x1000e
- description: YSH & ATIL General Board, CU1830 Module with Neo Backplane
items:
- const: yna,cu1830-neo
- const: ingenic,x1830
...

67
Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml Normal file
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@@ -0,0 +1,67 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mips/ingenic/ingenic,cpu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Bindings for Ingenic XBurst family CPUs
maintainers:
- 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
description:
Ingenic XBurst family CPUs shall have the following properties.
properties:
compatible:
oneOf:
- description: Ingenic XBurst®1 CPU Cores
enum:
- ingenic,xburst-mxu1.0
- ingenic,xburst-fpu1.0-mxu1.1
- ingenic,xburst-fpu2.0-mxu2.0
- description: Ingenic XBurst®2 CPU Cores
enum:
- ingenic,xburst2-fpu2.1-mxu2.1-smt
reg:
maxItems: 1
clocks:
maxItems: 1
required:
- device_type
- compatible
- reg
- clocks
examples:
- |
#include <dt-bindings/clock/jz4780-cgu.h>
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "ingenic,xburst-fpu1.0-mxu1.1";
reg = <0>;
clocks = <&cgu JZ4780_CLK_CPU>;
clock-names = "cpu";
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "ingenic,xburst-fpu1.0-mxu1.1";
reg = <1>;
clocks = <&cgu JZ4780_CLK_CORE1>;
clock-names = "cpu";
};
};
...

20
Documentation/devicetree/bindings/mips/loongson/devices.yaml
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@@ -17,11 +17,23 @@ properties:
compatible:
oneOf:
- description: Generic Loongson3 Quad Core + RS780E
- description: Classic Loongson64 Quad Core + LS7A
items:
- const: loongson,loongson3-4core-rs780e
- const: loongson,loongson64c-4core-ls7a
- description: Generic Loongson3 Octa Core + RS780E
- description: Classic Loongson64 Quad Core + RS780E
items:
- const: loongson,loongson3-8core-rs780e
- const: loongson,loongson64c-4core-rs780e
- description: Classic Loongson64 Octa Core + RS780E
items:
- const: loongson,loongson64c-8core-rs780e
- description: Generic Loongson64 Quad Core + LS7A
items:
- const: loongson,loongson64g-4core-ls7a
- description: Virtual Loongson64 Quad Core + VirtIO
items:
- const: loongson,loongson64v-4core-virtio
...

8
Documentation/devicetree/bindings/power/mti,mips-cpc.txt
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@@ -1,8 +0,0 @@
Binding for MIPS Cluster Power Controller (CPC).
This binding allows a system to specify where the CPC registers are
located.
Required properties:
compatible : Should be "mti,mips-cpc".
regs: Should describe the address & size of the CPC register region.

35
Documentation/devicetree/bindings/power/mti,mips-cpc.yaml Normal file
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@@ -0,0 +1,35 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/power/mti,mips-cpc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MIPS Cluster Power Controller
description: |
Defines a location of the MIPS Cluster Power Controller registers.
maintainers:
- Paul Burton <paulburton@kernel.org>
properties:
compatible:
const: mti,mips-cpc
reg:
description: |
Base address and size of an unoccupied memory region, which will be
used to map the MIPS CPC registers block.
maxItems: 1
required:
- compatible
- reg
examples:
- |
cpc@1bde0000 {
compatible = "mti,mips-cpc";
reg = <0x1bde0000 0x8000>;
};
...

5
Documentation/devicetree/bindings/timer/ingenic,tcu.yaml
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@@ -116,7 +116,9 @@ patternProperties:
- ingenic,jz4740-watchdog
- ingenic,jz4780-watchdog
- items:
- const: ingenic,jz4770-watchdog
- enum:
- ingenic,jz4770-watchdog
- ingenic,jz4725b-watchdog
- const: ingenic,jz4740-watchdog
reg:
@@ -142,6 +144,7 @@ patternProperties:
oneOf:
- enum:
- ingenic,jz4740-pwm
- ingenic,jz4725b-pwm
- items:
- enum:
- ingenic,jz4770-pwm

2
Documentation/devicetree/bindings/vendor-prefixes.yaml
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@@ -1179,6 +1179,8 @@ patternProperties:
description: Shenzhen Xunlong Software CO.,Limited
"^xylon,.*":
description: Xylon
"^ylm,.*":
description: Shenzhen Yangliming Electronic Technology Co., Ltd.
"^yna,.*":
description: YSH & ATIL
"^yones-toptech,.*":