Merge tag 'drm-intel-next-2018-06-20' of git://anongit.freedesktop.org/drm/drm-intel into drm-next
Chris is doing many reworks that allow us to get full-ppgtt supported on all platforms back to HSW. As well many other fix and improvements, Including: - Use GEM suspend when aborting initialization (Chris) - Change i915_gem_fault to return vm_fault_t (Chris) - Expand VMA to Non gem object entities (Chris) - Improve logs for load failure, but quite logging on fault injection to avoid noise on CI (Chris) - Other page directory handling fixes and improvements for gen6 (Chris) - Other gtt clean-up removing redundancies and unused checks (Chris) - Reorder aliasing ppgtt fini (Chris) - Refactor of unsetting obg->mm.pages (Chris) - Apply batch location restrictions before pinning (Chris) - Ringbuffer fixes for context restore (Chris) - Execlist fixes on freeing error pointer on allocation error (Chris) - Make closing request flush mandatory (Chris) - Move GEM sanitize from resume_early to resume (Chris) - Improve debug dumps (Chris) - Silent compiler for selftest (Chris) - Other execlists changes to improve hangcheck and reset. - Many gtt page directory fixes and improvements (Chris) - Reorg context workarounds (Chris) - Avoid ERR_PTR dereference on selftest (Chris) Other GEM related work: - Stop trying to reset GPU if reset failed (Mika) - Add HW workaround for KBL to fix GPU reset (Mika) - Fix context ban and hang accounting for client (Mika) - Fixes on OA perf (Michel, Jani) - Refactor on GuC log mechanisms (Piotr) - Enable provoking vertex fix on Gen9 system (Kenneth) More ICL patches for Display enabling: - ICL - 10-bit support for HDMI (RK) - ICL - Start adding TBT PLL (Paulo) - ICL - DDI HDMK level selection (Manasi) - ICL - GMBUS GPIO pin mapping fix (Mahesh) - ICL - Adding DP_AUX_E support (James) - ICL - Display interrupts handling (DK) Other display fixes and improvements: - Fix sprite destination color keying on SKL+ (Ville) - Fixes and improvements on PCH detection, specially for non PCH systems (Jani) - Document PCH_NOP (Lucas) - Allow DBLSCAN user modes with eDP/LVDS/DSI (Ville) - Opregion and ACPI cleanup and organization (Jani) - Kill delays when activation psr (Rodrigo) - ...and a consequent fix of the psr activation flow (DK) - Fix HDMI infoframe setting (Imre) - Fix Display interrupts and modes on old gens (Ville) - Start switching to kernel unsigned int types (Jani) - Introduction to Amber Lake and Whiskey Lake platforms (Jose) - Audio clock fixes for HBR3 (RK) - Standardize i915_reg.h definitions according to our doc and checkpatch (Paulo) - Remove unused timespec_to_jiffies_timeout function (Arnd) - Increase the scope of PSR wake fix for other VBTs out there (Vathsala) - Improve debug msgs with prop name/id (Ville) - Other clean up on unecessary cursor size defines (Ville) - Enforce max hdisplay/hblank_start limits on HSW/BDW (Ville) - Make ELD pointers constant (Jani) - Fix for PSR VBT parse (Colin) - Add warn about unsupported CDCLK rates (Imre) Signed-off-by: Dave Airlie <airlied@redhat.com> # gpg: Signature made Thu 21 Jun 2018 07:12:10 AM AEST # gpg: using RSA key FA625F640EEB13CA # gpg: Good signature from "Rodrigo Vivi <rodrigo.vivi@intel.com>" # gpg: aka "Rodrigo Vivi <rodrigo.vivi@gmail.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6D20 7068 EEDD 6509 1C2C E2A3 FA62 5F64 0EEB 13CA Link: https://patchwork.freedesktop.org/patch/msgid/20180625165622.GA21761@intel.com
This commit is contained in:
Dave Airlie
@@ -55,6 +55,8 @@ unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt)
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return D_SKL;
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else if (IS_KABYLAKE(gvt->dev_priv))
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return D_KBL;
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else if (IS_BROXTON(gvt->dev_priv))
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return D_BXT;
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return 0;
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}
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@@ -255,7 +257,8 @@ static int mul_force_wake_write(struct intel_vgpu *vgpu,
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new = CALC_MODE_MASK_REG(old, *(u32 *)p_data);
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if (IS_SKYLAKE(vgpu->gvt->dev_priv)
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|| IS_KABYLAKE(vgpu->gvt->dev_priv)) {
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|| IS_KABYLAKE(vgpu->gvt->dev_priv)
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|| IS_BROXTON(vgpu->gvt->dev_priv)) {
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switch (offset) {
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case FORCEWAKE_RENDER_GEN9_REG:
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ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG;
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@@ -316,6 +319,7 @@ static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
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}
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}
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/* vgpu_lock already hold by emulate mmio r/w */
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intel_gvt_reset_vgpu_locked(vgpu, false, engine_mask);
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/* sw will wait for the device to ack the reset request */
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@@ -420,7 +424,10 @@ static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
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vgpu_vreg(vgpu, offset) |= I965_PIPECONF_ACTIVE;
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else
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vgpu_vreg(vgpu, offset) &= ~I965_PIPECONF_ACTIVE;
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/* vgpu_lock already hold by emulate mmio r/w */
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mutex_unlock(&vgpu->vgpu_lock);
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intel_gvt_check_vblank_emulation(vgpu->gvt);
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mutex_lock(&vgpu->vgpu_lock);
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return 0;
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}
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@@ -857,7 +864,8 @@ static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu,
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data = vgpu_vreg(vgpu, offset);
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if ((IS_SKYLAKE(vgpu->gvt->dev_priv)
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|| IS_KABYLAKE(vgpu->gvt->dev_priv))
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|| IS_KABYLAKE(vgpu->gvt->dev_priv)
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|| IS_BROXTON(vgpu->gvt->dev_priv))
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&& offset != _REG_SKL_DP_AUX_CH_CTL(port_index)) {
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/* SKL DPB/C/D aux ctl register changed */
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return 0;
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@@ -1209,8 +1217,8 @@ static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
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ret = handle_g2v_notification(vgpu, data);
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break;
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/* add xhot and yhot to handled list to avoid error log */
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case 0x78830:
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case 0x78834:
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case _vgtif_reg(cursor_x_hot):
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case _vgtif_reg(cursor_y_hot):
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case _vgtif_reg(pdp[0].lo):
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case _vgtif_reg(pdp[0].hi):
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case _vgtif_reg(pdp[1].lo):
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@@ -1369,6 +1377,16 @@ static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset,
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*data0 = 0x1e1a1100;
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else
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*data0 = 0x61514b3d;
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} else if (IS_BROXTON(vgpu->gvt->dev_priv)) {
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/**
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* "Read memory latency" command on gen9.
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* Below memory latency values are read
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* from Broxton MRB.
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*/
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if (!*data0)
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*data0 = 0x16080707;
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else
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*data0 = 0x16161616;
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}
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break;
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case SKL_PCODE_CDCLK_CONTROL:
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@@ -1426,8 +1444,11 @@ static int skl_power_well_ctl_write(struct intel_vgpu *vgpu,
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{
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u32 v = *(u32 *)p_data;
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v &= (1 << 31) | (1 << 29) | (1 << 9) |
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(1 << 7) | (1 << 5) | (1 << 3) | (1 << 1);
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if (IS_BROXTON(vgpu->gvt->dev_priv))
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v &= (1 << 31) | (1 << 29);
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else
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v &= (1 << 31) | (1 << 29) | (1 << 9) |
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(1 << 7) | (1 << 5) | (1 << 3) | (1 << 1);
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v |= (v >> 1);
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return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes);
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@@ -1447,6 +1468,102 @@ static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset,
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return 0;
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}
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static int bxt_de_pll_enable_write(struct intel_vgpu *vgpu,
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unsigned int offset, void *p_data, unsigned int bytes)
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{
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u32 v = *(u32 *)p_data;
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if (v & BXT_DE_PLL_PLL_ENABLE)
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v |= BXT_DE_PLL_LOCK;
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vgpu_vreg(vgpu, offset) = v;
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return 0;
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}
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static int bxt_port_pll_enable_write(struct intel_vgpu *vgpu,
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unsigned int offset, void *p_data, unsigned int bytes)
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{
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u32 v = *(u32 *)p_data;
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if (v & PORT_PLL_ENABLE)
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v |= PORT_PLL_LOCK;
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vgpu_vreg(vgpu, offset) = v;
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return 0;
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}
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static int bxt_phy_ctl_family_write(struct intel_vgpu *vgpu,
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unsigned int offset, void *p_data, unsigned int bytes)
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{
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u32 v = *(u32 *)p_data;
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u32 data = v & COMMON_RESET_DIS ? BXT_PHY_LANE_ENABLED : 0;
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vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_A) = data;
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vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_B) = data;
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vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_C) = data;
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vgpu_vreg(vgpu, offset) = v;
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return 0;
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}
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static int bxt_port_tx_dw3_read(struct intel_vgpu *vgpu,
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unsigned int offset, void *p_data, unsigned int bytes)
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{
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u32 v = vgpu_vreg(vgpu, offset);
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v &= ~UNIQUE_TRANGE_EN_METHOD;
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vgpu_vreg(vgpu, offset) = v;
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return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
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}
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static int bxt_pcs_dw12_grp_write(struct intel_vgpu *vgpu,
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unsigned int offset, void *p_data, unsigned int bytes)
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{
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u32 v = *(u32 *)p_data;
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if (offset == _PORT_PCS_DW12_GRP_A || offset == _PORT_PCS_DW12_GRP_B) {
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vgpu_vreg(vgpu, offset - 0x600) = v;
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vgpu_vreg(vgpu, offset - 0x800) = v;
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} else {
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vgpu_vreg(vgpu, offset - 0x400) = v;
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vgpu_vreg(vgpu, offset - 0x600) = v;
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}
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vgpu_vreg(vgpu, offset) = v;
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return 0;
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}
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static int bxt_gt_disp_pwron_write(struct intel_vgpu *vgpu,
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unsigned int offset, void *p_data, unsigned int bytes)
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{
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u32 v = *(u32 *)p_data;
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if (v & BIT(0)) {
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vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=
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~PHY_RESERVED;
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vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=
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PHY_POWER_GOOD;
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}
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if (v & BIT(1)) {
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vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &=
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~PHY_RESERVED;
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vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |=
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PHY_POWER_GOOD;
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}
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vgpu_vreg(vgpu, offset) = v;
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return 0;
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}
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static int mmio_read_from_hw(struct intel_vgpu *vgpu,
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unsigned int offset, void *p_data, unsigned int bytes)
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{
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@@ -2670,17 +2787,17 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
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MMIO_D(_MMIO(0x45504), D_SKL_PLUS);
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MMIO_D(_MMIO(0x45520), D_SKL_PLUS);
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MMIO_D(_MMIO(0x46000), D_SKL_PLUS);
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MMIO_DH(_MMIO(0x46010), D_SKL | D_KBL, NULL, skl_lcpll_write);
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MMIO_DH(_MMIO(0x46014), D_SKL | D_KBL, NULL, skl_lcpll_write);
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MMIO_D(_MMIO(0x6C040), D_SKL | D_KBL);
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MMIO_D(_MMIO(0x6C048), D_SKL | D_KBL);
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MMIO_D(_MMIO(0x6C050), D_SKL | D_KBL);
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MMIO_D(_MMIO(0x6C044), D_SKL | D_KBL);
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MMIO_D(_MMIO(0x6C04C), D_SKL | D_KBL);
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MMIO_D(_MMIO(0x6C054), D_SKL | D_KBL);
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MMIO_D(_MMIO(0x6c058), D_SKL | D_KBL);
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MMIO_D(_MMIO(0x6c05c), D_SKL | D_KBL);
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MMIO_DH(_MMIO(0x6c060), D_SKL | D_KBL, dpll_status_read, NULL);
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MMIO_DH(_MMIO(0x46010), D_SKL_PLUS, NULL, skl_lcpll_write);
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MMIO_DH(_MMIO(0x46014), D_SKL_PLUS, NULL, skl_lcpll_write);
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MMIO_D(_MMIO(0x6C040), D_SKL_PLUS);
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MMIO_D(_MMIO(0x6C048), D_SKL_PLUS);
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MMIO_D(_MMIO(0x6C050), D_SKL_PLUS);
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MMIO_D(_MMIO(0x6C044), D_SKL_PLUS);
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MMIO_D(_MMIO(0x6C04C), D_SKL_PLUS);
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MMIO_D(_MMIO(0x6C054), D_SKL_PLUS);
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MMIO_D(_MMIO(0x6c058), D_SKL_PLUS);
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MMIO_D(_MMIO(0x6c05c), D_SKL_PLUS);
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MMIO_DH(_MMIO(0x6c060), D_SKL_PLUS, dpll_status_read, NULL);
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MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
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MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
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@@ -2805,53 +2922,57 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
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MMIO_D(_MMIO(0x7239c), D_SKL_PLUS);
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MMIO_D(_MMIO(0x7039c), D_SKL_PLUS);
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MMIO_D(_MMIO(0x8f074), D_SKL | D_KBL);
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MMIO_D(_MMIO(0x8f004), D_SKL | D_KBL);
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MMIO_D(_MMIO(0x8f034), D_SKL | D_KBL);
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MMIO_D(_MMIO(0x8f074), D_SKL_PLUS);
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MMIO_D(_MMIO(0x8f004), D_SKL_PLUS);
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MMIO_D(_MMIO(0x8f034), D_SKL_PLUS);
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MMIO_D(_MMIO(0xb11c), D_SKL | D_KBL);
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MMIO_D(_MMIO(0xb11c), D_SKL_PLUS);
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MMIO_D(_MMIO(0x51000), D_SKL | D_KBL);
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MMIO_D(_MMIO(0x51000), D_SKL_PLUS);
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MMIO_D(_MMIO(0x6c00c), D_SKL_PLUS);
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MMIO_F(_MMIO(0xc800), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL | D_KBL, NULL, NULL);
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MMIO_F(_MMIO(0xb020), 0x80, F_CMD_ACCESS, 0, 0, D_SKL | D_KBL, NULL, NULL);
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MMIO_F(_MMIO(0xc800), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
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NULL, NULL);
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MMIO_F(_MMIO(0xb020), 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
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NULL, NULL);
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MMIO_D(RPM_CONFIG0, D_SKL_PLUS);
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MMIO_D(_MMIO(0xd08), D_SKL_PLUS);
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MMIO_D(RC6_LOCATION, D_SKL_PLUS);
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MMIO_DFH(_MMIO(0x20e0), D_SKL_PLUS, F_MODE_MASK, NULL, NULL);
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MMIO_DFH(_MMIO(0x20ec), D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
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MMIO_DFH(_MMIO(0x20ec), D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
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NULL, NULL);
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/* TRTT */
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MMIO_DFH(_MMIO(0x4de0), D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL);
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MMIO_DFH(_MMIO(0x4de4), D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL);
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MMIO_DFH(_MMIO(0x4de8), D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL);
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MMIO_DFH(_MMIO(0x4dec), D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL);
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MMIO_DFH(_MMIO(0x4df0), D_SKL | D_KBL, F_CMD_ACCESS, NULL, NULL);
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MMIO_DFH(_MMIO(0x4df4), D_SKL | D_KBL, F_CMD_ACCESS, NULL, gen9_trtte_write);
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MMIO_DH(_MMIO(0x4dfc), D_SKL | D_KBL, NULL, gen9_trtt_chicken_write);
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MMIO_DFH(_MMIO(0x4de0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
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MMIO_DFH(_MMIO(0x4de4), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
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MMIO_DFH(_MMIO(0x4de8), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
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MMIO_DFH(_MMIO(0x4dec), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
|
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MMIO_DFH(_MMIO(0x4df0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
|
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MMIO_DFH(_MMIO(0x4df4), D_SKL_PLUS, F_CMD_ACCESS,
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NULL, gen9_trtte_write);
|
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MMIO_DH(_MMIO(0x4dfc), D_SKL_PLUS, NULL, gen9_trtt_chicken_write);
|
||||
|
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MMIO_D(_MMIO(0x45008), D_SKL | D_KBL);
|
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MMIO_D(_MMIO(0x45008), D_SKL_PLUS);
|
||||
|
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MMIO_D(_MMIO(0x46430), D_SKL | D_KBL);
|
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MMIO_D(_MMIO(0x46430), D_SKL_PLUS);
|
||||
|
||||
MMIO_D(_MMIO(0x46520), D_SKL | D_KBL);
|
||||
MMIO_D(_MMIO(0x46520), D_SKL_PLUS);
|
||||
|
||||
MMIO_D(_MMIO(0xc403c), D_SKL | D_KBL);
|
||||
MMIO_D(_MMIO(0xc403c), D_SKL_PLUS);
|
||||
MMIO_D(_MMIO(0xb004), D_SKL_PLUS);
|
||||
MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
|
||||
|
||||
MMIO_D(_MMIO(0x65900), D_SKL_PLUS);
|
||||
MMIO_D(_MMIO(0x1082c0), D_SKL | D_KBL);
|
||||
MMIO_D(_MMIO(0x4068), D_SKL | D_KBL);
|
||||
MMIO_D(_MMIO(0x67054), D_SKL | D_KBL);
|
||||
MMIO_D(_MMIO(0x6e560), D_SKL | D_KBL);
|
||||
MMIO_D(_MMIO(0x6e554), D_SKL | D_KBL);
|
||||
MMIO_D(_MMIO(0x2b20), D_SKL | D_KBL);
|
||||
MMIO_D(_MMIO(0x65f00), D_SKL | D_KBL);
|
||||
MMIO_D(_MMIO(0x65f08), D_SKL | D_KBL);
|
||||
MMIO_D(_MMIO(0x320f0), D_SKL | D_KBL);
|
||||
MMIO_D(_MMIO(0x1082c0), D_SKL_PLUS);
|
||||
MMIO_D(_MMIO(0x4068), D_SKL_PLUS);
|
||||
MMIO_D(_MMIO(0x67054), D_SKL_PLUS);
|
||||
MMIO_D(_MMIO(0x6e560), D_SKL_PLUS);
|
||||
MMIO_D(_MMIO(0x6e554), D_SKL_PLUS);
|
||||
MMIO_D(_MMIO(0x2b20), D_SKL_PLUS);
|
||||
MMIO_D(_MMIO(0x65f00), D_SKL_PLUS);
|
||||
MMIO_D(_MMIO(0x65f08), D_SKL_PLUS);
|
||||
MMIO_D(_MMIO(0x320f0), D_SKL_PLUS);
|
||||
|
||||
MMIO_D(_MMIO(0x70034), D_SKL_PLUS);
|
||||
MMIO_D(_MMIO(0x71034), D_SKL_PLUS);
|
||||
@@ -2869,11 +2990,185 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
|
||||
|
||||
MMIO_D(_MMIO(0x44500), D_SKL_PLUS);
|
||||
MMIO_DFH(GEN9_CSFE_CHICKEN1_RCS, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
|
||||
MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL | D_KBL, F_MODE_MASK | F_CMD_ACCESS,
|
||||
MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
|
||||
NULL, NULL);
|
||||
|
||||
MMIO_D(_MMIO(0x4ab8), D_KBL);
|
||||
MMIO_D(_MMIO(0x2248), D_SKL_PLUS | D_KBL);
|
||||
MMIO_D(_MMIO(0x2248), D_KBL | D_SKL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int init_bxt_mmio_info(struct intel_gvt *gvt)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = gvt->dev_priv;
|
||||
int ret;
|
||||
|
||||
MMIO_F(_MMIO(0x80000), 0x3000, 0, 0, 0, D_BXT, NULL, NULL);
|
||||
|
||||
MMIO_D(GEN7_SAMPLER_INSTDONE, D_BXT);
|
||||
MMIO_D(GEN7_ROW_INSTDONE, D_BXT);
|
||||
MMIO_D(GEN8_FAULT_TLB_DATA0, D_BXT);
|
||||
MMIO_D(GEN8_FAULT_TLB_DATA1, D_BXT);
|
||||
MMIO_D(ERROR_GEN6, D_BXT);
|
||||
MMIO_D(DONE_REG, D_BXT);
|
||||
MMIO_D(EIR, D_BXT);
|
||||
MMIO_D(PGTBL_ER, D_BXT);
|
||||
MMIO_D(_MMIO(0x4194), D_BXT);
|
||||
MMIO_D(_MMIO(0x4294), D_BXT);
|
||||
MMIO_D(_MMIO(0x4494), D_BXT);
|
||||
|
||||
MMIO_RING_D(RING_PSMI_CTL, D_BXT);
|
||||
MMIO_RING_D(RING_DMA_FADD, D_BXT);
|
||||
MMIO_RING_D(RING_DMA_FADD_UDW, D_BXT);
|
||||
MMIO_RING_D(RING_IPEHR, D_BXT);
|
||||
MMIO_RING_D(RING_INSTPS, D_BXT);
|
||||
MMIO_RING_D(RING_BBADDR_UDW, D_BXT);
|
||||
MMIO_RING_D(RING_BBSTATE, D_BXT);
|
||||
MMIO_RING_D(RING_IPEIR, D_BXT);
|
||||
|
||||
MMIO_F(SOFT_SCRATCH(0), 16 * 4, 0, 0, 0, D_BXT, NULL, NULL);
|
||||
|
||||
MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write);
|
||||
MMIO_D(BXT_RP_STATE_CAP, D_BXT);
|
||||
MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT,
|
||||
NULL, bxt_phy_ctl_family_write);
|
||||
MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT,
|
||||
NULL, bxt_phy_ctl_family_write);
|
||||
MMIO_D(BXT_PHY_CTL(PORT_A), D_BXT);
|
||||
MMIO_D(BXT_PHY_CTL(PORT_B), D_BXT);
|
||||
MMIO_D(BXT_PHY_CTL(PORT_C), D_BXT);
|
||||
MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT,
|
||||
NULL, bxt_port_pll_enable_write);
|
||||
MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT,
|
||||
NULL, bxt_port_pll_enable_write);
|
||||
MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL,
|
||||
bxt_port_pll_enable_write);
|
||||
|
||||
MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY0), D_BXT);
|
||||
MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY0), D_BXT);
|
||||
MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY0), D_BXT);
|
||||
MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY0), D_BXT);
|
||||
MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY0), D_BXT);
|
||||
MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY0), D_BXT);
|
||||
MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY0), D_BXT);
|
||||
MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY0), D_BXT);
|
||||
MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY0), D_BXT);
|
||||
|
||||
MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY1), D_BXT);
|
||||
MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY1), D_BXT);
|
||||
MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY1), D_BXT);
|
||||
MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY1), D_BXT);
|
||||
MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY1), D_BXT);
|
||||
MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY1), D_BXT);
|
||||
MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY1), D_BXT);
|
||||
MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY1), D_BXT);
|
||||
MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY1), D_BXT);
|
||||
|
||||
MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH0), D_BXT);
|
||||
MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH0), D_BXT);
|
||||
MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
|
||||
MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
|
||||
MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH0), D_BXT);
|
||||
MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH0), D_BXT);
|
||||
MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT,
|
||||
NULL, bxt_pcs_dw12_grp_write);
|
||||
MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
|
||||
MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
|
||||
MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT,
|
||||
bxt_port_tx_dw3_read, NULL);
|
||||
MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
|
||||
MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH0), D_BXT);
|
||||
MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH0), D_BXT);
|
||||
MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
|
||||
MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
|
||||
MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
|
||||
MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
|
||||
MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 0), D_BXT);
|
||||
MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 1), D_BXT);
|
||||
MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 2), D_BXT);
|
||||
MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 3), D_BXT);
|
||||
MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 6), D_BXT);
|
||||
MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 8), D_BXT);
|
||||
MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 9), D_BXT);
|
||||
MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH0, 10), D_BXT);
|
||||
|
||||
MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY0, DPIO_CH1), D_BXT);
|
||||
MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY0, DPIO_CH1), D_BXT);
|
||||
MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
|
||||
MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
|
||||
MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY0, DPIO_CH1), D_BXT);
|
||||
MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY0, DPIO_CH1), D_BXT);
|
||||
MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT,
|
||||
NULL, bxt_pcs_dw12_grp_write);
|
||||
MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
|
||||
MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
|
||||
MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT,
|
||||
bxt_port_tx_dw3_read, NULL);
|
||||
MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
|
||||
MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY0, DPIO_CH1), D_BXT);
|
||||
MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY0, DPIO_CH1), D_BXT);
|
||||
MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
|
||||
MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
|
||||
MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
|
||||
MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
|
||||
MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 0), D_BXT);
|
||||
MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 1), D_BXT);
|
||||
MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 2), D_BXT);
|
||||
MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 3), D_BXT);
|
||||
MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 6), D_BXT);
|
||||
MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 8), D_BXT);
|
||||
MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 9), D_BXT);
|
||||
MMIO_D(BXT_PORT_PLL(DPIO_PHY0, DPIO_CH1, 10), D_BXT);
|
||||
|
||||
MMIO_D(BXT_PORT_PLL_EBB_0(DPIO_PHY1, DPIO_CH0), D_BXT);
|
||||
MMIO_D(BXT_PORT_PLL_EBB_4(DPIO_PHY1, DPIO_CH0), D_BXT);
|
||||
MMIO_D(BXT_PORT_PCS_DW10_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
|
||||
MMIO_D(BXT_PORT_PCS_DW10_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
|
||||
MMIO_D(BXT_PORT_PCS_DW12_LN01(DPIO_PHY1, DPIO_CH0), D_BXT);
|
||||
MMIO_D(BXT_PORT_PCS_DW12_LN23(DPIO_PHY1, DPIO_CH0), D_BXT);
|
||||
MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT,
|
||||
NULL, bxt_pcs_dw12_grp_write);
|
||||
MMIO_D(BXT_PORT_TX_DW2_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
|
||||
MMIO_D(BXT_PORT_TX_DW2_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
|
||||
MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT,
|
||||
bxt_port_tx_dw3_read, NULL);
|
||||
MMIO_D(BXT_PORT_TX_DW3_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
|
||||
MMIO_D(BXT_PORT_TX_DW4_LN0(DPIO_PHY1, DPIO_CH0), D_BXT);
|
||||
MMIO_D(BXT_PORT_TX_DW4_GRP(DPIO_PHY1, DPIO_CH0), D_BXT);
|
||||
MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
|
||||
MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
|
||||
MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
|
||||
MMIO_D(BXT_PORT_TX_DW14_LN(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
|
||||
MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 0), D_BXT);
|
||||
MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 1), D_BXT);
|
||||
MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 2), D_BXT);
|
||||
MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 3), D_BXT);
|
||||
MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 6), D_BXT);
|
||||
MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 8), D_BXT);
|
||||
MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 9), D_BXT);
|
||||
MMIO_D(BXT_PORT_PLL(DPIO_PHY1, DPIO_CH0, 10), D_BXT);
|
||||
|
||||
MMIO_D(BXT_DE_PLL_CTL, D_BXT);
|
||||
MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write);
|
||||
MMIO_D(BXT_DSI_PLL_CTL, D_BXT);
|
||||
MMIO_D(BXT_DSI_PLL_ENABLE, D_BXT);
|
||||
|
||||
MMIO_D(GEN9_CLKGATE_DIS_0, D_BXT);
|
||||
|
||||
MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A), D_BXT);
|
||||
MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B), D_BXT);
|
||||
MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C), D_BXT);
|
||||
|
||||
MMIO_D(RC6_CTX_BASE, D_BXT);
|
||||
|
||||
MMIO_D(GEN8_PUSHBUS_CONTROL, D_BXT);
|
||||
MMIO_D(GEN8_PUSHBUS_ENABLE, D_BXT);
|
||||
MMIO_D(GEN8_PUSHBUS_SHIFT, D_BXT);
|
||||
MMIO_D(GEN6_GFXPAUSE, D_BXT);
|
||||
MMIO_D(GEN8_L3SQCREG1, D_BXT);
|
||||
|
||||
MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -2965,6 +3260,16 @@ int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
|
||||
ret = init_skl_mmio_info(gvt);
|
||||
if (ret)
|
||||
goto err;
|
||||
} else if (IS_BROXTON(dev_priv)) {
|
||||
ret = init_broadwell_mmio_info(gvt);
|
||||
if (ret)
|
||||
goto err;
|
||||
ret = init_skl_mmio_info(gvt);
|
||||
if (ret)
|
||||
goto err;
|
||||
ret = init_bxt_mmio_info(gvt);
|
||||
if (ret)
|
||||
goto err;
|
||||
}
|
||||
|
||||
gvt->mmio.mmio_block = mmio_blocks;
|
||||
|
||||
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