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Merge tag 'i3c/for-4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/i3c/linux

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Pull initial i3c support from Boris Brezillon:
 "Add initial support for I3C along with two I3C master controller
  drivers"

* tag 'i3c/for-4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/i3c/linux:
  i3c: master: cdns: fix I2C transfers in Cadence I3C master driver
  ic3: off by one in mode_show()
  i3c: fix an error code in i3c_master_add_i3c_dev_locked()
  i3c: master: dw: fix mask operation by using the correct operator
  MAINTAINERS: Add myself as the dw-i3c-master module maintainer
  dt-binding: i3c: Document Synopsys DesignWare I3C
  i3c: master: Add driver for Synopsys DesignWare IP
  i3c: master: Remove set but not used variable 'old_i3c_scl_lim'
  dt-bindings: i3c: Document Cadence I3C master bindings
  i3c: master: Add driver for Cadence IP
  MAINTAINERS: Add myself as the I3C subsystem maintainer
  dt-bindings: i3c: Document core bindings
  i3c: Add sysfs ABI spec
  docs: driver-api: Add I3C documentation
  i3c: Add core I3C infrastructure
This commit is contained in:
Linus Torvalds
2018-12-25 12:26:34 -08:00
parent 4971f090aa 25ac3da61b
commit b3cc2bfe72
25 changed files with 7855 additions and 1 deletions
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385
include/linux/i3c/ccc.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2018 Cadence Design Systems Inc.
*
* Author: Boris Brezillon <boris.brezillon@bootlin.com>
*/
#ifndef I3C_CCC_H
#define I3C_CCC_H
#include <linux/bitops.h>
#include <linux/i3c/device.h>
/* I3C CCC (Common Command Codes) related definitions */
#define I3C_CCC_DIRECT BIT(7)
#define I3C_CCC_ID(id, broadcast) \
((id) | ((broadcast) ? 0 : I3C_CCC_DIRECT))
/* Commands valid in both broadcast and unicast modes */
#define I3C_CCC_ENEC(broadcast) I3C_CCC_ID(0x0, broadcast)
#define I3C_CCC_DISEC(broadcast) I3C_CCC_ID(0x1, broadcast)
#define I3C_CCC_ENTAS(as, broadcast) I3C_CCC_ID(0x2 + (as), broadcast)
#define I3C_CCC_RSTDAA(broadcast) I3C_CCC_ID(0x6, broadcast)
#define I3C_CCC_SETMWL(broadcast) I3C_CCC_ID(0x9, broadcast)
#define I3C_CCC_SETMRL(broadcast) I3C_CCC_ID(0xa, broadcast)
#define I3C_CCC_SETXTIME(broadcast) ((broadcast) ? 0x28 : 0x98)
#define I3C_CCC_VENDOR(id, broadcast) ((id) + ((broadcast) ? 0x61 : 0xe0))
/* Broadcast-only commands */
#define I3C_CCC_ENTDAA I3C_CCC_ID(0x7, true)
#define I3C_CCC_DEFSLVS I3C_CCC_ID(0x8, true)
#define I3C_CCC_ENTTM I3C_CCC_ID(0xb, true)
#define I3C_CCC_ENTHDR(x) I3C_CCC_ID(0x20 + (x), true)
/* Unicast-only commands */
#define I3C_CCC_SETDASA I3C_CCC_ID(0x7, false)
#define I3C_CCC_SETNEWDA I3C_CCC_ID(0x8, false)
#define I3C_CCC_GETMWL I3C_CCC_ID(0xb, false)
#define I3C_CCC_GETMRL I3C_CCC_ID(0xc, false)
#define I3C_CCC_GETPID I3C_CCC_ID(0xd, false)
#define I3C_CCC_GETBCR I3C_CCC_ID(0xe, false)
#define I3C_CCC_GETDCR I3C_CCC_ID(0xf, false)
#define I3C_CCC_GETSTATUS I3C_CCC_ID(0x10, false)
#define I3C_CCC_GETACCMST I3C_CCC_ID(0x11, false)
#define I3C_CCC_SETBRGTGT I3C_CCC_ID(0x13, false)
#define I3C_CCC_GETMXDS I3C_CCC_ID(0x14, false)
#define I3C_CCC_GETHDRCAP I3C_CCC_ID(0x15, false)
#define I3C_CCC_GETXTIME I3C_CCC_ID(0x19, false)
#define I3C_CCC_EVENT_SIR BIT(0)
#define I3C_CCC_EVENT_MR BIT(1)
#define I3C_CCC_EVENT_HJ BIT(3)
/**
* struct i3c_ccc_events - payload passed to ENEC/DISEC CCC
*
* @events: bitmask of I3C_CCC_EVENT_xxx events.
*
* Depending on the CCC command, the specific events coming from all devices
* (broadcast version) or a specific device (unicast version) will be
* enabled (ENEC) or disabled (DISEC).
*/
struct i3c_ccc_events {
u8 events;
};
/**
* struct i3c_ccc_mwl - payload passed to SETMWL/GETMWL CCC
*
* @len: maximum write length in bytes
*
* The maximum write length is only applicable to SDR private messages or
* extended Write CCCs (like SETXTIME).
*/
struct i3c_ccc_mwl {
__be16 len;
};
/**
* struct i3c_ccc_mrl - payload passed to SETMRL/GETMRL CCC
*
* @len: maximum read length in bytes
* @ibi_len: maximum IBI payload length
*
* The maximum read length is only applicable to SDR private messages or
* extended Read CCCs (like GETXTIME).
* The IBI length is only valid if the I3C slave is IBI capable
* (%I3C_BCR_IBI_REQ_CAP is set).
*/
struct i3c_ccc_mrl {
__be16 read_len;
u8 ibi_len;
} __packed;
/**
* struct i3c_ccc_dev_desc - I3C/I2C device descriptor used for DEFSLVS
*
* @dyn_addr: dynamic address assigned to the I3C slave or 0 if the entry is
* describing an I2C slave.
* @dcr: DCR value (not applicable to entries describing I2C devices)
* @lvr: LVR value (not applicable to entries describing I3C devices)
* @bcr: BCR value or 0 if this entry is describing an I2C slave
* @static_addr: static address or 0 if the device does not have a static
* address
*
* The DEFSLVS command should be passed an array of i3c_ccc_dev_desc
* descriptors (one entry per I3C/I2C dev controlled by the master).
*/
struct i3c_ccc_dev_desc {
u8 dyn_addr;
union {
u8 dcr;
u8 lvr;
};
u8 bcr;
u8 static_addr;
};
/**
* struct i3c_ccc_defslvs - payload passed to DEFSLVS CCC
*
* @count: number of dev descriptors
* @master: descriptor describing the current master
* @slaves: array of descriptors describing slaves controlled by the
* current master
*
* Information passed to the broadcast DEFSLVS to propagate device
* information to all masters currently acting as slaves on the bus.
* This is only meaningful if you have more than one master.
*/
struct i3c_ccc_defslvs {
u8 count;
struct i3c_ccc_dev_desc master;
struct i3c_ccc_dev_desc slaves[0];
} __packed;
/**
* enum i3c_ccc_test_mode - enum listing all available test modes
*
* @I3C_CCC_EXIT_TEST_MODE: exit test mode
* @I3C_CCC_VENDOR_TEST_MODE: enter vendor test mode
*/
enum i3c_ccc_test_mode {
I3C_CCC_EXIT_TEST_MODE,
I3C_CCC_VENDOR_TEST_MODE,
};
/**
* struct i3c_ccc_enttm - payload passed to ENTTM CCC
*
* @mode: one of the &enum i3c_ccc_test_mode modes
*
* Information passed to the ENTTM CCC to instruct an I3C device to enter a
* specific test mode.
*/
struct i3c_ccc_enttm {
u8 mode;
};
/**
* struct i3c_ccc_setda - payload passed to SETNEWDA and SETDASA CCCs
*
* @addr: dynamic address to assign to an I3C device
*
* Information passed to the SETNEWDA and SETDASA CCCs to assign/change the
* dynamic address of an I3C device.
*/
struct i3c_ccc_setda {
u8 addr;
};
/**
* struct i3c_ccc_getpid - payload passed to GETPID CCC
*
* @pid: 48 bits PID in big endian
*/
struct i3c_ccc_getpid {
u8 pid[6];
};
/**
* struct i3c_ccc_getbcr - payload passed to GETBCR CCC
*
* @bcr: BCR (Bus Characteristic Register) value
*/
struct i3c_ccc_getbcr {
u8 bcr;
};
/**
* struct i3c_ccc_getdcr - payload passed to GETDCR CCC
*
* @dcr: DCR (Device Characteristic Register) value
*/
struct i3c_ccc_getdcr {
u8 dcr;
};
#define I3C_CCC_STATUS_PENDING_INT(status) ((status) & GENMASK(3, 0))
#define I3C_CCC_STATUS_PROTOCOL_ERROR BIT(5)
#define I3C_CCC_STATUS_ACTIVITY_MODE(status) \
(((status) & GENMASK(7, 6)) >> 6)
/**
* struct i3c_ccc_getstatus - payload passed to GETSTATUS CCC
*
* @status: status of the I3C slave (see I3C_CCC_STATUS_xxx macros for more
* information).
*/
struct i3c_ccc_getstatus {
__be16 status;
};
/**
* struct i3c_ccc_getaccmst - payload passed to GETACCMST CCC
*
* @newmaster: address of the master taking bus ownership
*/
struct i3c_ccc_getaccmst {
u8 newmaster;
};
/**
* struct i3c_ccc_bridged_slave_desc - bridged slave descriptor
*
* @addr: dynamic address of the bridged device
* @id: ID of the slave device behind the bridge
*/
struct i3c_ccc_bridged_slave_desc {
u8 addr;
__be16 id;
} __packed;
/**
* struct i3c_ccc_setbrgtgt - payload passed to SETBRGTGT CCC
*
* @count: number of bridged slaves
* @bslaves: bridged slave descriptors
*/
struct i3c_ccc_setbrgtgt {
u8 count;
struct i3c_ccc_bridged_slave_desc bslaves[0];
} __packed;
/**
* enum i3c_sdr_max_data_rate - max data rate values for private SDR transfers
*/
enum i3c_sdr_max_data_rate {
I3C_SDR0_FSCL_MAX,
I3C_SDR1_FSCL_8MHZ,
I3C_SDR2_FSCL_6MHZ,
I3C_SDR3_FSCL_4MHZ,
I3C_SDR4_FSCL_2MHZ,
};
/**
* enum i3c_tsco - clock to data turn-around
*/
enum i3c_tsco {
I3C_TSCO_8NS,
I3C_TSCO_9NS,
I3C_TSCO_10NS,
I3C_TSCO_11NS,
I3C_TSCO_12NS,
};
#define I3C_CCC_MAX_SDR_FSCL_MASK GENMASK(2, 0)
#define I3C_CCC_MAX_SDR_FSCL(x) ((x) & I3C_CCC_MAX_SDR_FSCL_MASK)
/**
* struct i3c_ccc_getmxds - payload passed to GETMXDS CCC
*
* @maxwr: write limitations
* @maxrd: read limitations
* @maxrdturn: maximum read turn-around expressed micro-seconds and
* little-endian formatted
*/
struct i3c_ccc_getmxds {
u8 maxwr;
u8 maxrd;
u8 maxrdturn[3];
} __packed;
#define I3C_CCC_HDR_MODE(mode) BIT(mode)
/**
* struct i3c_ccc_gethdrcap - payload passed to GETHDRCAP CCC
*
* @modes: bitmap of supported HDR modes
*/
struct i3c_ccc_gethdrcap {
u8 modes;
} __packed;
/**
* enum i3c_ccc_setxtime_subcmd - SETXTIME sub-commands
*/
enum i3c_ccc_setxtime_subcmd {
I3C_CCC_SETXTIME_ST = 0x7f,
I3C_CCC_SETXTIME_DT = 0xbf,
I3C_CCC_SETXTIME_ENTER_ASYNC_MODE0 = 0xdf,
I3C_CCC_SETXTIME_ENTER_ASYNC_MODE1 = 0xef,
I3C_CCC_SETXTIME_ENTER_ASYNC_MODE2 = 0xf7,
I3C_CCC_SETXTIME_ENTER_ASYNC_MODE3 = 0xfb,
I3C_CCC_SETXTIME_ASYNC_TRIGGER = 0xfd,
I3C_CCC_SETXTIME_TPH = 0x3f,
I3C_CCC_SETXTIME_TU = 0x9f,
I3C_CCC_SETXTIME_ODR = 0x8f,
};
/**
* struct i3c_ccc_setxtime - payload passed to SETXTIME CCC
*
* @subcmd: one of the sub-commands ddefined in &enum i3c_ccc_setxtime_subcmd
* @data: sub-command payload. Amount of data is determined by
* &i3c_ccc_setxtime->subcmd
*/
struct i3c_ccc_setxtime {
u8 subcmd;
u8 data[0];
} __packed;
#define I3C_CCC_GETXTIME_SYNC_MODE BIT(0)
#define I3C_CCC_GETXTIME_ASYNC_MODE(x) BIT((x) + 1)
#define I3C_CCC_GETXTIME_OVERFLOW BIT(7)
/**
* struct i3c_ccc_getxtime - payload retrieved from GETXTIME CCC
*
* @supported_modes: bitmap describing supported XTIME modes
* @state: current status (enabled mode and overflow status)
* @frequency: slave's internal oscillator frequency in 500KHz steps
* @inaccuracy: slave's internal oscillator inaccuracy in 0.1% steps
*/
struct i3c_ccc_getxtime {
u8 supported_modes;
u8 state;
u8 frequency;
u8 inaccuracy;
} __packed;
/**
* struct i3c_ccc_cmd_payload - CCC payload
*
* @len: payload length
* @data: payload data. This buffer must be DMA-able
*/
struct i3c_ccc_cmd_payload {
u16 len;
void *data;
};
/**
* struct i3c_ccc_cmd_dest - CCC command destination
*
* @addr: can be an I3C device address or the broadcast address if this is a
* broadcast CCC
* @payload: payload to be sent to this device or broadcasted
*/
struct i3c_ccc_cmd_dest {
u8 addr;
struct i3c_ccc_cmd_payload payload;
};
/**
* struct i3c_ccc_cmd - CCC command
*
* @rnw: true if the CCC should retrieve data from the device. Only valid for
* unicast commands
* @id: CCC command id
* @ndests: number of destinations. Should always be one for broadcast commands
* @dests: array of destinations and associated payload for this CCC. Most of
* the time, only one destination is provided
* @err: I3C error code
*/
struct i3c_ccc_cmd {
u8 rnw;
u8 id;
unsigned int ndests;
struct i3c_ccc_cmd_dest *dests;
enum i3c_error_code err;
};
#endif /* I3C_CCC_H */

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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2018 Cadence Design Systems Inc.
*
* Author: Boris Brezillon <boris.brezillon@bootlin.com>
*/
#ifndef I3C_DEV_H
#define I3C_DEV_H
#include <linux/bitops.h>
#include <linux/device.h>
#include <linux/i2c.h>
#include <linux/kconfig.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
/**
* enum i3c_error_code - I3C error codes
*
* These are the standard error codes as defined by the I3C specification.
* When -EIO is returned by the i3c_device_do_priv_xfers() or
* i3c_device_send_hdr_cmds() one can check the error code in
* &struct_i3c_priv_xfer.err or &struct i3c_hdr_cmd.err to get a better idea of
* what went wrong.
*
* @I3C_ERROR_UNKNOWN: unknown error, usually means the error is not I3C
* related
* @I3C_ERROR_M0: M0 error
* @I3C_ERROR_M1: M1 error
* @I3C_ERROR_M2: M2 error
*/
enum i3c_error_code {
I3C_ERROR_UNKNOWN = 0,
I3C_ERROR_M0 = 1,
I3C_ERROR_M1,
I3C_ERROR_M2,
};
/**
* enum i3c_hdr_mode - HDR mode ids
* @I3C_HDR_DDR: DDR mode
* @I3C_HDR_TSP: TSP mode
* @I3C_HDR_TSL: TSL mode
*/
enum i3c_hdr_mode {
I3C_HDR_DDR,
I3C_HDR_TSP,
I3C_HDR_TSL,
};
/**
* struct i3c_priv_xfer - I3C SDR private transfer
* @rnw: encodes the transfer direction. true for a read, false for a write
* @len: transfer length in bytes of the transfer
* @data: input/output buffer
* @data.in: input buffer. Must point to a DMA-able buffer
* @data.out: output buffer. Must point to a DMA-able buffer
* @err: I3C error code
*/
struct i3c_priv_xfer {
u8 rnw;
u16 len;
union {
void *in;
const void *out;
} data;
enum i3c_error_code err;
};
/**
* enum i3c_dcr - I3C DCR values
* @I3C_DCR_GENERIC_DEVICE: generic I3C device
*/
enum i3c_dcr {
I3C_DCR_GENERIC_DEVICE = 0,
};
#define I3C_PID_MANUF_ID(pid) (((pid) & GENMASK_ULL(47, 33)) >> 33)
#define I3C_PID_RND_LOWER_32BITS(pid) (!!((pid) & BIT_ULL(32)))
#define I3C_PID_RND_VAL(pid) ((pid) & GENMASK_ULL(31, 0))
#define I3C_PID_PART_ID(pid) (((pid) & GENMASK_ULL(31, 16)) >> 16)
#define I3C_PID_INSTANCE_ID(pid) (((pid) & GENMASK_ULL(15, 12)) >> 12)
#define I3C_PID_EXTRA_INFO(pid) ((pid) & GENMASK_ULL(11, 0))
#define I3C_BCR_DEVICE_ROLE(bcr) ((bcr) & GENMASK(7, 6))
#define I3C_BCR_I3C_SLAVE (0 << 6)
#define I3C_BCR_I3C_MASTER (1 << 6)
#define I3C_BCR_HDR_CAP BIT(5)
#define I3C_BCR_BRIDGE BIT(4)
#define I3C_BCR_OFFLINE_CAP BIT(3)
#define I3C_BCR_IBI_PAYLOAD BIT(2)
#define I3C_BCR_IBI_REQ_CAP BIT(1)
#define I3C_BCR_MAX_DATA_SPEED_LIM BIT(0)
/**
* struct i3c_device_info - I3C device information
* @pid: Provisional ID
* @bcr: Bus Characteristic Register
* @dcr: Device Characteristic Register
* @static_addr: static/I2C address
* @dyn_addr: dynamic address
* @hdr_cap: supported HDR modes
* @max_read_ds: max read speed information
* @max_write_ds: max write speed information
* @max_ibi_len: max IBI payload length
* @max_read_turnaround: max read turn-around time in micro-seconds
* @max_read_len: max private SDR read length in bytes
* @max_write_len: max private SDR write length in bytes
*
* These are all basic information that should be advertised by an I3C device.
* Some of them are optional depending on the device type and device
* capabilities.
* For each I3C slave attached to a master with
* i3c_master_add_i3c_dev_locked(), the core will send the relevant CCC command
* to retrieve these data.
*/
struct i3c_device_info {
u64 pid;
u8 bcr;
u8 dcr;
u8 static_addr;
u8 dyn_addr;
u8 hdr_cap;
u8 max_read_ds;
u8 max_write_ds;
u8 max_ibi_len;
u32 max_read_turnaround;
u16 max_read_len;
u16 max_write_len;
};
/*
* I3C device internals are kept hidden from I3C device users. It's just
* simpler to refactor things when everything goes through getter/setters, and
* I3C device drivers should not have to worry about internal representation
* anyway.
*/
struct i3c_device;
/* These macros should be used to i3c_device_id entries. */
#define I3C_MATCH_MANUF_AND_PART (I3C_MATCH_MANUF | I3C_MATCH_PART)
#define I3C_DEVICE(_manufid, _partid, _drvdata) \
{ \
.match_flags = I3C_MATCH_MANUF_AND_PART, \
.manuf_id = _manufid, \
.part_id = _partid, \
.data = _drvdata, \
}
#define I3C_DEVICE_EXTRA_INFO(_manufid, _partid, _info, _drvdata) \
{ \
.match_flags = I3C_MATCH_MANUF_AND_PART | \
I3C_MATCH_EXTRA_INFO, \
.manuf_id = _manufid, \
.part_id = _partid, \
.extra_info = _info, \
.data = _drvdata, \
}
#define I3C_CLASS(_dcr, _drvdata) \
{ \
.match_flags = I3C_MATCH_DCR, \
.dcr = _dcr, \
}
/**
* struct i3c_driver - I3C device driver
* @driver: inherit from device_driver
* @probe: I3C device probe method
* @remove: I3C device remove method
* @id_table: I3C device match table. Will be used by the framework to decide
* which device to bind to this driver
*/
struct i3c_driver {
struct device_driver driver;
int (*probe)(struct i3c_device *dev);
int (*remove)(struct i3c_device *dev);
const struct i3c_device_id *id_table;
};
static inline struct i3c_driver *drv_to_i3cdrv(struct device_driver *drv)
{
return container_of(drv, struct i3c_driver, driver);
}
struct device *i3cdev_to_dev(struct i3c_device *i3cdev);
struct i3c_device *dev_to_i3cdev(struct device *dev);
static inline void i3cdev_set_drvdata(struct i3c_device *i3cdev,
void *data)
{
struct device *dev = i3cdev_to_dev(i3cdev);
dev_set_drvdata(dev, data);
}
static inline void *i3cdev_get_drvdata(struct i3c_device *i3cdev)
{
struct device *dev = i3cdev_to_dev(i3cdev);
return dev_get_drvdata(dev);
}
int i3c_driver_register_with_owner(struct i3c_driver *drv,
struct module *owner);
void i3c_driver_unregister(struct i3c_driver *drv);
#define i3c_driver_register(__drv) \
i3c_driver_register_with_owner(__drv, THIS_MODULE)
/**
* module_i3c_driver() - Register a module providing an I3C driver
* @__drv: the I3C driver to register
*
* Provide generic init/exit functions that simply register/unregister an I3C
* driver.
* Should be used by any driver that does not require extra init/cleanup steps.
*/
#define module_i3c_driver(__drv) \
module_driver(__drv, i3c_driver_register, i3c_driver_unregister)
/**
* i3c_i2c_driver_register() - Register an i2c and an i3c driver
* @i3cdrv: the I3C driver to register
* @i2cdrv: the I2C driver to register
*
* This function registers both @i2cdev and @i3cdev, and fails if one of these
* registrations fails. This is mainly useful for devices that support both I2C
* and I3C modes.
* Note that when CONFIG_I3C is not enabled, this function only registers the
* I2C driver.
*
* Return: 0 if both registrations succeeds, a negative error code otherwise.
*/
static inline int i3c_i2c_driver_register(struct i3c_driver *i3cdrv,
struct i2c_driver *i2cdrv)
{
int ret;
ret = i2c_add_driver(i2cdrv);
if (ret || !IS_ENABLED(CONFIG_I3C))
return ret;
ret = i3c_driver_register(i3cdrv);
if (ret)
i2c_del_driver(i2cdrv);
return ret;
}
/**
* i3c_i2c_driver_unregister() - Unregister an i2c and an i3c driver
* @i3cdrv: the I3C driver to register
* @i2cdrv: the I2C driver to register
*
* This function unregisters both @i3cdrv and @i2cdrv.
* Note that when CONFIG_I3C is not enabled, this function only unregisters the
* @i2cdrv.
*/
static inline void i3c_i2c_driver_unregister(struct i3c_driver *i3cdrv,
struct i2c_driver *i2cdrv)
{
if (IS_ENABLED(CONFIG_I3C))
i3c_driver_unregister(i3cdrv);
i2c_del_driver(i2cdrv);
}
/**
* module_i3c_i2c_driver() - Register a module providing an I3C and an I2C
* driver
* @__i3cdrv: the I3C driver to register
* @__i2cdrv: the I3C driver to register
*
* Provide generic init/exit functions that simply register/unregister an I3C
* and an I2C driver.
* This macro can be used even if CONFIG_I3C is disabled, in this case, only
* the I2C driver will be registered.
* Should be used by any driver that does not require extra init/cleanup steps.
*/
#define module_i3c_i2c_driver(__i3cdrv, __i2cdrv) \
module_driver(__i3cdrv, \
i3c_i2c_driver_register, \
i3c_i2c_driver_unregister)
int i3c_device_do_priv_xfers(struct i3c_device *dev,
struct i3c_priv_xfer *xfers,
int nxfers);
void i3c_device_get_info(struct i3c_device *dev, struct i3c_device_info *info);
struct i3c_ibi_payload {
unsigned int len;
const void *data;
};
/**
* struct i3c_ibi_setup - IBI setup object
* @max_payload_len: maximum length of the payload associated to an IBI. If one
* IBI appears to have a payload that is bigger than this
* number, the IBI will be rejected.
* @num_slots: number of pre-allocated IBI slots. This should be chosen so that
* the system never runs out of IBI slots, otherwise you'll lose
* IBIs.
* @handler: IBI handler, every time an IBI is received. This handler is called
* in a workqueue context. It is allowed to sleep and send new
* messages on the bus, though it's recommended to keep the
* processing done there as fast as possible to avoid delaying
* processing of other queued on the same workqueue.
*
* Temporary structure used to pass information to i3c_device_request_ibi().
* This object can be allocated on the stack since i3c_device_request_ibi()
* copies every bit of information and do not use it after
* i3c_device_request_ibi() has returned.
*/
struct i3c_ibi_setup {
unsigned int max_payload_len;
unsigned int num_slots;
void (*handler)(struct i3c_device *dev,
const struct i3c_ibi_payload *payload);
};
int i3c_device_request_ibi(struct i3c_device *dev,
const struct i3c_ibi_setup *setup);
void i3c_device_free_ibi(struct i3c_device *dev);
int i3c_device_enable_ibi(struct i3c_device *dev);
int i3c_device_disable_ibi(struct i3c_device *dev);
#endif /* I3C_DEV_H */

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include/linux/i3c/master.h Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2018 Cadence Design Systems Inc.
*
* Author: Boris Brezillon <boris.brezillon@bootlin.com>
*/
#ifndef I3C_MASTER_H
#define I3C_MASTER_H
#include <asm/bitsperlong.h>
#include <linux/bitops.h>
#include <linux/i2c.h>
#include <linux/i3c/ccc.h>
#include <linux/i3c/device.h>
#include <linux/rwsem.h>
#include <linux/spinlock.h>
#include <linux/workqueue.h>
#define I3C_HOT_JOIN_ADDR 0x2
#define I3C_BROADCAST_ADDR 0x7e
#define I3C_MAX_ADDR GENMASK(6, 0)
struct i3c_master_controller;
struct i3c_bus;
struct i2c_device;
struct i3c_device;
/**
* struct i3c_i2c_dev_desc - Common part of the I3C/I2C device descriptor
* @node: node element used to insert the slot into the I2C or I3C device
* list
* @master: I3C master that instantiated this device. Will be used to do
* I2C/I3C transfers
* @master_priv: master private data assigned to the device. Can be used to
* add master specific information
*
* This structure is describing common I3C/I2C dev information.
*/
struct i3c_i2c_dev_desc {
struct list_head node;
struct i3c_master_controller *master;
void *master_priv;
};
#define I3C_LVR_I2C_INDEX_MASK GENMASK(7, 5)
#define I3C_LVR_I2C_INDEX(x) ((x) << 5)
#define I3C_LVR_I2C_FM_MODE BIT(4)
#define I2C_MAX_ADDR GENMASK(9, 0)
/**
* struct i2c_dev_boardinfo - I2C device board information
* @node: used to insert the boardinfo object in the I2C boardinfo list
* @base: regular I2C board information
* @lvr: LVR (Legacy Virtual Register) needed by the I3C core to know about
* the I2C device limitations
*
* This structure is used to attach board-level information to an I2C device.
* Each I2C device connected on the I3C bus should have one.
*/
struct i2c_dev_boardinfo {
struct list_head node;
struct i2c_board_info base;
u8 lvr;
};
/**
* struct i2c_dev_desc - I2C device descriptor
* @common: common part of the I2C device descriptor
* @boardinfo: pointer to the boardinfo attached to this I2C device
* @dev: I2C device object registered to the I2C framework
*
* Each I2C device connected on the bus will have an i2c_dev_desc.
* This object is created by the core and later attached to the controller
* using &struct_i3c_master_controller->ops->attach_i2c_dev().
*
* &struct_i2c_dev_desc is the internal representation of an I2C device
* connected on an I3C bus. This object is also passed to all
* &struct_i3c_master_controller_ops hooks.
*/
struct i2c_dev_desc {
struct i3c_i2c_dev_desc common;
const struct i2c_dev_boardinfo *boardinfo;
struct i2c_client *dev;
};
/**
* struct i3c_ibi_slot - I3C IBI (In-Band Interrupt) slot
* @work: work associated to this slot. The IBI handler will be called from
* there
* @dev: the I3C device that has generated this IBI
* @len: length of the payload associated to this IBI
* @data: payload buffer
*
* An IBI slot is an object pre-allocated by the controller and used when an
* IBI comes in.
* Every time an IBI comes in, the I3C master driver should find a free IBI
* slot in its IBI slot pool, retrieve the IBI payload and queue the IBI using
* i3c_master_queue_ibi().
*
* How IBI slots are allocated is left to the I3C master driver, though, for
* simple kmalloc-based allocation, the generic IBI slot pool can be used.
*/
struct i3c_ibi_slot {
struct work_struct work;
struct i3c_dev_desc *dev;
unsigned int len;
void *data;
};
/**
* struct i3c_device_ibi_info - IBI information attached to a specific device
* @all_ibis_handled: used to be informed when no more IBIs are waiting to be
* processed. Used by i3c_device_disable_ibi() to wait for
* all IBIs to be dequeued
* @pending_ibis: count the number of pending IBIs. Each pending IBI has its
* work element queued to the controller workqueue
* @max_payload_len: maximum payload length for an IBI coming from this device.
* this value is specified when calling
* i3c_device_request_ibi() and should not change at run
* time. All messages IBIs exceeding this limit should be
* rejected by the master
* @num_slots: number of IBI slots reserved for this device
* @enabled: reflect the IBI status
* @handler: IBI handler specified at i3c_device_request_ibi() call time. This
* handler will be called from the controller workqueue, and as such
* is allowed to sleep (though it is recommended to process the IBI
* as fast as possible to not stall processing of other IBIs queued
* on the same workqueue).
* New I3C messages can be sent from the IBI handler
*
* The &struct_i3c_device_ibi_info object is allocated when
* i3c_device_request_ibi() is called and attached to a specific device. This
* object is here to manage IBIs coming from a specific I3C device.
*
* Note that this structure is the generic view of the IBI management
* infrastructure. I3C master drivers may have their own internal
* representation which they can associate to the device using
* controller-private data.
*/
struct i3c_device_ibi_info {
struct completion all_ibis_handled;
atomic_t pending_ibis;
unsigned int max_payload_len;
unsigned int num_slots;
unsigned int enabled;
void (*handler)(struct i3c_device *dev,
const struct i3c_ibi_payload *payload);
};
/**
* struct i3c_dev_boardinfo - I3C device board information
* @node: used to insert the boardinfo object in the I3C boardinfo list
* @init_dyn_addr: initial dynamic address requested by the FW. We provide no
* guarantee that the device will end up using this address,
* but try our best to assign this specific address to the
* device
* @static_addr: static address the I3C device listen on before it's been
* assigned a dynamic address by the master. Will be used during
* bus initialization to assign it a specific dynamic address
* before starting DAA (Dynamic Address Assignment)
* @pid: I3C Provisional ID exposed by the device. This is a unique identifier
* that may be used to attach boardinfo to i3c_dev_desc when the device
* does not have a static address
* @of_node: optional DT node in case the device has been described in the DT
*
* This structure is used to attach board-level information to an I3C device.
* Not all I3C devices connected on the bus will have a boardinfo. It's only
* needed if you want to attach extra resources to a device or assign it a
* specific dynamic address.
*/
struct i3c_dev_boardinfo {
struct list_head node;
u8 init_dyn_addr;
u8 static_addr;
u64 pid;
struct device_node *of_node;
};
/**
* struct i3c_dev_desc - I3C device descriptor
* @common: common part of the I3C device descriptor
* @info: I3C device information. Will be automatically filled when you create
* your device with i3c_master_add_i3c_dev_locked()
* @ibi_lock: lock used to protect the &struct_i3c_device->ibi
* @ibi: IBI info attached to a device. Should be NULL until
* i3c_device_request_ibi() is called
* @dev: pointer to the I3C device object exposed to I3C device drivers. This
* should never be accessed from I3C master controller drivers. Only core
* code should manipulate it in when updating the dev <-> desc link or
* when propagating IBI events to the driver
* @boardinfo: pointer to the boardinfo attached to this I3C device
*
* Internal representation of an I3C device. This object is only used by the
* core and passed to I3C master controller drivers when they're requested to
* do some operations on the device.
* The core maintains the link between the internal I3C dev descriptor and the
* object exposed to the I3C device drivers (&struct_i3c_device).
*/
struct i3c_dev_desc {
struct i3c_i2c_dev_desc common;
struct i3c_device_info info;
struct mutex ibi_lock;
struct i3c_device_ibi_info *ibi;
struct i3c_device *dev;
const struct i3c_dev_boardinfo *boardinfo;
};
/**
* struct i3c_device - I3C device object
* @dev: device object to register the I3C dev to the device model
* @desc: pointer to an i3c device descriptor object. This link is updated
* every time the I3C device is rediscovered with a different dynamic
* address assigned
* @bus: I3C bus this device is attached to
*
* I3C device object exposed to I3C device drivers. The takes care of linking
* this object to the relevant &struct_i3c_dev_desc one.
* All I3C devs on the I3C bus are represented, including I3C masters. For each
* of them, we have an instance of &struct i3c_device.
*/
struct i3c_device {
struct device dev;
struct i3c_dev_desc *desc;
struct i3c_bus *bus;
};
/*
* The I3C specification says the maximum number of devices connected on the
* bus is 11, but this number depends on external parameters like trace length,
* capacitive load per Device, and the types of Devices present on the Bus.
* I3C master can also have limitations, so this number is just here as a
* reference and should be adjusted on a per-controller/per-board basis.
*/
#define I3C_BUS_MAX_DEVS 11
#define I3C_BUS_MAX_I3C_SCL_RATE 12900000
#define I3C_BUS_TYP_I3C_SCL_RATE 12500000
#define I3C_BUS_I2C_FM_PLUS_SCL_RATE 1000000
#define I3C_BUS_I2C_FM_SCL_RATE 400000
#define I3C_BUS_TLOW_OD_MIN_NS 200
/**
* enum i3c_bus_mode - I3C bus mode
* @I3C_BUS_MODE_PURE: only I3C devices are connected to the bus. No limitation
* expected
* @I3C_BUS_MODE_MIXED_FAST: I2C devices with 50ns spike filter are present on
* the bus. The only impact in this mode is that the
* high SCL pulse has to stay below 50ns to trick I2C
* devices when transmitting I3C frames
* @I3C_BUS_MODE_MIXED_SLOW: I2C devices without 50ns spike filter are present
* on the bus
*/
enum i3c_bus_mode {
I3C_BUS_MODE_PURE,
I3C_BUS_MODE_MIXED_FAST,
I3C_BUS_MODE_MIXED_SLOW,
};
/**
* enum i3c_addr_slot_status - I3C address slot status
* @I3C_ADDR_SLOT_FREE: address is free
* @I3C_ADDR_SLOT_RSVD: address is reserved
* @I3C_ADDR_SLOT_I2C_DEV: address is assigned to an I2C device
* @I3C_ADDR_SLOT_I3C_DEV: address is assigned to an I3C device
* @I3C_ADDR_SLOT_STATUS_MASK: address slot mask
*
* On an I3C bus, addresses are assigned dynamically, and we need to know which
* addresses are free to use and which ones are already assigned.
*
* Addresses marked as reserved are those reserved by the I3C protocol
* (broadcast address, ...).
*/
enum i3c_addr_slot_status {
I3C_ADDR_SLOT_FREE,
I3C_ADDR_SLOT_RSVD,
I3C_ADDR_SLOT_I2C_DEV,
I3C_ADDR_SLOT_I3C_DEV,
I3C_ADDR_SLOT_STATUS_MASK = 3,
};
/**
* struct i3c_bus - I3C bus object
* @cur_master: I3C master currently driving the bus. Since I3C is multi-master
* this can change over the time. Will be used to let a master
* know whether it needs to request bus ownership before sending
* a frame or not
* @id: bus ID. Assigned by the framework when register the bus
* @addrslots: a bitmap with 2-bits per-slot to encode the address status and
* ease the DAA (Dynamic Address Assignment) procedure (see
* &enum i3c_addr_slot_status)
* @mode: bus mode (see &enum i3c_bus_mode)
* @scl_rate.i3c: maximum rate for the clock signal when doing I3C SDR/priv
* transfers
* @scl_rate.i2c: maximum rate for the clock signal when doing I2C transfers
* @scl_rate: SCL signal rate for I3C and I2C mode
* @devs.i3c: contains a list of I3C device descriptors representing I3C
* devices connected on the bus and successfully attached to the
* I3C master
* @devs.i2c: contains a list of I2C device descriptors representing I2C
* devices connected on the bus and successfully attached to the
* I3C master
* @devs: 2 lists containing all I3C/I2C devices connected to the bus
* @lock: read/write lock on the bus. This is needed to protect against
* operations that have an impact on the whole bus and the devices
* connected to it. For example, when asking slaves to drop their
* dynamic address (RSTDAA CCC), we need to make sure no one is trying
* to send I3C frames to these devices.
* Note that this lock does not protect against concurrency between
* devices: several drivers can send different I3C/I2C frames through
* the same master in parallel. This is the responsibility of the
* master to guarantee that frames are actually sent sequentially and
* not interlaced
*
* The I3C bus is represented with its own object and not implicitly described
* by the I3C master to cope with the multi-master functionality, where one bus
* can be shared amongst several masters, each of them requesting bus ownership
* when they need to.
*/
struct i3c_bus {
struct i3c_dev_desc *cur_master;
int id;
unsigned long addrslots[((I2C_MAX_ADDR + 1) * 2) / BITS_PER_LONG];
enum i3c_bus_mode mode;
struct {
unsigned long i3c;
unsigned long i2c;
} scl_rate;
struct {
struct list_head i3c;
struct list_head i2c;
} devs;
struct rw_semaphore lock;
};
/**
* struct i3c_master_controller_ops - I3C master methods
* @bus_init: hook responsible for the I3C bus initialization. You should at
* least call master_set_info() from there and set the bus mode.
* You can also put controller specific initialization in there.
* This method is mandatory.
* @bus_cleanup: cleanup everything done in
* &i3c_master_controller_ops->bus_init().
* This method is optional.
* @attach_i3c_dev: called every time an I3C device is attached to the bus. It
* can be after a DAA or when a device is statically declared
* by the FW, in which case it will only have a static address
* and the dynamic address will be 0.
* When this function is called, device information have not
* been retrieved yet.
* This is a good place to attach master controller specific
* data to I3C devices.
* This method is optional.
* @reattach_i3c_dev: called every time an I3C device has its addressed
* changed. It can be because the device has been powered
* down and has lost its address, or it can happen when a
* device had a static address and has been assigned a
* dynamic address with SETDASA.
* This method is optional.
* @detach_i3c_dev: called when an I3C device is detached from the bus. Usually
* happens when the master device is unregistered.
* This method is optional.
* @do_daa: do a DAA (Dynamic Address Assignment) procedure. This is procedure
* should send an ENTDAA CCC command and then add all devices
* discovered sure the DAA using i3c_master_add_i3c_dev_locked().
* Add devices added with i3c_master_add_i3c_dev_locked() will then be
* attached or re-attached to the controller.
* This method is mandatory.
* @supports_ccc_cmd: should return true if the CCC command is supported, false
* otherwise.
* This method is optional, if not provided the core assumes
* all CCC commands are supported.
* @send_ccc_cmd: send a CCC command
* This method is mandatory.
* @priv_xfers: do one or several private I3C SDR transfers
* This method is mandatory.
* @attach_i2c_dev: called every time an I2C device is attached to the bus.
* This is a good place to attach master controller specific
* data to I2C devices.
* This method is optional.
* @detach_i2c_dev: called when an I2C device is detached from the bus. Usually
* happens when the master device is unregistered.
* This method is optional.
* @i2c_xfers: do one or several I2C transfers. Note that, unlike i3c
* transfers, the core does not guarantee that buffers attached to
* the transfers are DMA-safe. If drivers want to have DMA-safe
* buffers, they should use the i2c_get_dma_safe_msg_buf()
* and i2c_put_dma_safe_msg_buf() helpers provided by the I2C
* framework.
* This method is mandatory.
* @i2c_funcs: expose the supported I2C functionalities.
* This method is mandatory.
* @request_ibi: attach an IBI handler to an I3C device. This implies defining
* an IBI handler and the constraints of the IBI (maximum payload
* length and number of pre-allocated slots).
* Some controllers support less IBI-capable devices than regular
* devices, so this method might return -%EBUSY if there's no
* more space for an extra IBI registration
* This method is optional.
* @free_ibi: free an IBI previously requested with ->request_ibi(). The IBI
* should have been disabled with ->disable_irq() prior to that
* This method is mandatory only if ->request_ibi is not NULL.
* @enable_ibi: enable the IBI. Only valid if ->request_ibi() has been called
* prior to ->enable_ibi(). The controller should first enable
* the IBI on the controller end (for example, unmask the hardware
* IRQ) and then send the ENEC CCC command (with the IBI flag set)
* to the I3C device.
* This method is mandatory only if ->request_ibi is not NULL.
* @disable_ibi: disable an IBI. First send the DISEC CCC command with the IBI
* flag set and then deactivate the hardware IRQ on the
* controller end.
* This method is mandatory only if ->request_ibi is not NULL.
* @recycle_ibi_slot: recycle an IBI slot. Called every time an IBI has been
* processed by its handler. The IBI slot should be put back
* in the IBI slot pool so that the controller can re-use it
* for a future IBI
* This method is mandatory only if ->request_ibi is not
* NULL.
*/
struct i3c_master_controller_ops {
int (*bus_init)(struct i3c_master_controller *master);
void (*bus_cleanup)(struct i3c_master_controller *master);
int (*attach_i3c_dev)(struct i3c_dev_desc *dev);
int (*reattach_i3c_dev)(struct i3c_dev_desc *dev, u8 old_dyn_addr);
void (*detach_i3c_dev)(struct i3c_dev_desc *dev);
int (*do_daa)(struct i3c_master_controller *master);
bool (*supports_ccc_cmd)(struct i3c_master_controller *master,
const struct i3c_ccc_cmd *cmd);
int (*send_ccc_cmd)(struct i3c_master_controller *master,
struct i3c_ccc_cmd *cmd);
int (*priv_xfers)(struct i3c_dev_desc *dev,
struct i3c_priv_xfer *xfers,
int nxfers);
int (*attach_i2c_dev)(struct i2c_dev_desc *dev);
void (*detach_i2c_dev)(struct i2c_dev_desc *dev);
int (*i2c_xfers)(struct i2c_dev_desc *dev,
const struct i2c_msg *xfers, int nxfers);
u32 (*i2c_funcs)(struct i3c_master_controller *master);
int (*request_ibi)(struct i3c_dev_desc *dev,
const struct i3c_ibi_setup *req);
void (*free_ibi)(struct i3c_dev_desc *dev);
int (*enable_ibi)(struct i3c_dev_desc *dev);
int (*disable_ibi)(struct i3c_dev_desc *dev);
void (*recycle_ibi_slot)(struct i3c_dev_desc *dev,
struct i3c_ibi_slot *slot);
};
/**
* struct i3c_master_controller - I3C master controller object
* @dev: device to be registered to the device-model
* @this: an I3C device object representing this master. This device will be
* added to the list of I3C devs available on the bus
* @i2c: I2C adapter used for backward compatibility. This adapter is
* registered to the I2C subsystem to be as transparent as possible to
* existing I2C drivers
* @ops: master operations. See &struct i3c_master_controller_ops
* @secondary: true if the master is a secondary master
* @init_done: true when the bus initialization is done
* @boardinfo.i3c: list of I3C boardinfo objects
* @boardinfo.i2c: list of I2C boardinfo objects
* @boardinfo: board-level information attached to devices connected on the bus
* @bus: I3C bus exposed by this master
* @wq: workqueue used to execute IBI handlers. Can also be used by master
* drivers if they need to postpone operations that need to take place
* in a thread context. Typical examples are Hot Join processing which
* requires taking the bus lock in maintenance, which in turn, can only
* be done from a sleep-able context
*
* A &struct i3c_master_controller has to be registered to the I3C subsystem
* through i3c_master_register(). None of &struct i3c_master_controller fields
* should be set manually, just pass appropriate values to
* i3c_master_register().
*/
struct i3c_master_controller {
struct device dev;
struct i3c_dev_desc *this;
struct i2c_adapter i2c;
const struct i3c_master_controller_ops *ops;
unsigned int secondary : 1;
unsigned int init_done : 1;
struct {
struct list_head i3c;
struct list_head i2c;
} boardinfo;
struct i3c_bus bus;
struct workqueue_struct *wq;
};
/**
* i3c_bus_for_each_i2cdev() - iterate over all I2C devices present on the bus
* @bus: the I3C bus
* @dev: an I2C device descriptor pointer updated to point to the current slot
* at each iteration of the loop
*
* Iterate over all I2C devs present on the bus.
*/
#define i3c_bus_for_each_i2cdev(bus, dev) \
list_for_each_entry(dev, &(bus)->devs.i2c, common.node)
/**
* i3c_bus_for_each_i3cdev() - iterate over all I3C devices present on the bus
* @bus: the I3C bus
* @dev: and I3C device descriptor pointer updated to point to the current slot
* at each iteration of the loop
*
* Iterate over all I3C devs present on the bus.
*/
#define i3c_bus_for_each_i3cdev(bus, dev) \
list_for_each_entry(dev, &(bus)->devs.i3c, common.node)
int i3c_master_do_i2c_xfers(struct i3c_master_controller *master,
const struct i2c_msg *xfers,
int nxfers);
int i3c_master_disec_locked(struct i3c_master_controller *master, u8 addr,
u8 evts);
int i3c_master_enec_locked(struct i3c_master_controller *master, u8 addr,
u8 evts);
int i3c_master_entdaa_locked(struct i3c_master_controller *master);
int i3c_master_defslvs_locked(struct i3c_master_controller *master);
int i3c_master_get_free_addr(struct i3c_master_controller *master,
u8 start_addr);
int i3c_master_add_i3c_dev_locked(struct i3c_master_controller *master,
u8 addr);
int i3c_master_do_daa(struct i3c_master_controller *master);
int i3c_master_set_info(struct i3c_master_controller *master,
const struct i3c_device_info *info);
int i3c_master_register(struct i3c_master_controller *master,
struct device *parent,
const struct i3c_master_controller_ops *ops,
bool secondary);
int i3c_master_unregister(struct i3c_master_controller *master);
/**
* i3c_dev_get_master_data() - get master private data attached to an I3C
* device descriptor
* @dev: the I3C device descriptor to get private data from
*
* Return: the private data previously attached with i3c_dev_set_master_data()
* or NULL if no data has been attached to the device.
*/
static inline void *i3c_dev_get_master_data(const struct i3c_dev_desc *dev)
{
return dev->common.master_priv;
}
/**
* i3c_dev_set_master_data() - attach master private data to an I3C device
* descriptor
* @dev: the I3C device descriptor to attach private data to
* @data: private data
*
* This functions allows a master controller to attach per-device private data
* which can then be retrieved with i3c_dev_get_master_data().
*/
static inline void i3c_dev_set_master_data(struct i3c_dev_desc *dev,
void *data)
{
dev->common.master_priv = data;
}
/**
* i2c_dev_get_master_data() - get master private data attached to an I2C
* device descriptor
* @dev: the I2C device descriptor to get private data from
*
* Return: the private data previously attached with i2c_dev_set_master_data()
* or NULL if no data has been attached to the device.
*/
static inline void *i2c_dev_get_master_data(const struct i2c_dev_desc *dev)
{
return dev->common.master_priv;
}
/**
* i2c_dev_set_master_data() - attach master private data to an I2C device
* descriptor
* @dev: the I2C device descriptor to attach private data to
* @data: private data
*
* This functions allows a master controller to attach per-device private data
* which can then be retrieved with i2c_device_get_master_data().
*/
static inline void i2c_dev_set_master_data(struct i2c_dev_desc *dev,
void *data)
{
dev->common.master_priv = data;
}
/**
* i3c_dev_get_master() - get master used to communicate with a device
* @dev: I3C dev
*
* Return: the master controller driving @dev
*/
static inline struct i3c_master_controller *
i3c_dev_get_master(struct i3c_dev_desc *dev)
{
return dev->common.master;
}
/**
* i2c_dev_get_master() - get master used to communicate with a device
* @dev: I2C dev
*
* Return: the master controller driving @dev
*/
static inline struct i3c_master_controller *
i2c_dev_get_master(struct i2c_dev_desc *dev)
{
return dev->common.master;
}
/**
* i3c_master_get_bus() - get the bus attached to a master
* @master: master object
*
* Return: the I3C bus @master is connected to
*/
static inline struct i3c_bus *
i3c_master_get_bus(struct i3c_master_controller *master)
{
return &master->bus;
}
struct i3c_generic_ibi_pool;
struct i3c_generic_ibi_pool *
i3c_generic_ibi_alloc_pool(struct i3c_dev_desc *dev,
const struct i3c_ibi_setup *req);
void i3c_generic_ibi_free_pool(struct i3c_generic_ibi_pool *pool);
struct i3c_ibi_slot *
i3c_generic_ibi_get_free_slot(struct i3c_generic_ibi_pool *pool);
void i3c_generic_ibi_recycle_slot(struct i3c_generic_ibi_pool *pool,
struct i3c_ibi_slot *slot);
void i3c_master_queue_ibi(struct i3c_dev_desc *dev, struct i3c_ibi_slot *slot);
struct i3c_ibi_slot *i3c_master_get_free_ibi_slot(struct i3c_dev_desc *dev);
#endif /* I3C_MASTER_H */

17
include/linux/mod_devicetable.h
View File

@@ -448,6 +448,23 @@ struct pci_epf_device_id {
kernel_ulong_t driver_data;
};
/* i3c */
#define I3C_MATCH_DCR 0x1
#define I3C_MATCH_MANUF 0x2
#define I3C_MATCH_PART 0x4
#define I3C_MATCH_EXTRA_INFO 0x8
struct i3c_device_id {
__u8 match_flags;
__u8 dcr;
__u16 manuf_id;
__u16 part_id;
__u16 extra_info;
const void *data;
};
/* spi */
#define SPI_NAME_SIZE 32