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Merge tag 'soc-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Browse Source 
Pull ARM SoC platform changes from Olof Johansson:
 "This is the bulk of new SoC enablement and other platform changes for
  3.17:

   - Samsung S5PV210 has been converted to DT and multiplatform
   - Clock drivers and bindings for some of the lower-end i.MX 1/2
     platforms
   - Kirkwood, one of the popular Marvell platforms, is folded into the
     mvebu platform code, removing mach-kirkwood
   - Hwmod data for TI AM43xx and DRA7 platforms
   - More additions of Renesas shmobile platform support
   - Removal of plat-samsung contents that can be removed with S5PV210
     being multiplatform/DT-enabled and the other two old platforms
     being removed

  New platforms (most with only basic support right now):

   - Hisilicon X5HD2 settop box chipset is introduced
   - Mediatek MT6589 (mobile chipset) is introduced
   - Broadcom BCM7xxx settop box chipset is introduced

  + as usual a lot other pieces all over the platform code"

* tag 'soc-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (240 commits)
  ARM: hisi: remove smp from machine descriptor
  power: reset: move hisilicon reboot code
  ARM: dts: Add hix5hd2-dkb dts file.
  ARM: debug: Rename Hi3716 to HIX5HD2
  ARM: hisi: enable hix5hd2 SoC
  ARM: hisi: add ARCH_HISI
  MAINTAINERS: add entry for Broadcom ARM STB architecture
  ARM: brcmstb: select GISB arbiter and interrupt drivers
  ARM: brcmstb: add infrastructure for ARM-based Broadcom STB SoCs
  ARM: configs: enable SMP in bcm_defconfig
  ARM: add SMP support for Broadcom mobile SoCs
  Documentation: arm: misc updates to Marvell EBU SoC status
  Documentation: arm: add URLs to public datasheets for the Marvell Armada XP SoC
  ARM: mvebu: fix build without platforms selected
  ARM: mvebu: add cpuidle support for Armada 38x
  ARM: mvebu: add cpuidle support for Armada 370
  cpuidle: mvebu: add Armada 38x support
  cpuidle: mvebu: add Armada 370 support
  cpuidle: mvebu: rename the driver from armada-370-xp to mvebu-v7
  ARM: mvebu: export the SCU address
  ...
This commit is contained in:
Linus Torvalds
2014-08-08 11:14:29 -07:00
parent 44c916d58b c2fff85e21
commit b3345d7c57
407 changed files with 11492 additions and 19495 deletions
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40
include/dt-bindings/clock/imx1-clock.h Normal file
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/*
* Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __DT_BINDINGS_CLOCK_IMX1_H
#define __DT_BINDINGS_CLOCK_IMX1_H
#define IMX1_CLK_DUMMY 0
#define IMX1_CLK_CLK32 1
#define IMX1_CLK_CLK16M_EXT 2
#define IMX1_CLK_CLK16M 3
#define IMX1_CLK_CLK32_PREMULT 4
#define IMX1_CLK_PREM 5
#define IMX1_CLK_MPLL 6
#define IMX1_CLK_MPLL_GATE 7
#define IMX1_CLK_SPLL 8
#define IMX1_CLK_SPLL_GATE 9
#define IMX1_CLK_MCU 10
#define IMX1_CLK_FCLK 11
#define IMX1_CLK_HCLK 12
#define IMX1_CLK_CLK48M 13
#define IMX1_CLK_PER1 14
#define IMX1_CLK_PER2 15
#define IMX1_CLK_PER3 16
#define IMX1_CLK_CLKO 17
#define IMX1_CLK_UART3_GATE 18
#define IMX1_CLK_SSI2_GATE 19
#define IMX1_CLK_BROM_GATE 20
#define IMX1_CLK_DMA_GATE 21
#define IMX1_CLK_CSI_GATE 22
#define IMX1_CLK_MMA_GATE 23
#define IMX1_CLK_USBD_GATE 24
#define IMX1_CLK_MAX 25
#endif

80
include/dt-bindings/clock/imx21-clock.h Normal file
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/*
* Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __DT_BINDINGS_CLOCK_IMX21_H
#define __DT_BINDINGS_CLOCK_IMX21_H
#define IMX21_CLK_DUMMY 0
#define IMX21_CLK_CKIL 1
#define IMX21_CLK_CKIH 2
#define IMX21_CLK_FPM 3
#define IMX21_CLK_CKIH_DIV1P5 4
#define IMX21_CLK_MPLL_GATE 5
#define IMX21_CLK_SPLL_GATE 6
#define IMX21_CLK_FPM_GATE 7
#define IMX21_CLK_CKIH_GATE 8
#define IMX21_CLK_MPLL_OSC_SEL 9
#define IMX21_CLK_IPG 10
#define IMX21_CLK_HCLK 11
#define IMX21_CLK_MPLL_SEL 12
#define IMX21_CLK_SPLL_SEL 13
#define IMX21_CLK_SSI1_SEL 14
#define IMX21_CLK_SSI2_SEL 15
#define IMX21_CLK_USB_DIV 16
#define IMX21_CLK_FCLK 17
#define IMX21_CLK_MPLL 18
#define IMX21_CLK_SPLL 19
#define IMX21_CLK_NFC_DIV 20
#define IMX21_CLK_SSI1_DIV 21
#define IMX21_CLK_SSI2_DIV 22
#define IMX21_CLK_PER1 23
#define IMX21_CLK_PER2 24
#define IMX21_CLK_PER3 25
#define IMX21_CLK_PER4 26
#define IMX21_CLK_UART1_IPG_GATE 27
#define IMX21_CLK_UART2_IPG_GATE 28
#define IMX21_CLK_UART3_IPG_GATE 29
#define IMX21_CLK_UART4_IPG_GATE 30
#define IMX21_CLK_CSPI1_IPG_GATE 31
#define IMX21_CLK_CSPI2_IPG_GATE 32
#define IMX21_CLK_SSI1_GATE 33
#define IMX21_CLK_SSI2_GATE 34
#define IMX21_CLK_SDHC1_IPG_GATE 35
#define IMX21_CLK_SDHC2_IPG_GATE 36
#define IMX21_CLK_GPIO_GATE 37
#define IMX21_CLK_I2C_GATE 38
#define IMX21_CLK_DMA_GATE 39
#define IMX21_CLK_USB_GATE 40
#define IMX21_CLK_EMMA_GATE 41
#define IMX21_CLK_SSI2_BAUD_GATE 42
#define IMX21_CLK_SSI1_BAUD_GATE 43
#define IMX21_CLK_LCDC_IPG_GATE 44
#define IMX21_CLK_NFC_GATE 45
#define IMX21_CLK_LCDC_HCLK_GATE 46
#define IMX21_CLK_PER4_GATE 47
#define IMX21_CLK_BMI_GATE 48
#define IMX21_CLK_USB_HCLK_GATE 49
#define IMX21_CLK_SLCDC_GATE 50
#define IMX21_CLK_SLCDC_HCLK_GATE 51
#define IMX21_CLK_EMMA_HCLK_GATE 52
#define IMX21_CLK_BROM_GATE 53
#define IMX21_CLK_DMA_HCLK_GATE 54
#define IMX21_CLK_CSI_HCLK_GATE 55
#define IMX21_CLK_CSPI3_IPG_GATE 56
#define IMX21_CLK_WDOG_GATE 57
#define IMX21_CLK_GPT1_IPG_GATE 58
#define IMX21_CLK_GPT2_IPG_GATE 59
#define IMX21_CLK_GPT3_IPG_GATE 60
#define IMX21_CLK_PWM_IPG_GATE 61
#define IMX21_CLK_RTC_GATE 62
#define IMX21_CLK_KPP_GATE 63
#define IMX21_CLK_OWIRE_GATE 64
#define IMX21_CLK_MAX 65
#endif

108
include/dt-bindings/clock/imx27-clock.h Normal file
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/*
* Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __DT_BINDINGS_CLOCK_IMX27_H
#define __DT_BINDINGS_CLOCK_IMX27_H
#define IMX27_CLK_DUMMY 0
#define IMX27_CLK_CKIH 1
#define IMX27_CLK_CKIL 2
#define IMX27_CLK_MPLL 3
#define IMX27_CLK_SPLL 4
#define IMX27_CLK_MPLL_MAIN2 5
#define IMX27_CLK_AHB 6
#define IMX27_CLK_IPG 7
#define IMX27_CLK_NFC_DIV 8
#define IMX27_CLK_PER1_DIV 9
#define IMX27_CLK_PER2_DIV 10
#define IMX27_CLK_PER3_DIV 11
#define IMX27_CLK_PER4_DIV 12
#define IMX27_CLK_VPU_SEL 13
#define IMX27_CLK_VPU_DIV 14
#define IMX27_CLK_USB_DIV 15
#define IMX27_CLK_CPU_SEL 16
#define IMX27_CLK_CLKO_SEL 17
#define IMX27_CLK_CPU_DIV 18
#define IMX27_CLK_CLKO_DIV 19
#define IMX27_CLK_SSI1_SEL 20
#define IMX27_CLK_SSI2_SEL 21
#define IMX27_CLK_SSI1_DIV 22
#define IMX27_CLK_SSI2_DIV 23
#define IMX27_CLK_CLKO_EN 24
#define IMX27_CLK_SSI2_IPG_GATE 25
#define IMX27_CLK_SSI1_IPG_GATE 26
#define IMX27_CLK_SLCDC_IPG_GATE 27
#define IMX27_CLK_SDHC3_IPG_GATE 28
#define IMX27_CLK_SDHC2_IPG_GATE 29
#define IMX27_CLK_SDHC1_IPG_GATE 30
#define IMX27_CLK_SCC_IPG_GATE 31
#define IMX27_CLK_SAHARA_IPG_GATE 32
#define IMX27_CLK_RTC_IPG_GATE 33
#define IMX27_CLK_PWM_IPG_GATE 34
#define IMX27_CLK_OWIRE_IPG_GATE 35
#define IMX27_CLK_LCDC_IPG_GATE 36
#define IMX27_CLK_KPP_IPG_GATE 37
#define IMX27_CLK_IIM_IPG_GATE 38
#define IMX27_CLK_I2C2_IPG_GATE 39
#define IMX27_CLK_I2C1_IPG_GATE 40
#define IMX27_CLK_GPT6_IPG_GATE 41
#define IMX27_CLK_GPT5_IPG_GATE 42
#define IMX27_CLK_GPT4_IPG_GATE 43
#define IMX27_CLK_GPT3_IPG_GATE 44
#define IMX27_CLK_GPT2_IPG_GATE 45
#define IMX27_CLK_GPT1_IPG_GATE 46
#define IMX27_CLK_GPIO_IPG_GATE 47
#define IMX27_CLK_FEC_IPG_GATE 48
#define IMX27_CLK_EMMA_IPG_GATE 49
#define IMX27_CLK_DMA_IPG_GATE 50
#define IMX27_CLK_CSPI3_IPG_GATE 51
#define IMX27_CLK_CSPI2_IPG_GATE 52
#define IMX27_CLK_CSPI1_IPG_GATE 53
#define IMX27_CLK_NFC_BAUD_GATE 54
#define IMX27_CLK_SSI2_BAUD_GATE 55
#define IMX27_CLK_SSI1_BAUD_GATE 56
#define IMX27_CLK_VPU_BAUD_GATE 57
#define IMX27_CLK_PER4_GATE 58
#define IMX27_CLK_PER3_GATE 59
#define IMX27_CLK_PER2_GATE 60
#define IMX27_CLK_PER1_GATE 61
#define IMX27_CLK_USB_AHB_GATE 62
#define IMX27_CLK_SLCDC_AHB_GATE 63
#define IMX27_CLK_SAHARA_AHB_GATE 64
#define IMX27_CLK_LCDC_AHB_GATE 65
#define IMX27_CLK_VPU_AHB_GATE 66
#define IMX27_CLK_FEC_AHB_GATE 67
#define IMX27_CLK_EMMA_AHB_GATE 68
#define IMX27_CLK_EMI_AHB_GATE 69
#define IMX27_CLK_DMA_AHB_GATE 70
#define IMX27_CLK_CSI_AHB_GATE 71
#define IMX27_CLK_BROM_AHB_GATE 72
#define IMX27_CLK_ATA_AHB_GATE 73
#define IMX27_CLK_WDOG_IPG_GATE 74
#define IMX27_CLK_USB_IPG_GATE 75
#define IMX27_CLK_UART6_IPG_GATE 76
#define IMX27_CLK_UART5_IPG_GATE 77
#define IMX27_CLK_UART4_IPG_GATE 78
#define IMX27_CLK_UART3_IPG_GATE 79
#define IMX27_CLK_UART2_IPG_GATE 80
#define IMX27_CLK_UART1_IPG_GATE 81
#define IMX27_CLK_CKIH_DIV1P5 82
#define IMX27_CLK_FPM 83
#define IMX27_CLK_MPLL_OSC_SEL 84
#define IMX27_CLK_MPLL_SEL 85
#define IMX27_CLK_SPLL_GATE 86
#define IMX27_CLK_MSHC_DIV 87
#define IMX27_CLK_RTIC_IPG_GATE 88
#define IMX27_CLK_MSHC_IPG_GATE 89
#define IMX27_CLK_RTIC_AHB_GATE 90
#define IMX27_CLK_MSHC_BAUD_GATE 91
#define IMX27_CLK_CKIH_GATE 92
#define IMX27_CLK_MAX 93
#endif

224
include/dt-bindings/clock/imx6qdl-clock.h Normal file
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/*
* Copyright 2014 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __DT_BINDINGS_CLOCK_IMX6QDL_H
#define __DT_BINDINGS_CLOCK_IMX6QDL_H
#define IMX6QDL_CLK_DUMMY 0
#define IMX6QDL_CLK_CKIL 1
#define IMX6QDL_CLK_CKIH 2
#define IMX6QDL_CLK_OSC 3
#define IMX6QDL_CLK_PLL2_PFD0_352M 4
#define IMX6QDL_CLK_PLL2_PFD1_594M 5
#define IMX6QDL_CLK_PLL2_PFD2_396M 6
#define IMX6QDL_CLK_PLL3_PFD0_720M 7
#define IMX6QDL_CLK_PLL3_PFD1_540M 8
#define IMX6QDL_CLK_PLL3_PFD2_508M 9
#define IMX6QDL_CLK_PLL3_PFD3_454M 10
#define IMX6QDL_CLK_PLL2_198M 11
#define IMX6QDL_CLK_PLL3_120M 12
#define IMX6QDL_CLK_PLL3_80M 13
#define IMX6QDL_CLK_PLL3_60M 14
#define IMX6QDL_CLK_TWD 15
#define IMX6QDL_CLK_STEP 16
#define IMX6QDL_CLK_PLL1_SW 17
#define IMX6QDL_CLK_PERIPH_PRE 18
#define IMX6QDL_CLK_PERIPH2_PRE 19
#define IMX6QDL_CLK_PERIPH_CLK2_SEL 20
#define IMX6QDL_CLK_PERIPH2_CLK2_SEL 21
#define IMX6QDL_CLK_AXI_SEL 22
#define IMX6QDL_CLK_ESAI_SEL 23
#define IMX6QDL_CLK_ASRC_SEL 24
#define IMX6QDL_CLK_SPDIF_SEL 25
#define IMX6QDL_CLK_GPU2D_AXI 26
#define IMX6QDL_CLK_GPU3D_AXI 27
#define IMX6QDL_CLK_GPU2D_CORE_SEL 28
#define IMX6QDL_CLK_GPU3D_CORE_SEL 29
#define IMX6QDL_CLK_GPU3D_SHADER_SEL 30
#define IMX6QDL_CLK_IPU1_SEL 31
#define IMX6QDL_CLK_IPU2_SEL 32
#define IMX6QDL_CLK_LDB_DI0_SEL 33
#define IMX6QDL_CLK_LDB_DI1_SEL 34
#define IMX6QDL_CLK_IPU1_DI0_PRE_SEL 35
#define IMX6QDL_CLK_IPU1_DI1_PRE_SEL 36
#define IMX6QDL_CLK_IPU2_DI0_PRE_SEL 37
#define IMX6QDL_CLK_IPU2_DI1_PRE_SEL 38
#define IMX6QDL_CLK_IPU1_DI0_SEL 39
#define IMX6QDL_CLK_IPU1_DI1_SEL 40
#define IMX6QDL_CLK_IPU2_DI0_SEL 41
#define IMX6QDL_CLK_IPU2_DI1_SEL 42
#define IMX6QDL_CLK_HSI_TX_SEL 43
#define IMX6QDL_CLK_PCIE_AXI_SEL 44
#define IMX6QDL_CLK_SSI1_SEL 45
#define IMX6QDL_CLK_SSI2_SEL 46
#define IMX6QDL_CLK_SSI3_SEL 47
#define IMX6QDL_CLK_USDHC1_SEL 48
#define IMX6QDL_CLK_USDHC2_SEL 49
#define IMX6QDL_CLK_USDHC3_SEL 50
#define IMX6QDL_CLK_USDHC4_SEL 51
#define IMX6QDL_CLK_ENFC_SEL 52
#define IMX6QDL_CLK_EMI_SEL 53
#define IMX6QDL_CLK_EMI_SLOW_SEL 54
#define IMX6QDL_CLK_VDO_AXI_SEL 55
#define IMX6QDL_CLK_VPU_AXI_SEL 56
#define IMX6QDL_CLK_CKO1_SEL 57
#define IMX6QDL_CLK_PERIPH 58
#define IMX6QDL_CLK_PERIPH2 59
#define IMX6QDL_CLK_PERIPH_CLK2 60
#define IMX6QDL_CLK_PERIPH2_CLK2 61
#define IMX6QDL_CLK_IPG 62
#define IMX6QDL_CLK_IPG_PER 63
#define IMX6QDL_CLK_ESAI_PRED 64
#define IMX6QDL_CLK_ESAI_PODF 65
#define IMX6QDL_CLK_ASRC_PRED 66
#define IMX6QDL_CLK_ASRC_PODF 67
#define IMX6QDL_CLK_SPDIF_PRED 68
#define IMX6QDL_CLK_SPDIF_PODF 69
#define IMX6QDL_CLK_CAN_ROOT 70
#define IMX6QDL_CLK_ECSPI_ROOT 71
#define IMX6QDL_CLK_GPU2D_CORE_PODF 72
#define IMX6QDL_CLK_GPU3D_CORE_PODF 73
#define IMX6QDL_CLK_GPU3D_SHADER 74
#define IMX6QDL_CLK_IPU1_PODF 75
#define IMX6QDL_CLK_IPU2_PODF 76
#define IMX6QDL_CLK_LDB_DI0_PODF 77
#define IMX6QDL_CLK_LDB_DI1_PODF 78
#define IMX6QDL_CLK_IPU1_DI0_PRE 79
#define IMX6QDL_CLK_IPU1_DI1_PRE 80
#define IMX6QDL_CLK_IPU2_DI0_PRE 81
#define IMX6QDL_CLK_IPU2_DI1_PRE 82
#define IMX6QDL_CLK_HSI_TX_PODF 83
#define IMX6QDL_CLK_SSI1_PRED 84
#define IMX6QDL_CLK_SSI1_PODF 85
#define IMX6QDL_CLK_SSI2_PRED 86
#define IMX6QDL_CLK_SSI2_PODF 87
#define IMX6QDL_CLK_SSI3_PRED 88
#define IMX6QDL_CLK_SSI3_PODF 89
#define IMX6QDL_CLK_UART_SERIAL_PODF 90
#define IMX6QDL_CLK_USDHC1_PODF 91
#define IMX6QDL_CLK_USDHC2_PODF 92
#define IMX6QDL_CLK_USDHC3_PODF 93
#define IMX6QDL_CLK_USDHC4_PODF 94
#define IMX6QDL_CLK_ENFC_PRED 95
#define IMX6QDL_CLK_ENFC_PODF 96
#define IMX6QDL_CLK_EMI_PODF 97
#define IMX6QDL_CLK_EMI_SLOW_PODF 98
#define IMX6QDL_CLK_VPU_AXI_PODF 99
#define IMX6QDL_CLK_CKO1_PODF 100
#define IMX6QDL_CLK_AXI 101
#define IMX6QDL_CLK_MMDC_CH0_AXI_PODF 102
#define IMX6QDL_CLK_MMDC_CH1_AXI_PODF 103
#define IMX6QDL_CLK_ARM 104
#define IMX6QDL_CLK_AHB 105
#define IMX6QDL_CLK_APBH_DMA 106
#define IMX6QDL_CLK_ASRC 107
#define IMX6QDL_CLK_CAN1_IPG 108
#define IMX6QDL_CLK_CAN1_SERIAL 109
#define IMX6QDL_CLK_CAN2_IPG 110
#define IMX6QDL_CLK_CAN2_SERIAL 111
#define IMX6QDL_CLK_ECSPI1 112
#define IMX6QDL_CLK_ECSPI2 113
#define IMX6QDL_CLK_ECSPI3 114
#define IMX6QDL_CLK_ECSPI4 115
#define IMX6Q_CLK_ECSPI5 116
#define IMX6DL_CLK_I2C4 116
#define IMX6QDL_CLK_ENET 117
#define IMX6QDL_CLK_ESAI 118
#define IMX6QDL_CLK_GPT_IPG 119
#define IMX6QDL_CLK_GPT_IPG_PER 120
#define IMX6QDL_CLK_GPU2D_CORE 121
#define IMX6QDL_CLK_GPU3D_CORE 122
#define IMX6QDL_CLK_HDMI_IAHB 123
#define IMX6QDL_CLK_HDMI_ISFR 124
#define IMX6QDL_CLK_I2C1 125
#define IMX6QDL_CLK_I2C2 126
#define IMX6QDL_CLK_I2C3 127
#define IMX6QDL_CLK_IIM 128
#define IMX6QDL_CLK_ENFC 129
#define IMX6QDL_CLK_IPU1 130
#define IMX6QDL_CLK_IPU1_DI0 131
#define IMX6QDL_CLK_IPU1_DI1 132
#define IMX6QDL_CLK_IPU2 133
#define IMX6QDL_CLK_IPU2_DI0 134
#define IMX6QDL_CLK_LDB_DI0 135
#define IMX6QDL_CLK_LDB_DI1 136
#define IMX6QDL_CLK_IPU2_DI1 137
#define IMX6QDL_CLK_HSI_TX 138
#define IMX6QDL_CLK_MLB 139
#define IMX6QDL_CLK_MMDC_CH0_AXI 140
#define IMX6QDL_CLK_MMDC_CH1_AXI 141
#define IMX6QDL_CLK_OCRAM 142
#define IMX6QDL_CLK_OPENVG_AXI 143
#define IMX6QDL_CLK_PCIE_AXI 144
#define IMX6QDL_CLK_PWM1 145
#define IMX6QDL_CLK_PWM2 146
#define IMX6QDL_CLK_PWM3 147
#define IMX6QDL_CLK_PWM4 148
#define IMX6QDL_CLK_PER1_BCH 149
#define IMX6QDL_CLK_GPMI_BCH_APB 150
#define IMX6QDL_CLK_GPMI_BCH 151
#define IMX6QDL_CLK_GPMI_IO 152
#define IMX6QDL_CLK_GPMI_APB 153
#define IMX6QDL_CLK_SATA 154
#define IMX6QDL_CLK_SDMA 155
#define IMX6QDL_CLK_SPBA 156
#define IMX6QDL_CLK_SSI1 157
#define IMX6QDL_CLK_SSI2 158
#define IMX6QDL_CLK_SSI3 159
#define IMX6QDL_CLK_UART_IPG 160
#define IMX6QDL_CLK_UART_SERIAL 161
#define IMX6QDL_CLK_USBOH3 162
#define IMX6QDL_CLK_USDHC1 163
#define IMX6QDL_CLK_USDHC2 164
#define IMX6QDL_CLK_USDHC3 165
#define IMX6QDL_CLK_USDHC4 166
#define IMX6QDL_CLK_VDO_AXI 167
#define IMX6QDL_CLK_VPU_AXI 168
#define IMX6QDL_CLK_CKO1 169
#define IMX6QDL_CLK_PLL1_SYS 170
#define IMX6QDL_CLK_PLL2_BUS 171
#define IMX6QDL_CLK_PLL3_USB_OTG 172
#define IMX6QDL_CLK_PLL4_AUDIO 173
#define IMX6QDL_CLK_PLL5_VIDEO 174
#define IMX6QDL_CLK_PLL8_MLB 175
#define IMX6QDL_CLK_PLL7_USB_HOST 176
#define IMX6QDL_CLK_PLL6_ENET 177
#define IMX6QDL_CLK_SSI1_IPG 178
#define IMX6QDL_CLK_SSI2_IPG 179
#define IMX6QDL_CLK_SSI3_IPG 180
#define IMX6QDL_CLK_ROM 181
#define IMX6QDL_CLK_USBPHY1 182
#define IMX6QDL_CLK_USBPHY2 183
#define IMX6QDL_CLK_LDB_DI0_DIV_3_5 184
#define IMX6QDL_CLK_LDB_DI1_DIV_3_5 185
#define IMX6QDL_CLK_SATA_REF 186
#define IMX6QDL_CLK_SATA_REF_100M 187
#define IMX6QDL_CLK_PCIE_REF 188
#define IMX6QDL_CLK_PCIE_REF_125M 189
#define IMX6QDL_CLK_ENET_REF 190
#define IMX6QDL_CLK_USBPHY1_GATE 191
#define IMX6QDL_CLK_USBPHY2_GATE 192
#define IMX6QDL_CLK_PLL4_POST_DIV 193
#define IMX6QDL_CLK_PLL5_POST_DIV 194
#define IMX6QDL_CLK_PLL5_VIDEO_DIV 195
#define IMX6QDL_CLK_EIM_SLOW 196
#define IMX6QDL_CLK_SPDIF 197
#define IMX6QDL_CLK_CKO2_SEL 198
#define IMX6QDL_CLK_CKO2_PODF 199
#define IMX6QDL_CLK_CKO2 200
#define IMX6QDL_CLK_CKO 201
#define IMX6QDL_CLK_VDOA 202
#define IMX6QDL_CLK_PLL4_AUDIO_DIV 203
#define IMX6QDL_CLK_LVDS1_SEL 204
#define IMX6QDL_CLK_LVDS2_SEL 205
#define IMX6QDL_CLK_LVDS1_GATE 206
#define IMX6QDL_CLK_LVDS2_GATE 207
#define IMX6QDL_CLK_ESAI_AHB 208
#define IMX6QDL_CLK_END 209
#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */

34
include/dt-bindings/clock/s5pv210-audss.h Normal file
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@@ -0,0 +1,34 @@
/*
* Copyright (c) 2014 Tomasz Figa <tomasz.figa@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This header provides constants for Samsung audio subsystem
* clock controller.
*
* The constants defined in this header are being used in dts
* and s5pv210 audss driver.
*/
#ifndef _DT_BINDINGS_CLOCK_S5PV210_AUDSS_H
#define _DT_BINDINGS_CLOCK_S5PV210_AUDSS_H
#define CLK_MOUT_AUDSS 0
#define CLK_MOUT_I2S_A 1
#define CLK_DOUT_AUD_BUS 2
#define CLK_DOUT_I2S_A 3
#define CLK_I2S 4
#define CLK_HCLK_I2S 5
#define CLK_HCLK_UART 6
#define CLK_HCLK_HWA 7
#define CLK_HCLK_DMA 8
#define CLK_HCLK_BUF 9
#define CLK_HCLK_RP 10
#define AUDSS_MAX_CLKS 11
#endif

239
include/dt-bindings/clock/s5pv210.h Normal file
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/*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* Author: Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Device Tree binding constants for Samsung S5PV210 clock controller.
*/
#ifndef _DT_BINDINGS_CLOCK_S5PV210_H
#define _DT_BINDINGS_CLOCK_S5PV210_H
/* Core clocks. */
#define FIN_PLL 1
#define FOUT_APLL 2
#define FOUT_MPLL 3
#define FOUT_EPLL 4
#define FOUT_VPLL 5
/* Muxes. */
#define MOUT_FLASH 6
#define MOUT_PSYS 7
#define MOUT_DSYS 8
#define MOUT_MSYS 9
#define MOUT_VPLL 10
#define MOUT_EPLL 11
#define MOUT_MPLL 12
#define MOUT_APLL 13
#define MOUT_VPLLSRC 14
#define MOUT_CSIS 15
#define MOUT_FIMD 16
#define MOUT_CAM1 17
#define MOUT_CAM0 18
#define MOUT_DAC 19
#define MOUT_MIXER 20
#define MOUT_HDMI 21
#define MOUT_G2D 22
#define MOUT_MFC 23
#define MOUT_G3D 24
#define MOUT_FIMC2 25
#define MOUT_FIMC1 26
#define MOUT_FIMC0 27
#define MOUT_UART3 28
#define MOUT_UART2 29
#define MOUT_UART1 30
#define MOUT_UART0 31
#define MOUT_MMC3 32
#define MOUT_MMC2 33
#define MOUT_MMC1 34
#define MOUT_MMC0 35
#define MOUT_PWM 36
#define MOUT_SPI0 37
#define MOUT_SPI1 38
#define MOUT_DMC0 39
#define MOUT_PWI 40
#define MOUT_HPM 41
#define MOUT_SPDIF 42
#define MOUT_AUDIO2 43
#define MOUT_AUDIO1 44
#define MOUT_AUDIO0 45
/* Dividers. */
#define DOUT_PCLKP 46
#define DOUT_HCLKP 47
#define DOUT_PCLKD 48
#define DOUT_HCLKD 49
#define DOUT_PCLKM 50
#define DOUT_HCLKM 51
#define DOUT_A2M 52
#define DOUT_APLL 53
#define DOUT_CSIS 54
#define DOUT_FIMD 55
#define DOUT_CAM1 56
#define DOUT_CAM0 57
#define DOUT_TBLK 58
#define DOUT_G2D 59
#define DOUT_MFC 60
#define DOUT_G3D 61
#define DOUT_FIMC2 62
#define DOUT_FIMC1 63
#define DOUT_FIMC0 64
#define DOUT_UART3 65
#define DOUT_UART2 66
#define DOUT_UART1 67
#define DOUT_UART0 68
#define DOUT_MMC3 69
#define DOUT_MMC2 70
#define DOUT_MMC1 71
#define DOUT_MMC0 72
#define DOUT_PWM 73
#define DOUT_SPI1 74
#define DOUT_SPI0 75
#define DOUT_DMC0 76
#define DOUT_PWI 77
#define DOUT_HPM 78
#define DOUT_COPY 79
#define DOUT_FLASH 80
#define DOUT_AUDIO2 81
#define DOUT_AUDIO1 82
#define DOUT_AUDIO0 83
#define DOUT_DPM 84
#define DOUT_DVSEM 85
/* Gates */
#define SCLK_FIMC 86
#define CLK_CSIS 87
#define CLK_ROTATOR 88
#define CLK_FIMC2 89
#define CLK_FIMC1 90
#define CLK_FIMC0 91
#define CLK_MFC 92
#define CLK_G2D 93
#define CLK_G3D 94
#define CLK_IMEM 95
#define CLK_PDMA1 96
#define CLK_PDMA0 97
#define CLK_MDMA 98
#define CLK_DMC1 99
#define CLK_DMC0 100
#define CLK_NFCON 101
#define CLK_SROMC 102
#define CLK_CFCON 103
#define CLK_NANDXL 104
#define CLK_USB_HOST 105
#define CLK_USB_OTG 106
#define CLK_HDMI 107
#define CLK_TVENC 108
#define CLK_MIXER 109
#define CLK_VP 110
#define CLK_DSIM 111
#define CLK_FIMD 112
#define CLK_TZIC3 113
#define CLK_TZIC2 114
#define CLK_TZIC1 115
#define CLK_TZIC0 116
#define CLK_VIC3 117
#define CLK_VIC2 118
#define CLK_VIC1 119
#define CLK_VIC0 120
#define CLK_TSI 121
#define CLK_HSMMC3 122
#define CLK_HSMMC2 123
#define CLK_HSMMC1 124
#define CLK_HSMMC0 125
#define CLK_JTAG 126
#define CLK_MODEMIF 127
#define CLK_CORESIGHT 128
#define CLK_SDM 129
#define CLK_SECSS 130
#define CLK_PCM2 131
#define CLK_PCM1 132
#define CLK_PCM0 133
#define CLK_SYSCON 134
#define CLK_GPIO 135
#define CLK_TSADC 136
#define CLK_PWM 137
#define CLK_WDT 138
#define CLK_KEYIF 139
#define CLK_UART3 140
#define CLK_UART2 141
#define CLK_UART1 142
#define CLK_UART0 143
#define CLK_SYSTIMER 144
#define CLK_RTC 145
#define CLK_SPI1 146
#define CLK_SPI0 147
#define CLK_I2C_HDMI_PHY 148
#define CLK_I2C1 149
#define CLK_I2C2 150
#define CLK_I2C0 151
#define CLK_I2S1 152
#define CLK_I2S2 153
#define CLK_I2S0 154
#define CLK_AC97 155
#define CLK_SPDIF 156
#define CLK_TZPC3 157
#define CLK_TZPC2 158
#define CLK_TZPC1 159
#define CLK_TZPC0 160
#define CLK_SECKEY 161
#define CLK_IEM_APC 162
#define CLK_IEM_IEC 163
#define CLK_CHIPID 164
#define CLK_JPEG 163
/* Special clocks*/
#define SCLK_PWI 164
#define SCLK_SPDIF 165
#define SCLK_AUDIO2 166
#define SCLK_AUDIO1 167
#define SCLK_AUDIO0 168
#define SCLK_PWM 169
#define SCLK_SPI1 170
#define SCLK_SPI0 171
#define SCLK_UART3 172
#define SCLK_UART2 173
#define SCLK_UART1 174
#define SCLK_UART0 175
#define SCLK_MMC3 176
#define SCLK_MMC2 177
#define SCLK_MMC1 178
#define SCLK_MMC0 179
#define SCLK_FINVPLL 180
#define SCLK_CSIS 181
#define SCLK_FIMD 182
#define SCLK_CAM1 183
#define SCLK_CAM0 184
#define SCLK_DAC 185
#define SCLK_MIXER 186
#define SCLK_HDMI 187
#define SCLK_FIMC2 188
#define SCLK_FIMC1 189
#define SCLK_FIMC0 190
#define SCLK_HDMI27M 191
#define SCLK_HDMIPHY 192
#define SCLK_USBPHY0 193
#define SCLK_USBPHY1 194
/* S5P6442-specific clocks */
#define MOUT_D0SYNC 195
#define MOUT_D1SYNC 196
#define DOUT_MIXER 197
#define CLK_ETB 198
#define CLK_ETM 199
/* CLKOUT */
#define FOUT_APLL_CLKOUT 200
#define FOUT_MPLL_CLKOUT 201
#define DOUT_APLL_CLKOUT 202
#define MOUT_CLKSEL 203
#define DOUT_CLKOUT 204
#define MOUT_CLKOUT 205
/* Total number of clocks. */
#define NR_CLKS 206
#endif /* _DT_BINDINGS_CLOCK_S5PV210_H */

4
include/dt-bindings/clock/vf610-clock.h
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@@ -164,6 +164,8 @@
#define VF610_CLK_DMAMUX1 151
#define VF610_CLK_DMAMUX2 152
#define VF610_CLK_DMAMUX3 153
#define VF610_CLK_END 154
#define VF610_CLK_FLEXCAN0_EN 154
#define VF610_CLK_FLEXCAN1_EN 155
#define VF610_CLK_END 156
#endif /* __DT_BINDINGS_CLOCK_VF610_H */