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Merge tag 'soc-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Browse Source 
Pull ARM SoC platform changes from Olof Johansson:
 "This is the bulk of new SoC enablement and other platform changes for
  3.17:

   - Samsung S5PV210 has been converted to DT and multiplatform
   - Clock drivers and bindings for some of the lower-end i.MX 1/2
     platforms
   - Kirkwood, one of the popular Marvell platforms, is folded into the
     mvebu platform code, removing mach-kirkwood
   - Hwmod data for TI AM43xx and DRA7 platforms
   - More additions of Renesas shmobile platform support
   - Removal of plat-samsung contents that can be removed with S5PV210
     being multiplatform/DT-enabled and the other two old platforms
     being removed

  New platforms (most with only basic support right now):

   - Hisilicon X5HD2 settop box chipset is introduced
   - Mediatek MT6589 (mobile chipset) is introduced
   - Broadcom BCM7xxx settop box chipset is introduced

  + as usual a lot other pieces all over the platform code"

* tag 'soc-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (240 commits)
  ARM: hisi: remove smp from machine descriptor
  power: reset: move hisilicon reboot code
  ARM: dts: Add hix5hd2-dkb dts file.
  ARM: debug: Rename Hi3716 to HIX5HD2
  ARM: hisi: enable hix5hd2 SoC
  ARM: hisi: add ARCH_HISI
  MAINTAINERS: add entry for Broadcom ARM STB architecture
  ARM: brcmstb: select GISB arbiter and interrupt drivers
  ARM: brcmstb: add infrastructure for ARM-based Broadcom STB SoCs
  ARM: configs: enable SMP in bcm_defconfig
  ARM: add SMP support for Broadcom mobile SoCs
  Documentation: arm: misc updates to Marvell EBU SoC status
  Documentation: arm: add URLs to public datasheets for the Marvell Armada XP SoC
  ARM: mvebu: fix build without platforms selected
  ARM: mvebu: add cpuidle support for Armada 38x
  ARM: mvebu: add cpuidle support for Armada 370
  cpuidle: mvebu: add Armada 38x support
  cpuidle: mvebu: add Armada 370 support
  cpuidle: mvebu: rename the driver from armada-370-xp to mvebu-v7
  ARM: mvebu: export the SCU address
  ...
This commit is contained in:
Linus Torvalds
2014-08-08 11:14:29 -07:00
parent 44c916d58b c2fff85e21
commit b3345d7c57
407 changed files with 11492 additions and 19495 deletions
Download Patch File Download Diff File Expand all files Collapse all files

61
arch/arm/mach-exynos/pm.c
View File

@@ -28,7 +28,6 @@
#include <asm/suspend.h>
#include <plat/pm-common.h>
#include <plat/pll.h>
#include <plat/regs-srom.h>
#include <mach/map.h>
@@ -102,11 +101,15 @@ static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
}
#define EXYNOS_BOOT_VECTOR_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \
S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
(sysram_base_addr + 0x24) : S5P_INFORM0))
pmu_base_addr + S5P_INFORM7 : \
(samsung_rev() == EXYNOS4210_REV_1_0 ? \
(sysram_base_addr + 0x24) : \
pmu_base_addr + S5P_INFORM0))
#define EXYNOS_BOOT_VECTOR_FLAG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
(sysram_base_addr + 0x20) : S5P_INFORM1))
pmu_base_addr + S5P_INFORM6 : \
(samsung_rev() == EXYNOS4210_REV_1_0 ? \
(sysram_base_addr + 0x20) : \
pmu_base_addr + S5P_INFORM1))
#define S5P_CHECK_AFTR 0xFCBA0D10
#define S5P_CHECK_SLEEP 0x00000BAD
@@ -114,7 +117,7 @@ static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
static void exynos_set_wakeupmask(long mask)
{
__raw_writel(mask, S5P_WAKEUP_MASK);
pmu_raw_writel(mask, S5P_WAKEUP_MASK);
}
static void exynos_cpu_set_boot_vector(long flags)
@@ -191,27 +194,27 @@ static void exynos_pm_prepare(void)
unsigned int tmp;
/* Set wake-up mask registers */
__raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
__raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
pmu_raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
if (soc_is_exynos5250()) {
s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save));
/* Disable USE_RETENTION of JPEG_MEM_OPTION */
tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION);
tmp = pmu_raw_readl(EXYNOS5_JPEG_MEM_OPTION);
tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
__raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
pmu_raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
}
/* Set value of power down register for sleep mode */
exynos_sys_powerdown_conf(SYS_SLEEP);
__raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
pmu_raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
/* ensure at least INFORM0 has the resume address */
__raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
}
static void exynos_pm_central_suspend(void)
@@ -219,9 +222,9 @@ static void exynos_pm_central_suspend(void)
unsigned long tmp;
/* Setting Central Sequence Register for power down mode */
tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
}
static int exynos_pm_suspend(void)
@@ -233,7 +236,7 @@ static int exynos_pm_suspend(void)
/* Setting SEQ_OPTION register */
tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
__raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
exynos_cpu_save_register();
@@ -251,12 +254,12 @@ static int exynos_pm_central_resume(void)
* S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
* in this situation.
*/
tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
tmp |= S5P_CENTRAL_LOWPWR_CFG;
__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
/* clear the wakeup state register */
__raw_writel(0x0, S5P_WAKEUP_STAT);
pmu_raw_writel(0x0, S5P_WAKEUP_STAT);
/* No need to perform below restore code */
return -1;
}
@@ -274,13 +277,13 @@ static void exynos_pm_resume(void)
/* For release retention */
__raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
__raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
__raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
__raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
__raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
__raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
__raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
pmu_raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
pmu_raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
pmu_raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
pmu_raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
pmu_raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
pmu_raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
pmu_raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
if (soc_is_exynos5250())
s3c_pm_do_restore(exynos5_sys_save,
@@ -294,7 +297,7 @@ static void exynos_pm_resume(void)
early_wakeup:
/* Clear SLEEP mode set in INFORM1 */
__raw_writel(0x0, S5P_INFORM1);
pmu_raw_writel(0x0, S5P_INFORM1);
return;
}
@@ -338,7 +341,7 @@ static int exynos_suspend_enter(suspend_state_t state)
s3c_pm_restore_uarts();
S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
__raw_readl(S5P_WAKEUP_STAT));
pmu_raw_readl(S5P_WAKEUP_STAT));
s3c_pm_check_restore();
@@ -408,9 +411,9 @@ void __init exynos_pm_init(void)
gic_arch_extn.irq_set_wake = exynos_irq_set_wake;
/* All wakeup disable */
tmp = __raw_readl(S5P_WAKEUP_MASK);
tmp = pmu_raw_readl(S5P_WAKEUP_MASK);
tmp |= ((0xFF << 8) | (0x1F << 1));
__raw_writel(tmp, S5P_WAKEUP_MASK);
pmu_raw_writel(tmp, S5P_WAKEUP_MASK);
register_syscore_ops(&exynos_pm_syscore_ops);
suspend_set_ops(&exynos_suspend_ops);