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drm/i915/psr: Always wait for idle state when disabling PSR

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It should always wait for idle state when disabling PSR because PSR
could be inactive due a call to intel_psr_exit() and while PSR is
still being disabled asynchronously userspace could change the
modeset causing a call to psr_disable() that will not wait for PSR
idle and then PSR will be enabled again while PSR is still not idle.

v2: rebased on top of the patch reusing psr_exit()

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181106190843.18009-2-jose.souza@intel.com
This commit is contained in:
José Roberto de Souza
2018-11-06 11:08:41 -08:00
parent 26f9ec9a9a
commit b2fc2252ce
1 changed files with 18 additions and 23 deletions
Download Patch File Download Diff File Expand all files Collapse all files

41
drivers/gpu/drm/i915/intel_psr.c
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@@ -661,8 +661,12 @@ static void intel_psr_exit(struct drm_i915_private *dev_priv)
{ {
u32 val; u32 val;
if (!dev_priv->psr.active) if (!dev_priv->psr.active) {
if (INTEL_GEN(dev_priv) >= 9)
WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE);
WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
return; return;
}
if (dev_priv->psr.psr2_enabled) { if (dev_priv->psr.psr2_enabled) {
val = I915_READ(EDP_PSR2_CTL); val = I915_READ(EDP_PSR2_CTL);
@@ -680,32 +684,23 @@ static void
intel_psr_disable_source(struct intel_dp *intel_dp) intel_psr_disable_source(struct intel_dp *intel_dp)
{ {
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
i915_reg_t psr_status;
u32 psr_status_mask;
if (dev_priv->psr.active) { intel_psr_exit(dev_priv);
i915_reg_t psr_status;
u32 psr_status_mask;
intel_psr_exit(dev_priv); if (dev_priv->psr.psr2_enabled) {
psr_status = EDP_PSR2_STATUS;
if (dev_priv->psr.psr2_enabled) { psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
psr_status = EDP_PSR2_STATUS;
psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
} else {
psr_status = EDP_PSR_STATUS;
psr_status_mask = EDP_PSR_STATUS_STATE_MASK;
}
/* Wait till PSR is idle */
if (intel_wait_for_register(dev_priv,
psr_status, psr_status_mask, 0,
2000))
DRM_ERROR("Timed out waiting for PSR Idle State\n");
} else { } else {
if (dev_priv->psr.psr2_enabled) psr_status = EDP_PSR_STATUS;
WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE); psr_status_mask = EDP_PSR_STATUS_STATE_MASK;
else
WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
} }
/* Wait till PSR is idle */
if (intel_wait_for_register(dev_priv, psr_status, psr_status_mask, 0,
2000))
DRM_ERROR("Timed out waiting PSR idle state\n");
} }
static void intel_psr_disable_locked(struct intel_dp *intel_dp) static void intel_psr_disable_locked(struct intel_dp *intel_dp)