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sparc64: Make PAGE_OFFSET variable.

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Choose PAGE_OFFSET dynamically based upon cpu type.

Original UltraSPARC-I (spitfire) chips only supported a 44-bit
virtual address space.

Newer chips (T4 and later) support 52-bit virtual addresses
and up to 47-bits of physical memory space.

Therefore we have to adjust PAGE_SIZE dynamically based upon
the capabilities of the chip.

Note that this change alone does not allow us to support > 43-bit
physical memory, to do that we need to re-arrange our page table
support.  The current encodings of the pmd_t and pgd_t pointers
restricts us to "32 + 11" == 43 bits.

This change can waste quite a bit of memory for the various tables.
In particular, a future change should work to size and allocate
kern_linear_bitmap[] and sparc64_valid_addr_bitmap[] dynamically.
This isn't easy as we really cannot take a TLB miss when accessing
kern_linear_bitmap[].  We'd have to lock it into the TLB or similar.

Signed-off-by: David S. Miller <davem@davemloft.net>
Acked-by: Bob Picco <bob.picco@oracle.com>
This commit is contained in:
David S. Miller
2013-09-20 21:50:41 -07:00
parent f998c9c0d6
commit b2d4383480
7 changed files with 139 additions and 30 deletions
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22
arch/sparc/include/asm/page_64.h
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@@ -112,24 +112,16 @@ typedef pte_t *pgtable_t;
#include <asm-generic/memory_model.h>
#define PAGE_OFFSET_BY_BITS(X) (-(_AC(1,UL) << (X)))
extern unsigned long PAGE_OFFSET;
#endif /* !(__ASSEMBLY__) */
/* We used to stick this into a hard-coded global register (%g4)
* but that does not make sense anymore.
/* The maximum number of physical memory address bits we support, this
* is used to size various tables used to manage kernel TLB misses and
* also the sparsemem code.
*/
#define MAX_SUPPORTED_PA_BITS 43
#define PAGE_OFFSET_BY_BITS(X) (-(_AC(1,UL) << (X)))
#define PAGE_OFFSET PAGE_OFFSET_BY_BITS(MAX_SUPPORTED_PA_BITS)
/* The "virtual" portion of PAGE_OFFSET, used to clip off the non-physical
* bits of a linear kernel address.
*/
#define PAGE_OFFSET_VA_BITS (64 - MAX_SUPPORTED_PA_BITS)
/* The actual number of physical memory address bits we support, this is
* used to size various tables used to manage kernel TLB misses.
*/
#define MAX_PHYS_ADDRESS_BITS 41
#define MAX_PHYS_ADDRESS_BITS 47
/* These two shift counts are used when indexing sparc64_valid_addr_bitmap
* and kpte_linear_bitmap.